CN103384913A - 具有中心触点与改进地或电源分布的增强堆叠微电子组件 - Google Patents
具有中心触点与改进地或电源分布的增强堆叠微电子组件 Download PDFInfo
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- CN103384913A CN103384913A CN2011800677685A CN201180067768A CN103384913A CN 103384913 A CN103384913 A CN 103384913A CN 2011800677685 A CN2011800677685 A CN 2011800677685A CN 201180067768 A CN201180067768 A CN 201180067768A CN 103384913 A CN103384913 A CN 103384913A
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Abstract
一种微电子组件700,包括:介电元件730,介电元件730具有至少一个孔733和在其上的导电元件,导电元件包括暴露在介电元件730的第二表面处的端子740;第一微电子元件712,第一微电子元件712具有后表面和面对介电元件730的前表面,第一微电子元件712具有暴露在其前表面处的多个触点;第二微电子元件714,第二微电子元件714具有后表面和面对第一微电子元件712的后表面的前表面,第二微电子元件714具有暴露在该前表面处且突出于第一微电子元件712的边缘之外的多个触点;以及导电平面790,导电平面790附接到介电元件730且至少部分地定位在第一孔733与第二孔739之间,导电平面790与至少一个第一微电子元件712或第二微电子元件714的一个或多个触点电连接。
Description
相关申请的交叉引用
本申请要求2011年9月30日申请的韩国专利申请No.10-1061531的优先权,其公开内容通过引用并入本文。
技术领域
本发明涉及堆叠微电子组件与制造这种组件的方法,以及用于这种组件中的部件。
背景技术
半导体芯片通常设为单独的预封装单元。标准芯片具有带有大的前面的扁平矩形体,该前面具有连接到芯片的内部电路的触点。每个单独的芯片典型地安装在封装中,封装再安装在电路板例如印制电路板上,封装将芯片的触点连接到电路板的导体。在很多常规的设计中,芯片封装在电路板中占用的面积比芯片本身的面积大很多。如参考具有前面的扁平芯片的本公开中所使用的,“芯片的面积”应被理解为指的是所述前面的面积。在“倒装芯片”设计中,芯片的前面面对封装衬底的面,即,通过焊球或其他连接元件将芯片载体与芯片上的触点直接键合到芯片载体的触点。通过覆盖芯片的前面的端子又可以将芯片载体键合到电路板。“倒装芯片”设计提供相对紧凑的布置;每个芯片占用的电路板的面积等于或稍大于芯片的前面的面积,例如在通常指定的美国专利No.5,148,265、5,148,266和5,679,977中的某些实施例中所公开的,其公开内容通过引用并入本文。
某些创新的安装技术提供的紧密度接近或等于常规倒装芯片键合的紧密度。可以在等于或稍大于芯片本身的面积的、电路板的面积中容置单个芯片的封装通常被称为“芯片级封装”。
除了最小化被微电子组件占用的电路板的平面面积,还需要生产一种垂直于电路板平面的整体高度或尺寸较小的芯片封装。这种薄的微电子封装允许将其中安装有封装的电路板紧挨着相邻结构放置,由此使得产品的整体尺寸包含电路板。已经提出用于在单个封装或模块中提供多个芯片的多种提议。在常规的“多芯片模块”中,芯片并排地安装在单个封装衬底上,然后可以将该封装衬底安装至电路板。这种方法只是提供芯片所占用的电路板的总面积的有限减小。总面积仍然大于模块中各个芯片的整体表面积。
还已经提出将多个芯片封装在“堆叠”布置(即多个芯片放置成一个在另一个之上的布置)中。在堆叠布置中,可以将多个芯片安装在比芯片的总面积小的电路板的面积中。例如,在上述的美国专利No.5,679,977、5,148,265以及5,347,159的某些实施例中公布了一些堆叠芯片布置,其公开内容通过引用并入本文。也通过引用并入本文的美国专利No.4,941,033公开一种布置,其中芯片一个在另一个之上地堆叠,且通过与芯片相关联的所谓的“布线膜”上的导体彼此互连。
除了现有技术的这些努力,将需要在用于具有基本位于芯片的中心区域的触点的芯片的多芯片封装的情况下的进一步改进。某些半导体芯片,例如一些存储芯片,通常具有基本沿芯片的中心轴设置的一行或两行触点。
发明内容
本发明涉及一种微电子组件。在一个实施例中,所述微电子组件包括:介电元件,所述介电元件具有至少一个孔和在其上的导电元件,所述导电元件包括暴露在所述介电元件的第二表面处的端子;第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的前表面,所述第一微电子元件具有暴露在其前表面处的多个触点;第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件具有暴露在所述前表面处且突出于所述第一微电子元件的边缘之外的多个触点;以及导电平面,所述导电平面附接到所述介电元件且至少部分地定位在所述第一孔与第二孔之间,所述导电平面与所述第一微电子元件或所述第二微电子元件的至少一个的一个或多个触点电连接。可以将整个导电平面定位在所述第一孔与第二孔之间。所述导电平面可以是电源平面或地平面。导电电位平面的部分可以延伸至所述第一孔和第二孔的外边缘之外的位置。所述导电平面可以包括彼此间隔开的至少两个平面部分。所述两个平面部分可以包括:电源平面部分,所述电源平面部分与至少一个所述第一微电子元件或第二微电子元件的至少一些电源触点电连接;以及地平面部分,所述地平面部分与一个或多个所述第一微电子元件或第二微电子元件的触点电连接。所述导电平面可以与所述第一微电子元件的一个或多个触点电联接。所述导电平面可以与所述第二微电子元件的一个或多个触点电联接。
在另一个实施例中,所述微电子组件包括:介电元件,所述介电元件具有相对地面对的第一表面和第二表面以及在所述第一表面与第二表面之间延伸的第一孔和第二孔,所述介电元件进一步具有在其上的多个导电元件;第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的前表面,所述第一微电子元件具有暴露在其前表面处的多个触点;第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的后表面的前表面,所述第二微电子元件具有暴露在所述前表面处并突出于所述第一微电子元件边缘之外的多个触点;信号引线,所述信号引线与一个或多个微电子元件连接并延伸穿过所述一个或多个第一孔或第二孔到达所述介电元件上的一些所述导电元件;以及一个或多个跳线,所述一个或多个跳线延伸穿过所述第一孔并与所述第一微电子元件的触点连接,所述一个或多个跳线跨越所述第二孔并与所述介电元件上的导电元件连接。
在又另一个实施例中,所述微电子组件包括:介电元件,所述介电元件具有相对地面对的第一表面和第二表面以及在所述第一表面与第二表面之间延伸的第一孔和第二孔,所述介电元件进一步具有在其上的多个导电元件;第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的前表面,所述第一微电子元件具有暴露在其前表面处的多个触点;第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件具有暴露在所述前表面处且突出于所述第一微电子元件的边缘之外的多个触点;信号引线,所述信号引线与一个或多个微电子元件连接,并延伸穿过一个或多个所述第一孔或第二孔到达所述介电元件上的一些导电元件;以及一个或多个跳线,所述一个或多个跳线跨越至少一个所述第一孔或第二孔,并与所述介电元件上的导电元件连接。所述微电子组件可以进一步包括密封剂,所述密封剂设置在所述第一孔中,且覆盖所述信号引线和一个或多个跳线。所述跳线可以包括延伸的跳线,所述延伸的跳线从所述第一孔的一侧上的导电元件延伸,跨过所述第一孔,跨过所述第一孔与第二孔之间的部分的所述第二表面,并穿过所述第二孔,到达所述微电子元件中的一个。所述第一孔与第二孔可以具有细长的形状,并彼此基本平行地延伸。所述介电元件上的所述导电元件包括可以暴露在所述介电元件的所述第二表面处的端子。
在进一步实施例中,所述微电子组件包括:介电元件,所述介电元件具有相对地面对的第一表面和第二表面以及在所述第一表面与第二表面之间延伸的一个或多个孔,所述介电元件进一步具有在其上的导电元件;第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的所述第一表面的前表面,所述第一微电子元件具有第一边缘以及暴露在所述第一微电子元件的所述前表面处的多个触点;第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件的所述前表面的突出部分延伸到所述第一微电子元件的所述第一边缘之外,所述突出部分与所述介电元件的所述第一表面间隔开,所述第二微电子元件具有暴露在所述前表面的所述突出部分处的多个触点;引线,所述引线从所述微电子元件的触点延伸穿过所述至少一个孔到达至少一些所述导电元件;以及第一无源部件,所述第一无源部件设置在所述第二微电子元件的所述前表面的所述突出部分与所述介电元件的所述第一表面之间。所述微电子组件可以进一步包括第二无源部件,所述第二无源部件暴露在介电组件的所述第二表面上且位于两个孔之间。所述微电子组件可以进一步包括从所述第一无源部件延伸至所述微电子元件中的一个的触点的引线。所述介电元件可以包括暴露在所述第二表面上的多个端子,每个端子与电路板电联接。焊球可以将每个端子连接至所述电路板。铜柱可以将每个端子连接至所述电路板。每个端子可以与所述第一微电子元件连接。每个端子可以与所述第一微电子元件和第二微电子元件连接。
附图说明
图1是根据本发明实施例的堆叠微电子组件的示意性截面正视图;
图2是图1中的堆叠组件的仰视图;
图2A是示出此处的实施例中的微电子组件的变型中的键合元件之间的连接的不完整的局部剖视图;
图2B是示出此处的实施例中的微电子组件的变型中的键合元件之间的连接的不完整的局部剖视图;
图2C是示出此处的实施例中的微电子组件的变型中的键合元件之间的连接的不完整的局部剖视图;
图2D是示出此处的实施例中的微电子组件的变型中的键合元件之间的连接的不完整的局部剖视图;
图3是根据本发明的另一实施例的堆叠微电子组件的示意性截面正视图;
图4是根据本发明的另一实施例的堆叠微电子组件的示意性截面正视图;
图5是图4中的堆叠组件的仰视图;
图6是堆叠微电子组件的另一实施例的示意性剖视图;
图7是堆叠微电子组件的又另一实施例的示意性剖视图;
图8是图7中的堆叠微电子组件的仰视图;
图9是根据本发明的另一实施例的堆叠微电子组件的仰视图;
图10是堆叠微电子组件的另一实施例的示意性剖视图;
图11是图10中的堆叠微电子组件的仰视图;
图12是根据本发明的另一实施例的堆叠微电子组件的仰视图;
图13是根据本发明的一个实施例的系统的示意图;以及
图14是与电路板电联接的堆叠微电子组件的实施例的示意性剖视图。
具体实施方式
参考图1,根据本发明实施例的堆叠微电子组件10包括第一微电子元件12与第二微电子元件14。在一些实施例中,第一微电子元件12与第二微电子元件14可以是半导体芯片、晶片等。
第一微电子元件12具有前表面16、远离前表面16的后表面18、以及在前表面与后表面之间延伸的第一边缘27与第二边缘29。第一微电子元件12的前表面16包括第一端区域15与第二端区域17以及位于第一端区域15与第二端区域17之间的中心区域13。第一端区域15在中心区域13与第一边缘27之间延伸,第二端区域17在中心区域13与第二边缘29之间延伸。电触点20暴露在第一微电子元件12的前表面16处。如在本发明中所使用的,导电元件“暴露在”结构的表面处的表述表示该导电元件可用于与沿垂直于该表面的方向从该结构外向表面移动的理论点接触。因此,暴露在结构的表面处的端子或其他导电元件可从这样的表面突出;可与这样的表面平齐;或者可相对于这样的表面凹入并通过结构中的孔或凹入部暴露。第一微电子元件12的触点20暴露在中心区域13中的前表面16处。例如,触点20可以布置成与第一表面16的中心相邻的一列或平行的两列。
第二微电子元件14具有前表面22、远离前表面22的后表面24、以及在前表面与后表面之间延伸的第一边缘35与第二边缘37。第二微电子元件14的前表面22包括第一端区域21与第二端区域23以及位于第一端区域21与第二端区域23之间的中心区域19。第一端区域21在中心区域19与第一边缘35之间延伸,第二端区域23在中心区域19与第二边缘37之间延伸。电触点26暴露在第二微电子元件14的前表面22处。第二微电子元件14的触点26暴露在中心区域19中的前表面22处。例如,触点26可以布置成与第一表面22的中心相邻的一列或平行的两列。
如图1所示,第一微电子元件12与第二微电子元件14相对于彼此堆叠。在一些实施例中,第二微电子元件14的前表面22与第一微电子元件12的后表面18彼此面对。第二微电子元件14的至少部分的第二端区域23覆盖第一微电子元件12的至少部分的第二端区域17。第二微电子元件14的中心区域19的至少部分突出到第一微电子元件12的第二边缘29之外。因此,第二微电子元件14的触点26定位在第一微电子元件12的第二边缘29之外的位置。
微电子组件10进一步包括介电元件30,介电元件30具有相对地面对的第一表面32与第二表面34。虽然图1只示出一个介电元件30,但是微电子组件10可以包括多于一个介电元件。一个或多个导电元件或端子36暴露在介电元件30的第一表面32处。至少一些端子36可以是相对于第一微电子元件12和/或第二微电子元件14可移动的。
介电元件30可以进一步包括一个或多个孔。在图1所示的实施例中,介电元件30包括与第一微电子元件12的中心区域13基本对齐的第一孔33和与第二微电子元件14的中心区域19基本对齐的第二孔39,由此提供通向触点20和26的通路。
如图1所示,介电元件30可以延伸到第一微电子元件12的第一边缘27和第二微电子元件14的第一边缘35之外。介电元件30的第二表面34可以与第一微电子元件12的第一表面16并置。介电元件30可以部分地或全部地由任意适当的介电材料制成。例如,介电元件30可以包括柔性材料层,例如聚酰亚胺层、BT树脂层或通常用于制作带式自动键合(“TAB”)带的其他介电材料层。可选地,介电元件30可以包括相对坚硬的板状材料,例如纤维增强环氧的厚层,例如FR-4板或FR-5板。不论使用何种材料,介电元件30可以包括单个或多个介电材料层。
介电元件30还可以包括在第一表面32上暴露的导电元件40与导电迹线42。导电迹线42将导电元件40与端子36电联接。
间隔层31,例如粘合剂层,可以定位在第二微电子元件14的第一端区域21与部分的介电元件30之间。如果间隔层31包括粘合剂,该粘合剂可以将第二微电子元件14附接到介电元件30上。另一间隔层60可以定位在第二微电子元件14的第二端区域23与第一微电子元件12的第二端区域17之间。这个间隔层60可以包括用于将第一微电子元件12与第二微电子元件14粘合在一起的粘合剂。在这种情况下,间隔层60可以部分地或全部地由管芯附接粘合剂制成,并且可以包括低弹性模量材料,例如硅酮弹性体。然而,如果两个微电子元件12和14是由相同的材料形成的常规的半导体芯片,间隔层60也可以全部地或部分地由高弹性模量粘合剂或焊料的薄层构成,因为微电子元件响应于温度变化将一致地膨胀或收缩。不管使用什么材料,间隔层31与60中的每一个可以包括单个层或多个层。
如图1与图2所示,电连接或引线70将第一微电子元件12的触点20与一些导电元件40电连接。电连接70可以包括多个线键合72、74。线键合72、74延伸穿过第一孔33,且彼此基本平行地定向。线键合72和74中的每一个将触点20与介电元件的对应元件40电联接。根据该实施例的多线键合结构通过为在连接的触点之间流动的电流提供额外的路径,可以基本减小线键合连接的电感。
其他电连接或引线50将第二微电子元件14的触点26与一些元件40电联接。电连接50可以包括多个线键合52、54。线键合52、54延伸穿过第二孔39,且彼此基本平行地定向。线键合52和54中的每一个将触点26与介电元件30的对应元件40电联接。根据本实施例的多键合线结构通过为在连接的触点之间流动的电流提供额外的路径,可以基本减小线键合连接的电感。
如图2A所示,在电连接70中,第一键合线52可以具有与芯片触点20合金化结合的端部52A以及与导电元件40合金化结合的另一端部(未示出)。例如,键合线可以包括使用超声能、热或两者可以将其焊接到触点以与触点形成合金化接合部或键合的金属,例如金。相反地,第二键合线54可以具有合金化键合到第一键合线52的端部52A的一个端部54A以及合金化键合到第一键合线52的端部的相对的端部(未示出)。
第二键合线54无需接触与第一键合线52合金化键合的导电元件140。代替地,在特定实施例中,第二键合线54的端部54A可以这样的方式合金化键合到第一键合线52的端部52A:第二键合线不接触第二键合线的至少一个端部处的触点,并可以不接触任一端部处的触点。
每个键合线52、54的端部52A、54A可以包括在线键合工艺中形成的球。线键合工具典型地通过将金线的尖端从线轴推进到工具的尖端而操作。在处理的一个示例中,当工具在用于在第一触点(例如,芯片触点20)处形成第一线键合的位置时,工具可以对线施加超声能、热或二者直到线的尖端熔化并形成球。然后加热的球与触点的表面合金化键合。然后,当线键合工具的尖端从第一触点移开时,球仍然与触点键合,而这个触点与第二触点之间的键合线的长度放松(paid out)。然后,键合工具可以将线的第二端部附接到第二触点,从而在这个端部与第二触点形成合金化接合部。
然后可以以稍微不同的方式重复上述工艺以形成第二键合线。在这种情况下,线键合工具可以移动到某个位置,然后可以用于加热线的尖端以形成球,然后球将第二键合线的端部54A合金化结合到第一键合线的端部52A。然后,线键合工具可以将键合线的另一端部附接到第一键合线的第二端部,从而在这个端部与至少第一键合线形成合金化接合部。
导电元件52、54中的一些可以承载信号,即,随时间变化并典型地传递信息的电压或电流。例如,信号的例子是,但不限于:随时间变化并代表状态、变化、量度、时钟或定时输入、控制或反馈输入的电压或电流。其他的导电元件52、54可以提供与地或电源电压的连接。与地或电源电压的连接典型地提供在对电路的操作重要的频率上随时间至少相当稳定的电压。当连接是与地或电源电压的连接时,各个触点对之间的双线或多线键合连接可以是特别有利的。在一个示例中,双线连接72、74与52、54可以将各个微电子元件12、14连接至介电元件30上的地端子。类似地,双线键合连接72A、74A以及52A、54A可以将各个微电子元件连接至介电元件上的电源端子(用于通过电路板与电源进一步互连,未示出)。增加这些与地端子或电源端子的连接中的线键合的数量可以减小地与电源电路中的电感,这可以帮助减少系统中的噪音。
根据该实施例的多键合线结构与方法的另一个可能的益处是,当用于将键合线附接到触点(例如芯片或衬底上的键合焊盘)的面积有限时减小电感。一些芯片具有特别高的触点密度与细小间距。这种芯片上的键合焊盘具有非常有限的面积。第二键合线具有附接到第一键合线的端部的端部但本身不接触触点的结构可以实现双键合线或多键合线结构,而不需要增加键合焊盘的尺寸。因此,即使在形成与以细小间距布置的触点或具有小面积的触点的线键合连接时,仍然可以实现关于图2A描述的多键合线结构。
而且,具有高密度的一些微电子元件还具有高输入和输出速率,即高频率,以该高频率将信号传输到芯片上或从芯片传输出。在足够高的频率,可以大幅地增加连接的电感。根据该实施例的多键合线结构通过为在连接的触点之间流动的电流提供额外的路径,可以大幅地减小用于地、电源或信号传输的线键合连接的电感。
图2B示出第一键合线51与第二键合线53之间在其端部处的连接。如图4所示,在键合线的第一端部处,球51A与53A可以合金化结合在一起,但是以这样的方式合金化结合在一起:第二线53的球不接触触点20。在第二触点40处的键合线的第二端部51B、53B处,可以在线之间形成电连接,而不在第二端部51B、53B处形成球。在这种情况下,触点20与40中的一个可以是暴露在芯片的表面处的芯片触点,触点20与40中的另一个可以是暴露在衬底的表面处的衬底触点。如图2B进一步所示,第二线键合的第二端部53B在51B处与第一键合线结合,而第二键合线不接触触点40。
图2C示出上述实施例(图2B)的变型,其中第一键合线55具有与第一触点20结合的球端55A。第二键合线57的线端57B合金化结合到第一触点20上方的第一键合线的球端55A。另外,第二键合线57的球端57A合金化结合到在第二触点40处的第一键合线55的线端55B。如果需要,可以使用以这种方式与其他键合线合金化结合的甚至更大数量的键合线,以便为在一对触点之间流动的电流提供平行的电路径。
图2D示出其中使用键合带41代替键合线的电连接,其中键合带41具有合金化结合到触点中的一个(例如,触点20)的第一端部43。键合线41具有合金化结合到另一触点40的中间部分45,以及具有与键合带的第一端部43结合的第二端部47。键合带的第一端部43和第二端部47之间的结合可以为使得第二端部47不接触与第一端部结合的触点20。可选地,在一种变型(未示出)中,第二端部47可以接触或直接结合到与第一端43结合的相同的触点20。触点中的一个(例如,触点20、40中的一个)可以是衬底触点,触点20、40中的另一个可以是芯片触点。可选地,触点20、40都可以是在衬底的表面处暴露的衬底触点,或者触点20、40都可以是在芯片的表面处暴露的芯片触点。
如图1进一步所示,微电子组件10还可以包括第一密封剂80与第二密封剂82。第一密封剂80覆盖电连接70和介电元件30的第一孔33。第二密封剂82覆盖电连接70和介电元件30的第二孔39。
微电子组件10可以进一步包括多个结合单元,例如焊球81。焊球81附接到端子36,并因此与元件40、引线50和70以及触点20和26中的至少一些电互连。
如图3所示,多个无源电路元件,即,“无源器件”590A可以设置在或附接到第一孔533与第二孔539之间的介电元件530的第一表面532。无源器件590A可以是电容、电阻、电感等。一个或多个无源器件可以与介电元件上的一个或多个导电元件电互连,或与一个或两个微电子元件的一个或多个触点520、526电互连。一个或多个无源器件可以与微电子元件触点520或526以及介电元件的触点540电互连。可选地,或除此之外,可以在介电元件530的第二表面534与第二微电子元件514的前表面522之间设置多个无源器件590B。如无源器件590A的情况,这些无源器件590B可以与微电子元件512、514的任一个或全部或介电元件530电互连。在特定实施例中,无源器件590A或590B的至少一些是去耦电容,在一个示例中,去耦电容可以连接至微电子组件512或514的“电源”触点、或者介电元件530或者微电子组件512或514的“电源”触点和介电元件530,从而将来自电源的动力输入到微电子元件。
图4-6示出图1中所示的实施例的变型。在这个变型中,介电元件630包括多个孔。尽管图5示出具有四个孔的介电元件630,但是介电元件630可以包括更多或更少的孔。在图5所示的特定实施例中,介电元件630包括两个孔633a与633b,孔633a与633b在堆叠微电子组件600的第一方向622上可以相对于彼此基本对齐。孔633a与633b可以具有相似的形状和尺寸或者可以具有不同的尺寸或形状。例如,图13中示出的孔633a与633b中的每一个具有大体矩形的横截面与基本相似的尺寸。不论孔633a与633b的形状如何,第一微电子元件612的触点620都在孔633a与633b中暴露。
介电元件630可以进一步具有孔639a与639b,第二微电子元件614的触点626可以在孔639a与639b中暴露。孔639a与639b也可以相对于彼此基本对齐。在图5所示的实施例中,孔639a比孔639b大,且两个孔都具有大体矩形的形状。
堆叠微电子组件600包括多个迹线。在一个特定实施例中,导电迹线624a可以在沿着孔633a与633b之间的介电元件的表面632的方向上延伸。在一个实施例中,迹线624a可以具有延伸至在迹线的长度的方向上在孔633a的边缘664a、664b之外的、介电元件630的位置636的长度。如图5所示,导电结构如介电元件630的端子636可以通过迹线642a互连。另一迹线642b可以定位在孔639a与639b之间且可以具有延伸至孔639a与639b的边缘668a、668b之外的位置的长度。其他导电结构如介电元件630的端子636可以通过迹线642b互连。
堆叠微电子组件600包括适于传输信号的多个导电元件,例如,可以是线键合或其他适当的结构的信号引线。在图4示出的实施例中,信号引线652延伸穿过孔633a,并将第一微电子元件614的触点620与邻近孔633a的衬底触点652电联接。另一信号引线654延伸穿过孔633a,并将第一微电子元件612的触点620和邻近孔633a的衬底触点640互连。如图5所示,另一信号引线656将第一微电子元件的触点620电连接至与孔639a相邻的衬底触点640。信号引线656延伸跨过孔639a的宽度。
连接至第二微电子元件614的触点626的信号引线672延伸跨过孔633b的宽度,并与孔633b的遥远边缘之外的衬底触点640电联接。另一信号引线674延伸穿过孔639a,并将第二微电子元件614的触点626与邻近孔639b的、介电元件的中心部分中的衬底触点640互连。类似地,信号引线676延伸穿过孔639a,且将第二微电子元件614的触点626与邻近孔639b的衬底触点640电联接。
如图5与图6所示,堆叠微电子组件600可以进一步包括信号引线678,信号引线678延伸跨过孔639a的宽度,并将定位在孔639的相对侧上的两个衬底触点640互连。另一信号引线679延伸跨过孔633a或633b的宽度,且将位于这个孔633a或633b的相对侧上的两个衬底触点640互连。密封剂可以覆盖所有信号引线和孔633a、633b、639a和639b。
图7与图8示出图1中示出的实施例的变型。在这个变型中,堆叠微电子组件700包括设置在介电元件730的第一表面732上的导电地平面和/或电源平面790(即,用于连接至参考电位的金属平面)。可选地,导电平面790可以设置在介电元件730的第二表面734上。延伸穿过孔733的一个或多个线键合752可以将第一微电子元件712的触点720与地平面和/或电源平面390电连接。密封剂780可以覆盖孔733。类似地,延伸穿过孔739的一个或多个线键合762可以将第二微电子元件714的触点726与地平面和/或电源平面790电连接。密封剂782可以覆盖孔739。地平面和/或电源平面790可以定位在介电元件730的两个孔733与739之间,且平面790的至少部分可以延伸穿过密封剂780和782。在一个实施例中,导电地平面和/或电源平面790可以是单片结构,如图8所示。
微电子组件700可以进一步包括与导电平面790电联接的无源器件792。特别地,无源器件792可以具有安装至导电平面790的电极。无源器件792可以是一个或多个电容、电阻、电感等。例如,无源器件792可以是用于有效地保持恒定的输出电压的一个或多个去耦电容。在一个特定实施例中,去耦电容可以具有安装至导电平面790的电极以及远离导电平面的暴露电极。去耦电容可以存储电能,以及在电压突降的情况下,可以为保持恒定的输出电压所必需的电流提供能量。
微电子组件700可以额外地或可选地包括无源器件793,无源器件793具有与导电平面790连接的一个电极以及与衬底上的导电焊盘795连接的另一个电极。迹线797可以从焊盘795延伸并连接至端子740。例如,当导电平面用作将与地连接的地平面时,端子740可以用于连接至电源。可选地,焊盘795或迹线797可以与通路连接,从而与远离表面732(导电平面设置在表面732上)的介电元件的表面上的另一金属层或导电特征连接。
如图9所示,地平面或电源平面可以是沿介电材料830的表面间隔开的两个或更多个分离的平面部分。一个或多个电源平面部分或地平面部分可被暴露以使用介电材料上的一个或多个触点与第一微电子元件或第二微电子元件的一个或多个触点互连,如上面的图9所示。在图9示出的实施例中,地平面和/或电源平面790包括两个分离的部分790A与790B。部分790A与790B中的一个可以是电源平面部分,另一个可以是地平面部分。在另一个示例中,部分790A与790B都可以是电源平面部分,例如,用于与在相同或不同电压下输入的多于一个电源连接。在另一个示例中,平面部分790A与790B都可以是地平面部分。
如图9进一步所示,在第一微电子元件712或第二微电子元件714的触点720与地平面和/或电源平面790之间可以连接双线键合752A和752B。双线键合可以如关于图2A-2D所讨论地配置。线键合752A与752B可以连接在地平面和/或电源平面790的不同位置。可选地,双线键合751A与751B可以连接在地平面和/或电源平面790的单个位置。
图10与图11示出图7与图8中示出的实施例的变型。在这个变型中,堆叠微电子组件800包括居中地位于介电元件830上的导电地平面和/或电源平面890(即,电位平面)。地平面和/或电源平面890特别地附接到介电元件830的第一表面832。地平面和/或电源平面890的中心部分892定位在介电元件830的孔833与839之间。地平面和/或电源平面890还包括与中心部分892相邻的第一端部分894与第二端部分896。地平面和/或电源平面的第一端部分894与第二端部分896延伸到孔833与839的边界之外。因此,地平面和/或电源平面890可以围绕孔833与839。一个或多个线键合852可以将地平面或电源平面890电连接到第一微电子元件812的一个或多个触点820。类似地,一个或多个线键合872可以将地平面或电源平面890电连接到第二微电子元件814的一个或多个触点826。如图11所示,地平面或电源平面890可以是单片结构。
微电子组件800可以包括一个或多个无源器件871与873。无源器件871可以电容,该电容的一个电极安装至导电平面890,另一个电极连接到焊盘873。焊盘可以进一步如以上关于图7所描述地电连接。
无源器件873可以具有电连接到第一焊盘883的一个电极以及电连接到第二焊盘885的另一个电极。第一迹线889可以将第一焊盘883与导电平面890导电连接。第二迹线891可以将第二焊盘885连接到介电元件上的端子、或者将进一步与微电子元件连接(例如,通过线键合(未示出))的触点、或者两者。
如图12所示,地平面和/或电源平面可以是沿介电元件830的表面彼此间隔开的分离的平面部分。在图12所示的实施例中,地平面或电源平面890包括彼此间隔开的两个分离的平面部分890A与890B,一个平面部分是用于连接到电源的电源平面,另一个平面部分是用于连接到地的地平面,例如,通过平面部分与待连接到组件的电路板(未示出)之间的电连接而连接到地。在这个实施例中,无源器件895可以是电容。在这种情况下,无源器件895可以具有安装至平面部分890A(例如,电源平面)的电极以及安装至平面部分890B(例如,地平面)的另一电极,以便电容电极电连接在电源平面与地平面之间。
上述微电子组件可以用于构建不同的电子系统,如图13所示。例如,根据本发明的进一步实施例的系统1100包括与其他电子部件1108与1110结合的上述微电子组件1106。在示出的示例中,部件1108是半导体芯片,而部件1110是显示屏,但是可以使用任何其他部件。当然,尽管为了说明的清楚在图13中只示出了两个额外的部件,系统可以包括任何数量的这种部件。微电子组件1106可以是上述组件的任一个。在进一步变型中,可以使用任何数量的这种微电子组件。微电子组件1106以及部件1108和1110安装在共用壳体901(以虚线示意性地示出)中,并在必要时彼此电互连以形成所需的电路。在所示的示例性系统中,系统包括电路板1102例如柔性印刷电路板,电路板包括将部件彼此互连的很多个导体1104,图13只示出其中一个导体。然而,这只是示例性的;可以使用用于制作电连接的任何适当的结构。壳体901作为在例如移动电话或个人数字助理中可用的类型的便携式壳体被示出,屏1110暴露在壳体的表面处。在结构1106包括感光元件如成像芯片的情况下,还可以设置透镜1111或其他光学装置用于将光导向到结构。此外,图13所示的简化的系统仅仅是示例性的;可以使用上述的结构形成其他系统,包括通常被认为是固定结构的系统,例如台式电脑、路由器等。
如图14所示,上述的微电子组件中的任一个可以电联接到电路板或线路板1200。例如,微电子组件10可以包括多个结合单元,例如焊球81或铜柱。焊球81将微电子组件10电连接到电路板1200。虽然图14只示出将微电子组件10连接到电路板1200的焊球81,可以预计任何导电元件可以将电路板1200与微电子组件10互连。一个或多个导电元件或端子1202暴露在电路板1200的第一表面1204处。电路板1200的第一表面1204面对焊球81。焊球81附接到端子1202,由此与电路板1200中的至少一些电路电互连。
尽管此处已经参考特定实施例对本发明进行了描述,应该理解的是这些实施例仅仅是对本发明的原理和应用的说明。因此,应理解的是,在不脱离通过所附权利要求限定的本发明的精神和范围的情况下,可以对上述说明性实施例进行各种修改以及可以设计其他布置。
应理解的是,此处阐述的各个从属权利要求与特征可以与原始权利要求呈现的方式不同的方式组合。还应理解的是,结合各个实施例描述的特征可与所述实施例的其他特征共享。
Claims (60)
1.一种微电子组件,包括:
介电元件,所述介电元件具有相对地面对的第一表面与第二表面以及在所述第一表面与所述第二表面之间延伸的第一孔与第二孔,所述介电元件进一步具有在其上的多个导电元件;
第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的前表面,所述第一微电子元件具有暴露在其前表面处的多个触点;
第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件具有暴露在所述前表面处且突出于所述第一微电子元件的边缘之外的多个触点;
信号引线,所述信号引线连接到一个或多个所述微电子元件,且延伸穿过所述第一孔至所述介电元件上的一些所述导电元件;以及
导电平面,所述导电平面附接到所述介电元件,且至少部分地定位在所述第一孔与所述第二孔之间,所述导电平面与至少一个所述第一微电子元件或所述第二微电子元件的一个或多个所述触点电连接。
2.根据权利要求1所述的微电子组件,其中整个所述导电平面定位在所述第一孔与所述第二孔之间。
3.根据权利要求1所述的微电子组件,其中所述导电平面是电源平面。
4.根据权利要求1所述的微电子组件,其中所述导电平面是地平面。
5.根据权利要求1所述的微电子组件,其中所述导电平面的部分延伸至所述第一孔与所述第二孔的外边缘之外的位置。
6.根据权利要求1所述的微电子组件,其中导电平面包括彼此间隔开的至少两个平面部分。
7.根据权利要求6所述的微电子组件,其中所述至少两个平面部分包括:电源平面部分,所述电源平面部分电连接到至少一个所述第一微电子元件或所述第二微电子元件的至少一些电源触点;以及地平面部分,所述地平面部分电连接到一个或多个所述第一微电子元件或所述第二微电子元件的触点。
8.根据权利要求1所述的微电子组件,其中所述导电平面电联接到所述第一微电子元件的一个或多个触点。
9.根据权利要求1所述的微电子组件,其中所述导电平面电联接到所述第二微电子元件的一个或多个触点。
10.根据权利要求1所述的微电子组件,进一步包括双线键合,所述双线键合连接在所述导电平面与至少一个所述第一微电子元件或所述第二微电子元件的触点之间。
11.一种根据权利要求1所述的微电子组件,进一步包括:
至少一个无源部件,所述至少一个无源部件暴露在所述介电组件的所述第二表面处,且位于所述第一孔与所述第二孔之间。
12.根据权利要求11所述的微电子组件,其中所述至少一个无源部件电连接到所述第一微电子元件。
13.根据权利要求12所述的微电子组件,其中所述至少一个无源部件电连接到所述第一微电子元件和所述第二微电子元件。
14.根据权利要求11所述的微电子组件,其中所述至少一个无源部件具有安装在所述导电平面且与所述导电平面电联接的电极。
15.根据权利要求14所述的微电子组件,其中所述至少一个无源部件是具有远离所述导电平面的第二电极的电容。
16.根据权利要求11所述的微电子组件,其中所述至少一个无源部件包括至少一个电容,所述至少一个电容具有与用于连接到电源或地的导电端子连接的电极。
17.根据权利要求11所述的微电子组件,其中所述导电平面为第一导电平面,所述微电子组件进一步包括第二导电平面,所述第二导电平面覆盖所述介电元件的所述第二表面,用于分别连接电源和地,以及所述至少一个无源部件具有分别与所述第一导电平面和所述第二导电平面电连接的第一电极和第二电极。
18.根据权利要求17所述的微电子组件,其中所述至少一个无源部件为电容。
19.根据权利要求1所述的微电子组件,其中所述信号引线为线键合。
20.根据权利要求11所述的微电子组件,其中所述信号引线为引线键合。
21.一种系统,包括根据权利要求1所述的组件以及与所述组件电连接的一个或多个其他电子部件。
22.一种系统,包括根据权利要求11所述的组件以及与所述组件电连接的一个或多个其他电子部件。
23.一种根据权利要求21所述的系统,进一步包括壳体,所述组件与所述其他电子部件安装至所述壳体。
24.一种根据权利要求22所述的系统,进一步包括壳体,所述组件与所述其他电子部件安装至所述壳体。
25.一种微电子组件,包括:
介电元件,所述介电元件具有相对地面对的第一表面与第二表面以及在所述第一表面与所述第二表面之间延伸的第一孔与第二孔,所述介电元件进一步具有在其上的多个导电元件;
第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的前表面,所述第一微电子元件具有暴露在其前表面处的多个触点;
第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件具有暴露在所述前表面处且突出于所述第一微电子元件的边缘之外的多个触点;
信号引线,所述信号引线与一个或多个所述微电子元件连接,并延伸穿过所述一个或多个所述第一孔或所述第二孔至所述介电元件上的一些所述导电元件;以及
一个或多个跳线,所述一个或多个跳线延伸穿过所述第一孔并连接到所述第一微电子元件的触点,所述一个或多个跳线跨越所述第二孔并与所述介电元件上的导电元件连接。
26.根据权利要求25所述的微电子组件,其中所述信号引线为线键合。
27.根据权利要求25所述的微电子组件,其中所述跳线为线键合。
28.一种包括根据权利要求25所述的组件的系统,进一步包括与所述组件电连接的一个或多个其他电子部件。
29.一种根据权利要求28所述的系统,进一步包括壳体,所述组件与所述其他电子部件安装至所述壳体。
30.权利要求25所述的微电子组件,进一部包括第二跳线,所述第二跳线从所述第一孔的一侧上的导电元件延伸,跨过所述第一孔,跨过在所述第一孔与所述第二孔之间的部分的所述第二表面,并穿过所述第二孔,到达所述微电子元件中的一个。
31.一种微电子组件,包括:
介电元件,所述介电元件具有相对地面对的第一表面与第二表面以及在所述第一表面与所述第二表面之间延伸的第一孔与第二孔,所述介电元件进一步具有在其上的多个导电元件;
第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的前表面,所述第一微电子元件具有暴露在其前表面处的多个触点;
第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件具有暴露在所述前表面处且突出于所述第一微电子元件的边缘之外的多个触点;
信号引线,所述信号引线与一个或多个所述微电子元件连接,并延伸穿过一个或多个所述第一孔或第二孔至所述介电元件上的一些所述导电元件;以及
一个或多个跳线,所述一个或多个跳线跨越所述第一孔与所述第二孔并与所述介电元件上的导电元件连接。
32.根据权利要求31所述的微电子组件,进一步包括密封剂,所述密封剂放置在所述第一孔中且覆盖所述信号引线和所述一个或多个跳线。
33.根据权利要求31所述的微电子组件,进一步包括第二跳线,所述第二跳线从所述第一孔的一侧上的导电元件延伸,跨过所述第一孔,跨过在所述第一孔与所述第二孔之间的部分的所述第二表面,且穿过所述第二孔,到达所述微电子元件中的一个。
34.根据权利要求33所述的微电子组件,其中所述第一孔与所述第二孔具有细长的形状且彼此基本平行地延伸。
35.根据权利要求31所述的微电子组件,其中所述介电元件上的所述导电元件包括暴露在所述介电元件的所述第二表面处的端子。
36.根据权利要求31所述的微电子组件,其中所述信号引线为线键合。
37.根据权利要求31所述的微电子组件,其中所述跳线为线键合。
38.一种包括根据权利要求31所述的组件的系统,进一步包括与所述组件电连接的一个或多个其他电子部件。
39.一种根据权利要求38所述的系统,进一步包括壳体,所述组件和所述其他电子部件安装至所述壳体。
40.一种微电子组件,包括:
介电元件,所述介电元件具有相对地面对的第一表面与第二表面以及在所述第一表面与所述第二表面之间延伸的一个或多个孔,所述介电元件进一步具有在其上的导电元件;
第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的所述第一表面的前表面,所述第一微电子元件具有第一边缘和暴露在其前表面处的多个触点;
第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件的所述前表面的突出部分延伸到所述第一微电子元件的所述第一边缘之外,所述突出部分与所述介电元件的所述第一表面间隔开,所述第二微电子元件具有暴露在所述前表面的所述突出部分处的多个触点;
引线,所述引线从所述微电子元件的触点延伸穿过所述至少一个孔,到达至少一些所述导电元件;以及
第一无源部件,所述第一无源部件设置在所述第二微电子元件的所述前表面的所述突出部分与所述介电元件的所述第一表面之间。
41.根据权利要求40所述的微电子组件,其中所述一个或多个孔为两个孔,所述微电子组件进一步包括第二无源部件,所述第二无源部件暴露在所述介电组件的所述第二表面处且位于所述两个孔之间。
42.根据权利要求40所述的微电子组件,进一步包括从第一无源部件延伸至所述微电子元件中的一个的触点的引线。
43.根据权利要求40所述的微电子组件,进一步包括电路板,其中所述介电元件包括暴露在所述第二表面处并与所述电路板电联接的多个端子。
44.根据权利要求43所述的微电子组件,其中焊球将每个端子连接到所述电路板。
45.根据权利要求43所述的微电子组件,其中铜柱将每个端子连接到所述电路板。
46.根据权利要求40所述的微电子组件,其中所述引线为线键合。
47.一种包括根据权利要求40所述的组件的系统,进一步包括与所述组件电连接的一个或多个其他电子部件。
48.一种根据权利要求47所述的系统,进一步包括壳体,所述组件与所述其他电子部件安装至所述壳体。
49.一种微电子组件,包括:
介电元件,所述介电元件具有相对地面对的第一表面和第二表面以及第一孔和第二孔,所述第一孔和所述第二孔在所述第一表面和第二表面之间延伸且彼此间隔开,所述介电元件进一步具有在其上的导电元件;
第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的所述第一表面的前表面,所述第一微电子元件具有第一边缘和暴露在其所述前表面处的多个触点;
第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件的所述前表面的突出部分延伸到所述第一微电子元件的所述第一边缘之外,所述突出部分与所述介电元件的所述第一表面间隔开,所述第二微电子元件具有暴露在所述前表面的所述突出部分处的多个触点;
引线,所述引线从所述微电子元件的触点延伸穿过所述第一孔和所述第二孔,到达至少一些所述导电元件;以及
至少一个无源部件,所述至少一个无源部件暴露在所述介电组件的所述第二表面处且位于所述第一孔与所述第二孔之间。
50.根据权利要求49所述的微电子组件,其中所述至少一个无源部件电连接到所述第一微电子元件。
51.根据权利要求50所述的微电子组件,其中所述至少一个无源部件电连接到所述第一微电子元件和所述第二微电子元件。
52.根据权利要求49所述的微电子组件,进一步包括导电平面,所述导电平面覆盖所述介电元件的所述第二表面,其中所述至少一个无源部件具有安装在所述导电平面并与所述导电平面电联接的电极。
53.根据权利要求52所述的微电子组件,其中所述至少一个无源部件为具有远离所述导电平面的第二电极的电容。
54.根据权利要求49所述的微电子组件,其中所述至少一个无源部件包括至少一个电容,所述至少一个电容具有与用于连接到电源或地的导电端子连接的电极。
55.根据权利要求49所述的微电子组件,进一步包括第一导电平面和第二导电平面,所述第一导电平面和第二导电平面覆盖所述介电元件的所述第二平面,用于分别连接到电源和地,所述至少一个无源部件具有分别与所述第一导电平面和所述第二导电平面电连接的第一电极和第二电极。
56.根据权利要求55所述的微电子组件,其中所述至少一个无源部件为电容。
57.根据权利要求49所述的微电子组件,其中所述引线为线键合。
58.一种系统,包括根据权利要求49所述的组件以及与所述组件电连接的一个或多个其他电子部件。
59.一种根据权利要求58所述的系统,进一步包括壳体,所述组件与所述其他电子部件安装至所述壳体。
60.一种微电子组件,包括:
介电元件,所述介电元件具有相对地面对的第一表面与第二表面以及在所述第一表面与所述第二表面之间延伸的一个或多个孔,所述介电元件进一步具有在其上的导电元件;
第一微电子元件,所述第一微电子元件具有后表面和面对所述介电元件的所述第一表面的前表面,所述第一微电子元件具有第一边缘以及暴露在其前表面处的多个触点;
第二微电子元件,所述第二微电子元件具有后表面和面对所述第一微电子元件的所述后表面的前表面,所述第二微电子元件的所述前表面的突出部分延伸到所述第一微电子元件的所述第一边缘之外,所述突出部分与所述介电元件的所述第一表面间隔开,所述第二微电子元件具有暴露在所述前表面的所述突出部分处的多个触点;
引线,所述引线从所述微电子元件的触点延伸穿过所述至少一个孔,到达至少一些所述导电元件;
导电平面,所述导电平面附接到所述介电元件且至少部分地定位在所述第一孔与所述第二孔之间,所述导电平面与至少一个所述第一微电子元件或所述第二微电子元件的一个或多个所述触点电连接;
第一无源部件,所述第一无源部件设置在所述第二微电子元件的所述前表面的所述突出部分与所述介电元件的所述第一表面之间;
第二无源部件,所述第二无源部件暴露在所述介电组件的所述第二表面处且位于所述两个孔之间;
引线,所述引线从所述第一无源部件延伸至所述微电子元件中的一个的触点;以及
电路板,其中所述介电元件包括暴露在所述第二表面处并与所述电路板电联接的多个端子。
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- 2011-10-21 CN CN2011800677685A patent/CN103384913A/zh active Pending
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Also Published As
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TWI528522B (zh) | 2016-04-01 |
US8885356B2 (en) | 2014-11-11 |
US20150043181A1 (en) | 2015-02-12 |
US20120153435A1 (en) | 2012-06-21 |
KR101061531B1 (ko) | 2011-09-01 |
US20120155042A1 (en) | 2012-06-21 |
WO2012082227A3 (en) | 2012-10-04 |
JP2013546199A (ja) | 2013-12-26 |
US8466564B2 (en) | 2013-06-18 |
BR112013015117A2 (pt) | 2016-09-20 |
TW201234556A (en) | 2012-08-16 |
WO2012082227A2 (en) | 2012-06-21 |
JP5827342B2 (ja) | 2015-12-02 |
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