CN1459126A - 形成介电薄膜的方法 - Google Patents

形成介电薄膜的方法 Download PDF

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CN1459126A
CN1459126A CN01815753A CN01815753A CN1459126A CN 1459126 A CN1459126 A CN 1459126A CN 01815753 A CN01815753 A CN 01815753A CN 01815753 A CN01815753 A CN 01815753A CN 1459126 A CN1459126 A CN 1459126A
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gas
layer
oxide
temperature
annealing
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CN100342500C (zh
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萨吉·利维
罗宾·S·布卢姆
阿瓦沙伊·凯普坦
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Mattson Technology Inc
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Mattson Technology Inc
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Abstract

本发明提供一种在诸如半导体片等基材上沉积高介电常数介质膜的方法。在一个实施方案中，该方法涉及在基材上形成氮化物层。在可供选择的实施方案中，本发明涉及在半导体晶片(wafer)上形成金属氧化物或硅酸盐。当形成金属氧化物或硅酸盐时，首先在基材上沉积钝化层。

Description

形成介电薄膜的方法
                          相关申请
本申请是基于2000年9月19日提交的申请号为60/233,740的临时申请，并要求该申请为优先权。
                          背景技术
为了形成互补的金属氧化物半导体(CMOS)的装置、MOSFET(金属氧化物半导体场效应晶体管)装置或高端存储装置如DRAMs(动态随机存储器)，常常需要在基材如硅晶片上形成高介电常数(高k)的薄涂层。已经开发了多种在半导体晶片上形成这种薄膜的技术。
在过去，栅极介质层是由二氧化硅形成的。然而，上述装置的小型化越来越需要比二氧化硅介电常数更高的栅极介质。这需要达到超薄型的氧化物等值厚度(小于20埃)而不牺牲栅漏电流。在一个实施方案中，本领域的技术人员已经研究过用氮化物层代替传统二氧化硅膜的可能性。
例如，在一种形成介电薄膜的常规方法中，首先在基材上形成氮氧化物层，然后在含氧的或惰性气氛中退火来制备介电层。例如，在美国专利US5,880,040中，Sun等人描述了这种常规方法。特别是，Sun等人描述了一种生产介电层的方法，包括：将加热的硅基材表面暴露于N2O，在其表面上生长二氧化硅层，使得该层中混入一定浓度的氮。接着，加热该层并将其暴露于NO，导致在二氧化硅层与硅基材之间的界面区形成硅-氮键。然后在惰性气体例如氮气存在下使该层退火。虽然此方法可能具有某些优点，但是由于在其中含氮量相对较低，对某些应用而言，所形成的薄膜的介电常数“k”常常不够大。
还开发出其它的方法。例如，被称为栅极叠层(gate stack)的另一个常规方法，包括：在硅基材上形成基底氧化物层，接着沉积栅极介质和栅极接触材料，从而形成介电薄膜。对于栅极叠层来说，已经发现的一个问题是：100纳米工艺节点的设计氧化物厚度小于2纳米，而50纳米工艺节点的设计氧化物厚度小于1纳米。由于隧道电流，传统的二氧化硅被认为不能依比例缩小到这种尺寸而同时具有合格的栅极漏电流。二氧化硅在这种厚度范围内设计的隧道电流预计也大几个数量级。需要高介电常数的材料来达到减小隧道电流的目的。
照这样，目前的需要是改进在基材上沉淀高介电常数的涂层方法。
                          发明内容
根据本发明的一个实施方案，提供一种在基材上沉淀介质膜的方法，包括由适合容纳基材的反应容器和与反应容器相连用于加热基材的能源组成的系统。例如，在一个实施方案中，该基材可以是半导体晶片。
当在反应容器中时，可以在基材上形成介电常数大于约4的氮化物薄膜。例如，一种形成该薄膜的方法可以包括下列步骤：
a)用能源将该基材加热到氧化物沉积温度；
b)当基材处于氧化物沉积温度时，向反应容器供给氧化物气体。该氧化物气体由至少含有一个氮原子的化合物组成，因此氧化物气体与基材起反应，在基材上形成氮氧化物层。例如，在一些实施方案中，该含氮化合物选自NO、N2O、NO2和它们的混合物。
c)当该基材维持在氮化物沉积温度时，在氮氧化物层上沉淀一层氮化物层。例如，在一些实施方案中，向反应容器中供给第一气体前体和第二气体前体可以沉积氮化物层。在一些实施方案中，第一气体前体包括至少含有一个硅原子的化合物(例如，SiH4、SiH3、SiH2Cl2等)，而第二气体前体包括至少含有一个氮原子的化合物(例如，NH3、N2O等)。
形成该薄膜的方法也可以包括：在渗氮退火气体(例如NH3)存在下使氮化物层退火，以及在氧化物退火气体(例如N2O)存在下使氮化物层退火。
在一个实施方案中，为了使成型层的表面粗糙度最小，可以形成氮氧化物层，使得其厚度小于10埃。而且，在小于约750℃的温度下可以沉积氮化物层，而在氧化物退火气体存在下于大于770℃的温度下使氮化物层退火。形成的氮化物层厚度可以小于约25埃。
为了在氮化物沉积之前形成薄的氮氧化物层，可以在压力小于约50托，特别是小于约25托的气氛中形成该氮氧化物层。
如上所述，除在氧化物退火气体存在下使该氮化物层退火之外，也可以在渗氮退火气体存在下使该氮化物层退火。当在渗氮退火气体存在下退火时，温度可以是从约875℃到约925℃。
该氮化物层可被用于各种装置中。例如，该氮化物层可以用于电容器或晶体管中。
在一种替代的实施方案中，作为代替形成氮化物层，本发明目的是在半导体晶片上形成金属氧化物。在这一实例中，本发明的方法包括：在含氮气体存在下加热由二氧化硅组成的晶片，从而在该晶片上形成钝化层。含氮的气体可以是氨气。钝化层的厚度可以小于约5纳米，特别是小于1纳米。在从约600到约900℃的温度下在小于约10秒内可以形成钝化层。在形成钝化层的过程中，含氮气体的分压可以小于约100托。
根据本发明，形成钝化层是为了防止随后形成氧化物层。
在形成钝化层以后，在气体前体存在下可以加热该晶片以形成由金属氧化物或硅酸盐组成的介电层。在大于约300的温度下，特别是在从约400℃到约800℃的温度下可以形成介电层。在形成介电层的过程中，气体前体的分压可以小于约100托。例如，该介电层可以是HfO2、ZrO2、Al2O3、Ta2O5、La2O5或它们的硅酸盐。
在形成介电层以后，可以在退火气体存在下使该晶片退火。退火气体可以包括惰性气体和含氧气体。例如，退火气体可以是氮气、氩气或它们的混合物。另一方面，含氧气体可以是NO、N2O、O2或它们的混合物。
介电层一旦形成，其EOT可以小于1.2纳米。该介电层可被用于各种装置中。在一个实施方案中，多晶硅层可以沉积在介电层之上。
可以在快速热处理室中进行本发明的方法，晶片在该室中被迅速地加热到高温。在独立的加热循环过程中可以依照要求形成整体层。
下面更详细地描述本发明的其它特征和特点。
                          附图说明
本发明全部和能够公开的内容包括：对一个本领域中普通技术人员来说，在说明书剩余部分中更具体地阐明其最佳方式，其引用附图，其中：
图1是在一个本发明实施方案中可以使用的快速热化学气相沉积系统的剖视图；
图2是本发明方法的一个实施方案的流程图；
图3是根据本发明可以使用的快热化学气相沉积(RT-CVD)模块的俯视图；
图4是本发明方法的一个实施方案图；
图5是本发明方法的另一个实施方案图；
图6～23是说明实施例1中获得的结果图；和
图24是说明下面实施例2中获得的结果曲线图。
在本说明书和附图中重复使用的附图标记代表本发明的相同或类似的部件或元件。
                          具体实施方式
一个本领域中的普通技术人员将明白：该描述仅仅是示范性实施方案的说明，而不是用来限制本发明的更广的范围，其中更广的范围具体体现在示例性的结构中。
概括地讲，本发明涉及一种在基材上沉淀具有较高介电常数“k”的涂层的方法。例如，按照本发明形成涂层的介电常数一般是大于约4，在一些实施方案中，大于约10，而在另一些实施方案中，大于约15。例如，按照本发明形成的涂层的介电常数可以为约5到约100，在一些实施方案中，为约15到约20。而且，所形成的高k涂层厚度通常小于约30纳米。例如，当使用成型装置时，所形成的厚度一般为约1到约20纳米，而在一些实施方案中，厚度一般为约1到约10纳米。
如下面更详细描述的那样，本发明通常涉及高介电常数的栅极介质层的形成方法。按照本发明可以制备具有等值氧化物厚度(EOT)小的各种装置，例如CMOS装置。在一个实施方案中，本发明涉及形成氮化物叠层(stack)，特别涉及形成用于栅极介质领域中的Si3N4/SiO2叠层。在一种替代的实施方案中，本发明涉及在形成栅极介质中的在半导体晶片上沉淀高介电常数的金属氧化物或硅酸盐涂层。本发明形成的金属氧化物或硅酸盐涂层适合于传统自对准的双栅聚硅CMOS技术，形成的界面氧化物层最小，降低了装置的性能和可靠性。制造出的装置的等值氧化物厚度(EOT)值低和漏电流减小。
一般地，在本发明中可以使用任何能够在基材上沉积介质膜的室或容器。例如，传统的化学气相沉积容器可以适用于本发明的方法。然而，应当理解，本发明也可以使用其它技术中使用的其它容器，例如物理气相沉积、等离子增强的化学气相沉积、溅射等中使用的容器。
图1图解了系统10的一种具体实施方案，其采用化学气相沉积法在基材上沉积介质膜。如图所示，该系统10包括适合于容纳基材例如半导体晶片14的反应容器12。如图所示，晶片14被放置在由绝热材料例如石英制成的基材座15上。在一个实施方案中，可以利用晶片旋转机构调节基材座15以便旋转晶片14。旋转晶片14可以提高晶片14表面上的温度均匀性，并且可以促进晶片14与引入反应容器12中的气体之间的接触和气体均匀性。然而，应当理解，除晶片之外，该反应容器12也适合处理其它的基材，例如光学元件、薄膜、纤维、带状物(ribbons)等。
反应容器12设计成能以非常快速和在仔细控制条件下加热晶片14。可以由各种材料，例如包括金属和陶瓷，制成反应容器12。在一些实施方案中，例如，可以由不锈钢或石英制成反应容器12。当反应容器12由导热材料制成时，它一般包括冷却系统。例如，如图1所示，反应容器12包括：沿着反应容器12圆周缠绕的或容纳在反应容器12洞口在内的冷却导管16。
如图所示，在设备10中也提供能源22。具体地，使能源22与反应容器12相连，以便在处理过程中发射能量加热晶片14。一般地，可以使用各种加热设备作为能源22。例如，能源22可以包括：光源、激光(例如氮激光器)、紫外线加热设备、弧光灯、有高紫外线输出的蒸汽灯(例如水银灯)、闪光灯、红外辐射装置、电阻加热器以及它们的组合等。而且，可以改变能源22的光谱形状和/或某些性能(例如强度、极化度、连续和/或脉冲式发射辐射)以适合特定的工艺。例如，可以按照时间函数和/或根据晶片14的性能或晶片14上薄膜的函数控制能源22的谱形(例如，薄膜和/或晶片14的温度、沉积在晶片14上的薄膜厚度，或薄膜或晶片14的任何其它的物理或化学参数)。
例如，在所说明的实施方案中，能源22包括许多灯24。灯24可以是白炽灯，例如卤钨灯。能源22也可以包括：用于由灯24发射到晶片14上的均匀直接能源的反射镜或一组反射镜。如图1所示，灯24放置在晶片14之上。然而，应当明白：灯24可以放置在任何具体位置。例如，灯可以使用在晶片14之上和/或在晶片14之下。而且，如果需要，在系统10内也可以增加灯或减少灯。
系统10也可以包括置于能源22和晶片14之间的窗孔32，其能够使能量以预选的波长通过。例如，在一些实施方案中，窗孔32可以起过滤器的作用，使某些光的波长通过，而吸收其它波长。此外，在一些实施方案中，窗孔32可能不起过滤器的作用。
在一个实施方案中，在加热循环过程中，为了监视晶片14的温度，反应容器12可以包括许多辐射传感器。辐射传感器27可以包括：许多光学纤维、透镜、光管等。例如，在所说明的实施方案中，辐射传感器包括与许多对应温度探测器30相联接的光管28。例如，在一个实施方案中，设置光学纤维28来接受由晶片14发出的特殊波长的热能。然后，感应到的辐射含量传递给温度测检器30，其产生用于确定晶片温度的可用电压信号，在某种程度上，可以根据普朗克定律计算晶片温度。在一个实施方案中，每个光学纤维28与热敏元件30结合组成高温计。在另一实施方案中，光学纤维28通向一个简单的但是多路复用的辐射传感器。
除使用辐射传感器之外，在本发明系统中也可以使用其它的温度传感器。例如，可以在一个位置或许多位置上将一个或多个热电偶装入该系统中用于监视晶片晶片14的温度。热电偶可以与晶片14直接接触放置或可以放置在晶片14附近，由此可以推断出温度。
反应容器12也包括至少一个将一种或多种气体引入该容器而在晶片14上形成介质膜的入口18。如图所示，例如，入口18可以与通过管路72的气体源70和通过管路74的气体源80相连接，以便给反应容器12提供两种或多种不同的气体。在一个实施方案中，喷头可以连接到气体入口，使气体分散在晶片上。反应容器12也包括至少一个出口20，用于在某一段时间之后从容器12中抽空气体。也应该理解：虽然只说明了一个入口18和出口20，但是容器12可以包括许多给容器供气的入口和出口。
在一个实施方案中，反应容器可以包括闸门阀，例如从VAT购买的闸门阀，其使该室与操作面(handling side)隔离。使用机械初始抽气泵可以使该室达到真空状态。可以通过阀门控制压力。通过使用涡轮分子泵可以达到小于10-3托的高真空。
氮化物叠层的形成
参见图2，下面更详细地描述本发明方法的一个实施方案，其使用如图1所示的化学气相沉积系统在晶片14上形成氮化物介质膜。然而，应当理解，在本发明的方法中也可以使用其它系统和其它沉积技术。例如，在US美国专利No.6,136,725中Loan等人描述了适用化学气相沉积的系统，在这里在这里引入全部内容仅作为参考目的。
开始，使用能源22将晶片14加热至某一氧化物沉积温度。当晶片14保持在预定氧化物的沉积温度时，通过入口18将氧化物气体以某一流速提供给反应容器12，以便沉淀一段时间。例如，如图1所示，可以通过管路72由气体源70将一种或多种氧化物气体提供到气体入口18。可以改变氧化物气体流速，但是一般为每分钟约50标准立方厘米到每分钟约10标准升。而且，在一个实施方案中，用平均约10秒钟供给氧化物气体。该形成层的厚度可以为约15埃或15埃以下(例如，10埃或10埃以下)。
在本发明中可以使用许多氧化物气体。特别是，在本发明中可以使用能够在晶片上形成比较高介电常数的基底氧化物层的任何氧化物气体。例如，一些适合的氧化物气体包括含氮的气体，例如一氧化氮(NO)、一氧化二氮(N2O)、二氧化氮(NO2)等。因此，当使用含氮的氧化物气体例如上述的氧化物气体时，形成的基底氧化物层通常是具有通式SiOxNy的氧氮化物结构。
而且，可以根据使用的基材、使用的氧化物气体和/或积附涂层要求的特性来改变特定氧化物的沉积温度。例如，氧化物沉积温度一般是相对低，以便使基底氧化物层的厚度减到最小(6～9埃)，从而提高所形成薄膜的介电常数。例如，当基底氧化物层沉积在硅晶片上时，晶片温度一般保持在小于约1100℃，在一些实施方案中温度为600℃到约1100℃，在一些实施方案中温度小于约750℃，在一些实施方案中温度为约600℃到约750℃，而在一个实施方案中温度为约700℃。而且，在氧氮化物沉积过程中，反应容器压力一般为约1托到约760托。
在上述实施方案中，基底氧化物层中存在的含氮量可以显著地提高该层的介电常数，从而提高所得到的装置的电特性。已经发现：为了提高含氮量，应该降低氧化步骤的压力。因此，为了增加含氮量，压力应该小于100托，特别是小于50托，且更特别是小于25托。
在本发明的这一实例中，在基底氧化物层上沉积氮化物层。一般地，在本发明中可以使用任何众所周知的氮化物沉积技术，例如化学气相沉积。例如，在美国专利US 6,177,363中，Roy等人描述了一种适合的化学气相沉积的技术，在这里引入全部内容作为参考。而且，在一个实施方案中，可以使用图1的化学气相沉积方法使氮化物层沉积在晶片上。例如，可以通过入口18将一种或多种氮化物前体气体以确定的时限和确定的流速提供给反应容器12。在一个实施方案中，如图1所示，一种氮化物前体气体由气体源(未示出)通过管路74供给到气体入口18，而另一种前体气体由另一个气体源(未示出)供给到气体入口18。可以改变氮化物前体气体流速，但是一般为每分钟约50标准立方厘米到每分钟约10标准升。而且，在一个实施方案中，供给氮化物前体气体，直到厚度达到约20埃(一般为25～50秒)。
一般地，在本发明中可以使用许多能够形成氮化物层的任何气体前体。例如，一种氮化物气体前体可以含有硅(例如SiH3、SiH2Cl2、SiH4等)，而另一种气体前体可以含有氮(例如NH3等)。因此，例如SiH4气体前体和NH3气体前体可以在晶片的表面上反应形成分子式为Si3N4的氮化物层。
在氮化物沉淀时限过程中，通过能源22使晶片14保持在确定的温度下。例如，氮化物沉积温度可以小于约900℃，而在一些实施方案中温度为600℃到约750℃。在一个实施方案中，已经发现：保持在小于约750℃的温度下可以降低所形成层的粗糙度。而且，在供给氮化物前体气体过程中，反应容器压力一般小于约760托，而在一些实施方案中，压力小于100托。
在形成氮化物涂层之后，将它暴露于一种或多种附加的退火气体中来增加含氮量，除去氢气和减少该层的缺陷。例如，如图1所示，在要求的氮化物沉淀期限之后，可以使用泵(未示出)通过出口20从反应容器12除去氮化物气体。然后，通过入口18以确定的流速和确定的时限给反应容器12提供含氮退火气体(例如NH3)，以增加氮化物层的含氮量。可以改变含氮退火气体流速，但是一般为每分钟约50标准立方厘米到每分钟约10标准升。
在渗氮退火期间，能源22将晶片14加热到确定的渗氮温度。例如，在一些实施方案中，晶片14的渗氮温度可以小于约1100℃，而在另一些实施方案中，温度为600℃到约1100℃。本发明人已经发现：降低渗氮退火温度可以降低表面粗糙度。在这点上，为了降低粗糙度，该温度应该小于约900℃，特别是小于约850℃。另一方面，为了使含氮量最大，该温度应该为约875℃到约925℃，特别是约905℃。在供给含氮退火气体的过程中，反应容器压力一般为约1托到约760托，而在另一个实施方案中，压力约为500托。
一旦用渗氮气体退火后，然后可以用氧化物气体使氮化物层退火来除去该层中的氢气。例如，如图1所示，在要求的渗氮退火期限之后，可以使用泵(未示出)通过出口20从反应容器12中除去含氮退火气体。然后，可以通过入口18以确定的流速和确定的时限给反应容器12提供一种氧化物退火气体(例如N2O、NO等)。可以改变氧化物退火气体流速，但是一般为每分钟约50标准立方厘米到每分钟约10标准升。
在氧化物退火期间，能源22将晶片14加热到确定的氧化物温度。例如，在一些实施方案中，晶片14的氧化物退火温度小于约1100℃，而在另一些实施方案中，温度为600℃到约1100℃。为了降低粗糙度，氧化物退火温度应该更高，例如大于750℃。然而，为了增加含氮量或使含氮量最大，该温度应该更低，特别是小于约700℃。在供给氧化物退火气体的过程中，反应容器压力一般为约1托到约760托，而在另一个实施方案中，压力约为500托。
如果需要，也可以控制上述方法的各种参数，以便制备一种具有确定的预定性能的介质膜。为了控制沉积和退火条件，可以使用许多机械装置。例如，在本发明的一个实施方案中，如图1所示，该系统10可以包括：能够从系统10的各种组件或从控制器(operator)接受输入信号的系统控制器50，基于这些信号，控制系统10的详细参数。控制器50可以是一个可编程逻辑控制器(PLC)，例如Allen-Bradley控制逻辑处理器，尽管适用于控制上述系统10的任何其它控制器通常是可接受的。另一方面，硬线连接的电路、继电器、软件等可以代替PLC和用作控制器50。
例如，在一个实施方案中，系统控制器50从温度测检器30接受电压信号，其代表在各种位置抽样的辐射总量。基于接受的信号，设置控制器50以计算晶片14在不同位置处的温度。此外，如图1所示，也可以将系统控制器50与光源功率控制器25相连接。在此装置中，控制器50可以测定晶片14的温度，并根据这些信息控制能源22发出的热能数量。用这样的方式，可以即时对反应容器12内的条件进行调节，以便在仔细控制范围内处理晶片14。
例如，如上所述，可以和温度测检器30和能源22一起使用系统控制器50，来将反应容器12内的温度调整到预定的沉积温度或退火温度。在预定沉积期间或退火期间之后也可以自动调整温度。而且，如上所述，使用控制器50也可以在一次或多次循环中改变沉积温度或退火温度。
也可以使用控制器50自动地控制系统10的其它组件。例如，可以使用控制器50控制通过气体入口18进入反应容器12中气体的流速。如图所示，系统控制器50可以与阀门76和78(例如，电磁阀)相连，此阀门分别用于控制来自供气源70和80的气体流速。例如，在一些实施方案中，可以设置控制器50以接受温度测检器30的温度测量。因此，如上所述，当在特定的反应周期过程中某一温度时，系统控制器50可以使阀门76和/或78打开，以预定流速给反应容器12提供一种或多种气体。系统控制器可以根据来自系统10的各种输入信号或由程序员调整气体流速。
在形成如上所述的氮化物叠层(Si3N4/SiO2)之后，该叠层可被用于可被用于如上所述的各种装置中，例如晶体管中的金属氧化物半导体电容器。在一个实施方案中，在形成叠层之后，可以进行多晶硅沉积和POCL5掺杂(doping)。而且，在P沟金属氧化物半导体晶片中，使用BH3，接着退火，可以进行硼离子的嵌入(implant)。当用于晶体管结构时，上述叠层具有极好漏电流，为4e-3A/cm2@-1.5V，等值氧化物厚度(EOT)为14.6埃。
含金属氧化物和硅酸盐的高介电常数的栅极介质的形成
本发明的实施方案涉及形成含金属氧化物和硅酸盐的介电层。栅极介质层位于在氧化物-硅界面和栅极节点材料两者之间的半导体晶片上。本发明形成的栅极介质特别适用于小型的装置中。
本发明人已经认识到：在硅金属氧化物半导体沟槽(channel)和高介电常数电介质之间的中间层是等值氧化物厚度(EOT)达到小于1纳米的最关键特征之一。在过去，通常是在硅表面和栅极介质之间形成氧化物层。这种氧化物层或者是有意形成，或者是在退火过程中形成。例如，最高介电常数的电介质对氧气的扩散阻碍性差，其在退火过程中引起界面的氧化物层生长。然而，这些界面氧化物层的存在增加了等值氧化物厚度，降低了高介电常数电介质的效果(effectiveness)。而且，在退火过程中在高介电常数电介质和硅基材之间的任何反应也增加等值氧化物厚度，形成界面状态，降低迁移率(mobility)并显著增加漏电流。
本发明的实施方案涉及一种等值氧化物厚度小的互补金属氧化物半导体装置结构。特别是，本发明可以制造高介电常数的栅极介质，其与传统自对准的双栅聚硅互补金属氧化物半导体兼容，降低装置性能和可靠性的界面氧化物层形成最小。本发明制造的装置的等值氧化物厚度小于1.2纳米，显著地降低漏电流。
在这一实例中，在形成高介电常数栅极介质的过程中，以及起初在硅基材上现场形成超薄型的钝化层，在沉积后退火的过程中，本发明避免形成界面氧化物层。可控地和短暂地将清洁的硅表面暴露于含氮的环境例如NH3中，形成超薄型的钝化层。该形成层的厚度小于5纳米，特别是小于1纳米。在形成钝化层之后，进行高介电常数栅极介质例如金属氧化物或金属硅酸盐的沉积。
本发明的方法可用于沉积高介电常数的金属氧化物或硅酸盐涂层，其中金属是铝、铪、钽、钛、锆、钇、硅、镧和它们的结合物等。例如，可以使用本发明方法在由硅制成的半导体晶片上沉积金属氧化物的镀层，例如氧化铝(Al2O3)、氧化钽(Ta2O5)、二氧化钛(TiO2)、氧化锆(ZrO2)、二氧化铪(HfO2)、氧化钇(Y2O3)、氧化硅锆(SiZrO4)、氧化镧(La2O5)、其相应的硅酸盐等。例如，氧化钽一般形成介电常数为约15到约30的涂层。
在这一实例中，为了沉积介电常数比较高的涂层，如果需要，首先清洁基材。在清洁之后，在基材上由含氮气体例如氨气形成钝化层。然后，在钝化层上出现高介电常数的电介质沉积。该高介电常数的介电层在含可控数量氧气的氮气或氩气环境中经过现场退火来改善介电性质。该方法制备具有非常薄的等值氧化物厚度和很高质量的高介电常数的栅极介质。
一般地，可以使用任何能够用于在基材上沉积介质膜的室或容器来形成介电层。例如，传统的化学气相沉积容器可以适用于本发明的方法。例如，在图1中举例说明的系统可被用于上述方法中。换句话说，也可以使用一组工具系统进行快速热处理。图3中举例说明了一组工具的一个例子。
下面更详细地描述一种形成含金属氧化物或金属硅酸盐的介电层方法的实施方案。在图4和5中用示意图方法说明本发明方法的实施方案。如图所示和如上所述，首先清洁硅晶片。一般地，可以使用任何适合的清洗方法。例如，在一个实施方案中，可以处这样理硅表面，即将基材浸入稀释的氢氟酸中，接着用去离子水或其它的溶液清洗该基材。
晶片一经清洁后，然后在基材上形成由氮化物阻挡膜制成的钝化层。将该晶片表面暴露于含氮的保护条件例如含氨的保护条件下形成氮化物层。形成的氮化物层应该非常薄，例如小于5纳米，特别是小于1纳米。例如，在一个实施方案中，可以将该基材在约600℃到约900℃的温度下于氨气中暴露约0.1到10秒钟。
在将氨气引入反应室之前，基础压力应该在约1到约1×10-9的范围内，优选较低的基础压力。在钝化层生长的过程中氨气分压可以在约0.1到约100托的范围内。在形成钝化层之后，如果需要，可以冷却该基材，然后从该处理室排出氨气。
接着，在钝化层上形成高介电常数的介电层。为了形成高介电常数的介电层，以一定的流速，在一定的温度下将气体前体供应到反应容器中一定的沉淀时间。可以改变气体前体流速，但是一般为每分钟约一个标准立方厘米到每分钟约一升。气体前体可以单独或和载体气体，例如惰性气体(例如，氩气或者氮气)一起供应到反应容器中。
一般地，在本发明可以使用各种气体前体形成具有高介电常数“k”的涂层。特别是，在本发明中可以利用能够在晶片上形成高介电常数涂层的任何气体前体。例如，一些适合的气体前体包括含铝、铪、钽、钛、硅、钇、锆及其组合等的气体。
在有些情况下，有机金属化合物的蒸气可以用作前体。这种有机金属气体前体的一些例子包括，但不限于，三左旋丁基铝、乙氧基铝、乙酰丙酮铝、叔丁氧铪(IV)、乙氧基铪(IV)、四丁氧基硅烷、四乙氧基甲硅烷、五(二甲基氨基)钽、乙氧基钽、甲氧基钽、四乙氧基乙酰丙酮化钽、四(二乙基氨基)钛、叔丁氧钛、乙氧基钛、三-(2，2，6，6-四甲基-3，5-庚二酸)钛、三-[N，N-双(三甲硅烷基)酰胺]钇、三-(2，26，6-四甲基-3，5-庚二酸)锆、二(环戊二烯基)二甲基锆等。
当根据本发明使用时，例如上述有机金属前体可以在晶片基材上形成一种或多种金属氧化物层。
在金属氧化物或硅酸盐的沉积过程中，温度可以为约400℃到约800℃。沉积的持续时间可以为约0.1到约100秒。在沉积的过程中分压可以在约0.1到约100托的范围内。
在沉积高介电常数介电层之后，可以从该室除去任何其余气体前体。然后进行沉积后的退火。可以在同一个室中进行退火，或晶片可以移到RTP模块中。
沉积后退火的加工条件包括：温度为约400℃到约900℃，持续时间为约0.1到约100秒。在氮气或氩气或于它们与含氧气体例如NO、N2O和O2的混合物的保护条件下进行退火。该室中的压力可以为约0.1到约700托。
在处理的过程中，最好是反应容器或容器能保持在很高的真空状态例如10-9到10-3托下，保证没有氧气引入到该室，以便控制界面。通过此处理后，形成具有非常低的等值氧化物厚度和非常低的漏电流的形成层。例如，可以制造等值氧化物厚度为约7.87埃，漏电流为5×10-4A/cm2@Vg＝-1V的栅极叠层。
                           实施例
实施例1
互补金属氧化物半导体(CMOS)装置的小型化越来越需要比二氧化硅介电常数更高的栅极介质。这需要达到超薄型的氧化物等值厚度(＜20埃)而不致于牺牲栅漏电流。进行下列试验研究在栅极介质领域中使用Si3N4/SiO2叠层。研究的物理性能是粗糙度、含氮量和实际厚度。也对电容器和晶体管的电特性进行研究。
使用硅的局部氧化(LOCOS)隔离方法在p型硅晶片上面制造N沟道金属氧化膜半导体(NMOS)电容器。同时制造P沟金属氧化物半导体(PMOS)电容器，以检查渗透硼的抑制情况。使用本发明受让人销售的Integra Pro®-快热化学气相沉积成套工具生产二氧化硅/氮化物栅极叠层。
首先，在RT-CVD室中没有保护气氛于800℃下对晶片氧化10秒钟。然后，在700到800℃下用NH3和SiH4以25到50秒钟的时间沉积20埃的氮化硅。在CVD氮化物沉积之后，在NH3保护气氛下，接着在N2O保护气氛下于700到900℃下对样品样品进行退火30秒钟。表1表示了每个工序的工艺条件。然后将样品转移到LPCVD加热炉中进行多晶硅沉积和POCL5掺杂。在OMOS晶片的情况下，使用BH3，接着进行RTP退火，可以进行硼离子的嵌入(implant)。
                     表1：工艺条件
  I-NO氧化         II-CVD SiN   IV-NH3退火   V-N2O退火
  温度(℃)   时间(秒) 温度(℃)   温度(℃)   温度(℃)
  800   25 800   700-900   700-900
介电常数-等式(1)计算氧化的氮化物的介电常数：
             ε_实际＝(x/EOT)*ε_SiO2           (1)
其中：
X＝实际厚度
EOT＝导电氧化物厚度，包括QM效果和聚储层衰竭效应(depletioneffects)
ε_SiO2＝SiO2的介电常数(3.9)。
用透射式电子显微镜测定等式(1)中使用的实际厚度为23埃等值氧化物厚度，包括QM效果和聚储层衰竭效应(depletion effects)，如图6所示，经过5月时间达到该厚度。从对电容器结构进行的C-V测量中求出氧化物等值厚度。
比较使用等式(1)的电学氧化物厚度和实际厚度得到介电常数为5.6，其比热氧化介电常数高1.45倍。
薄膜粗糙度的降低保持了良好的电特性：低漏电流、高击穿负荷(highcharge to break down)和高可靠性。为了检查结果的正确性，确认粗糙度再现性(Roughness repeatability)。图7表示在750℃的沉积温度下化学气相沉积的粗糙度再现性。所得的晶片与晶片的标准偏差是8％。
使用外部分析法检验氮化物薄膜。在分析之前检查薄膜的阶变时间(staging time)确定它是否对测量结果有任何影响。如图8所示，由于样品的阶变(staging)，所以粗糙度没有显著的变化。
在每个工序之后，分析粗糙度，确定那些步骤对全部薄膜粗糙度有微小的影响，如图9所示。
当检查图9时，人们可以知道：第一个氧化步骤对薄膜粗糙度没有显著地影响。化学气相沉积步骤是薄膜粗糙度的主要根源。
通过检查时间相关性(图10)进一步研究化学气相沉积步骤的粗糙度。晶片处理包括：NO氧化，接着化学气相沉积法进行氮化物沉积；没有退火。
化学气相沉积温度也是控制薄膜粗糙度的一个重要因素。在图11中，比较在不同的沉积温度下相同厚度薄膜的表面粗糙度。为了达到相同的厚度，调整沉淀时间。
在两个不同温度下在氮化硅薄膜生长初期拍摄AFM图像。AFM图像说明一种趋势：较高的温度将导致增加粗糙度。此外，AFM图像显示出不同的粒径。在较高的温度下晶粒更大。在较高的温度下，表面上的原子有扩大的扩散长度，和迁移到能量较低的部位，形成较大的晶粒。随着扩散长度的增加，物理吸附的(physorbed)原子很可能附着于现有的原子团(cluster)上，而不是形成新的原子团。结果是颗粒密度较小和粒径较大。
图12表示沉积在不同氧化物膜上的所得到的化学气相沉积薄膜的微观粗糙度。当化学气相沉积法沉积参数保持不变时，在不同的压力下生长氧化物。较薄的氧化物降低了化学气相沉积氮化物的微观粗糙度。当NO压力降低时，氧化物厚度减小。在此厚度范围(6～9埃)，氧化物薄得足以具有不同的表面悬空键(dangling bond)密度作为其厚度的函数。Si与SiO2之间的界面宽度为5埃(2ML)。如果悬空键的密度高，在薄膜生长初期形成的岛状物较小而且较近。这将产生具有较低的微观粗糙度的薄膜。
接着改变不同温度来检查在不同NH3退火条件下的薄膜粗糙度。氨气退火温度的增加将导致薄膜粗糙度增加，如图13所示。
最后，研究N2O退火对薄膜微观粗糙度的影响。人们发现：增加N2O退火温度导致降低薄膜的微观粗糙度。在大约750℃下，薄膜的微观粗糙度有一个大的转变。此温度被认为是转变温度，其中膜粘度降低，使薄膜流动。重要的是注意：随着氨气退火温度增加，薄膜的微观粗糙度增加(图13)。然而，对于N2O退火来说，所得到的趋势相反。具有较少刚性分子网络的薄膜将显示出较低的粘度。O-Si-O网状结构比Si-O-N网状结构有较大的自由度。在氧化气氛N2O下，薄膜将增加氧含量，结果，分子网络有较小的刚性。薄膜流动较容易，结果是降低粗糙度。此外，氨气退火主要是在硅与氮比例高的薄膜部位上反应。当它有选择地反应时，认为它增加了粗糙度。
图14表示粘度效应和薄膜微观粗糙度的突然降低。
对薄SiO2的缩放比例(scaling)的基本限制是由于直接隧道效应而导致大的漏电流。使用介电常数较高的氮化硅/氧化物叠层，当保持相同的电容时，由于是真正的厚膜，所以应该降低直接的隧道效应。氧化物/氮化物层的介电常数随着氮浓度增加而增加。
使用X射线光电子能谱描绘薄膜材料组合物的特性。也使用X射线光电子能谱检验薄膜的实际厚度，得到与TEMs良好的相互关系。对用X射线光电子能谱测量确定的绝对含氮量估计过低。当TEM和C-V曲线结合起来测量时得出的介电常数(为5.4)与当用X射线光电子能谱测量的含氮量计算时得出的介电常数(为4.9)相比较，可以看到看到这一点。X射线光电子能谱的测量只是相对的。
第一个试验是确定在NO氧化步骤中的压力效应。图15表示了所得到的薄膜组成和厚度。当氧化压力从1增加到100托时，氮含量从14.2％减少到9.5％。
通过改变沉积温度检查氮化物沉积步骤。图16表示氮含量和实际厚度。试验结果表明改变沉积温度并没有显著地改变氮含量。然而，随着沉积温度增加，实际厚度也增加。
接着，检查氨气步骤。图17表示在不同的氨气退火温度下的氮含量。
在图18中可以看到实际厚度。随着氨气温度的增加，厚度也增加。
接着，研究氮含量与N2O退火温度之间的函数关系。氮气消耗随着N2O温度而增加。在具有较短停留时间的热系统中，由N2O分解产生原子氧。
                      (2)
原子氧与作为Si-NH2、Si＝NH基团一部分的[-NH2]和[-NH]反应。原子氧取代大部分薄膜中的[-NH2]和[＝NH]。结果是降低了薄膜中的氢含量和氮含量，如图19所示。
最后，我们研究了薄膜厚度与N2O退火温度的函数关系，如图18所示
从C-V曲线图求出氧化物等值厚度。也测量栅漏电流。在总曲线上绘制结果，如图22所示。总曲线被用作新工艺条件的参考。归一化电流密度由等式3定义：
漏电流比＝Ig_measured(EOT＝x)/Ig_mastr_plt(EOT＝x)    (3)
式中：
Ig_measured＝累积的测量漏电流(对于N沟道金属氧化膜半导体电容器来说为-2.5V)，其中根据C-V曲线确定，测量薄膜的等值氧化物厚度为x。
Ig_mstr_plt(EOT＝x)＝图22中EOT为x时从氮化物曲线中预计的漏电流。
电流的迁移机理(transport mechanism)主要是在低电场(fields)下的DT隧道效应和在较高电场(fields)下的FN。由于电流迁移机理的结果，当绘制如等式(4)所示的漏电流与EOT的曲线图时，预期的结果是指数函数关系。等式(4)是单层电介质的隧道效应几率(tunneling probability)。
       P(Veff，EOT)＝exp[-2*EOT*a*(me*{Eb-Vbeff})0.5]  (4)
式中：
a＝常数
me＝电子隧道质量(Electron tunneling mass)
Eb＝隧道效应的有效均匀的势垒高度(barrier height)
为了证明该薄膜有低的缺陷密度，而且可以由RN隧道效应等式推断，绘制FN函数(图21)。氮化物薄膜具有FN隧道效应历程(tunneling mechanism)。
进行大的DOE，目的是为了使漏电流和等值氧化物厚度(EOT)达到最小。我们优化了该过程，获得等值氧化物厚度为14.5埃的薄膜和比氧化物多两个数量级的栅漏电流，如图22所示。
对于晶体管来说，优化饱和电流是一个关键问题。对参数的范围进行研究，找到主要的影响参数。求出载流子迁移率使该数据标准化，将此结果与二氧化硅的结果比较：
                    μNormalized＝μSi3N4peak(E)/μSiO2(E)
式中：
μSi3N4peak(E)＝从在电场E下测量的数据(C-V和Id-Vg)求出氧化物/氮化物的峰值迁移率(peak mobility)。
μSiO2(E)＝氧化物在电场E下的全体迁移率。
使用马希森法则分析迁移率数据与电场，揭示出迁移率降低的主要根源是库仑散射。因此，当增加NO的温度时，等值氧化物厚度并没有显著改变，因此为了获得较高的载流子迁移率，希望使用较高的NO温度(参见图23)。
小结
原子力显微镜检查法(AFM)用来表征由整个过程的岛生长引起的粗糙度。首先，测量氧化物，发现其非常平滑，RMS为1.4埃。在氮化硅沉积之后，粗糙度增加。人们发现NO氧氮化物越薄，氮化硅沉积越光滑。较薄的NO氧化物导致较厚的化学气相沉积氮化物。降低化学气相沉积温度也减小氮化硅的粗糙度。化学气相沉积氮化物沉积之后进行NH3退火会增加粗糙度，是由于非同质薄膜的氮化。最后，N2O退火显著地降低粗糙度。
X射线光电子能谱用来估算薄膜的氮含量、氧含量和硅含量。人们发现：增加N2O温度会降低氮含量，而增加NH3温度会增加氮含量。
透射式电子显微镜和X射线光电子能谱用来研究薄膜的实际厚度。在确定了与透射式电子显微镜的相互关系之后，X射线光电子能谱用于实际厚度的测量。当增加退火温度时，发现实际厚度也增加。
电容器结构结构用来优化等值氧化物厚度和泄漏量。我们通过降低化学气相沉积温度和优化退火来改进等值氧化物厚度和泄漏量。
晶体管结构用来分析正电荷和饱和电流。
已经证明晶体管结构在等值氧化物厚度为14.6埃在-1.5V时具有极好漏电流，为4e-3A/cm2，同时具有良好的迁移率。
实施例2
在此实施例中使用p型硅(100)基材。用硼掺杂该基材使电阻率为0.02欧姆-厘米。用硼掺杂一种外延的硅层使电阻率为10欧姆-厘米。在薄膜淀积之前，将基材浸入稀释的HF中30秒钟，然后在去离子水中清洗。将该基材放在RT-CVD室中，该室被抽空到10-4托的压力，然后充满NH3气体到1～10托的压力。将该基材加热至700-800℃形成氧氮化物钝化层。然后使用叔丁氧铪(C16H36O4Hf)作为Hf前体，在50sccm的N2和分压为5托的O2的载体气体中在400～700℃下，将该基材暴露于快热MOCVD中10秒钟。模制成栅极面积为5×10-5cm2到10-3cm2的装置。Al/TiN和多晶硅被用作栅电极。
测量该装置与栅电压有关的电特性。图24说明用此方法制造的HfO2栅极叠层得到的等值氧化物厚度＝7.87A，极好的漏电流(Jg＝5×10-4A/cm2@Vg＝-1V)。本发明不局限于本文描述的具体实施方案。许多潜在的高介电常数的栅极介质可能是得益于此现场RTCVD方法。
在不脱离本发明精神和范围的情况下，本领域中普通技术人员可以进行本发明的这些和其它改进和变化。此外，应该清楚可以完全地或部分地互换各种实施方案的方面。此外，本领域中普通技术人员知道：上述说明仅仅是举例，而不是限制本发明，就此范围来说描述在附属的权利要求中。

Claims (33)

1.一种在基材上沉积介质膜的方法，包括：
i)提供一种系统，该系统包括适合容纳该基材的反应容器，及与所述反应容器相联用于加热其中所容纳之基材的能源；和
ii)在所述基材上形成薄膜，所述薄膜是按照包括下列步骤的方法形成的：
a)用所述能源加热基材；
b)当加热基材时向反应容器中提供氧化物气体，该氧化物气体
  包括含至少一个氮原子的化合物，使得该氧化物气体与该基材反
  应，在基材上形成氧氮化物层，该形成层的厚度小于10埃；
c)在所述氧氮化物层上沉积氮化物层，所述沉积是在小于约750
  ℃的温度下发生的；
d)在渗氮退火气体存在下，退火所述的氮化物层；及
e)在氧化物退火气体存在下，于大于约770℃的温度下使该氮化
  物层退火。
2.根据权利要求1的方法，其中所述薄膜的介电常数为约4到约80。
3.根据权利要求1的方法，其中所述含氮化合物包括NO。
4.根据权利要求1的方法，其中所述氮化物层是通过向反应容器中提供第一气体前体和第二气体前体而形成的，所述第一气体前体包括至少含有一个硅原子的化合物，而所述第二气体前体包括至少含有一个氮原子的化合物。
5.根据权利要求4的方法，其中所述第一气体前体包括SiH4。
6.根据权利要求4的方法，其中所述第二气体前体包括NH3。
7.根据权利要求1的方法，其中该基材为含硅的半导体晶片。
8.根据权利要求1的方法，其中所述氧氮化物层是在压力小于50托的气氛中形成的。
9.根据权利要求1的方法，其中所述氮化物层的厚度小于25埃。
10.根据权利要求1的方法，其中所述渗氮退火气体是氨气。
11.根据权利要求1的方法，其中所述氧化物退火气体是N2O。
12.根据权利要求10的方法，其中在所述渗氮退火气体存在下使所述氮化物层退火是在约875℃到约925℃的温度下进行的。
13.一种在基材上沉积介质膜的方法，包括：
在氧化物气体存在下加热含硅的半导体晶片，所述氧化物气体包括NO，所述氧化物气体与半导体晶片反应，在所述晶片上形成氧氮化物层，该氧氮化物层是在足以形成层厚度小于约约10埃的温度、压力和时间下形成的；
接着，在第一气体前体和第二气体前体存在下加热所述半导体晶片，在氧氮化物层上形成氮化物层，所述第一气体前体包括SiH4，所述第二气体前体包括氨气，所述氮化物层是在小于约750℃的温度下形成的，该氮化物层的厚度小于约25埃；
在氨气存在下使所述氮化物层退火；和
此后，在N2O存在下在至少770℃的温度下使所述氮化物层退火。
14.根据权利要求13的方法，其中所述氮化物层是在氨气存在下在约875℃到约925℃的温度下退火的。
15.根据权利要求13的方法，还包括在所述氮化物层上面沉积多晶硅层的步骤。
16.根据权利要求13的方法，还包括将所述介质膜引入电容器中的步骤。
17.根据权利要求13的方法，还包括将所述介质膜引入晶体管中的步骤。
18.一种在半导体晶片上形成介质膜的方法，包括：
在含氮气体存在下加热包含二氧化硅的晶片，以便在所述晶片上形成钝化层；
接着，在气体前体存在下加热所述晶片，所述气体前体在所述晶片上形成包含金属氧化物或硅酸盐的介电层，所述介电层是在大于约300℃的温度下形成的；和
在退火气体存在下使所述介电层退火，所述退火气体包括惰性气体和含氧气体。
19.根据权利要求18的方法，其中所述钝化层的厚度小于约5纳米。
20.根据权利要求18的方法，其中用来形成钝化层的含氮气体包括氨气。
21.根据权利要求20的方法，其中所述钝化层是在小于约10秒钟内在约600到约900℃的温度下形成的。
22.根据权利要求20的方法，其中在形成钝化层的过程中，氨气的分压小于约100托。
23.根据权利要求18的方法，其中所述介电层是在约400到约800℃的温度下形成的，而且其中在形成钝化层的过程中，所述气体前体的分压小于100托。
24.根据权利要求18的方法，其中所述介电层是在约400℃到约900℃的温度下退火的。
25.根据权利要求18的方法，其中在所述退火步骤中存在的含氧气体包括NO、N2O、O2或它们的混合物。
26.根据权利要求25的方法，其中所述惰性气体包括氮气、氩气或它们的混合物。
27.根据权利要求18的方法，其中所述介电层包括：HfO2、ZrO2、Al2O3、Ta2O5、La2O5或它们的硅酸盐。
28.半导体晶片上的一种介质膜，包括：
包含二氧化硅的半导体晶片；
沉积在所述半导体晶片上的钝化层，所述钝化层是通过氨气与所述半导体晶片的表面反应而形成的；
形成于所述钝化层上的介电层，所述介电层包含金属氧化物或硅酸盐；及
其中，所述介电层已经在含氧气体存在下退火。
29.根据权利要求28的介质膜，其中所述钝化层的厚度小于约5纳米。
30.根据权利要求28的介质膜，其中所述介电层包含选自HfO2、ZrO2、Al2O3、Ta2O5、La2O5或其硅酸盐的材料。
31.根据权利要求28的介质膜，其中所说涂层的等值氧化物厚度(EOT)小于约1.2纳米。
32.根据权利要求28的介质膜，其中所述钝化层的厚度小于约1纳米。
33.根据权利要求28的介质膜，其中所述介电层包含HfO2。
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EP1340247A4 (en) 2007-12-26
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