WO2004012237A2 - Methods of forming interfacial layers for high-k gates by ozone oxidation - Google Patents

Methods of forming interfacial layers for high-k gates by ozone oxidation Download PDF

Info

Publication number
WO2004012237A2
WO2004012237A2 PCT/US2003/023798 US0323798W WO2004012237A2 WO 2004012237 A2 WO2004012237 A2 WO 2004012237A2 US 0323798 W US0323798 W US 0323798W WO 2004012237 A2 WO2004012237 A2 WO 2004012237A2
Authority
WO
WIPO (PCT)
Prior art keywords
oxide layer
interfacial oxide
ozone oxidation
interfacial
forming
Prior art date
Application number
PCT/US2003/023798
Other languages
French (fr)
Other versions
WO2004012237A3 (en
Inventor
Yoshihide Senzaki
Robert Herring
Original Assignee
Aviza Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aviza Technology filed Critical Aviza Technology
Priority to AU2003265324A priority Critical patent/AU2003265324A1/en
Publication of WO2004012237A2 publication Critical patent/WO2004012237A2/en
Publication of WO2004012237A3 publication Critical patent/WO2004012237A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates generally to the field of semiconductors. More specifically, the present invention relates to methods of forming interfacial layers for high dielectric constant (high-kj gate stacks by ozone oxidation of silicon substrates at low temperatures.
  • Oxidation processes are often an important step in the fabrication of semiconductor devices.
  • Various equipment is known in the art for conducting oxidation of semiconductor devices. h a batch furnace, or in a single wafer system using a Rapid Thermal Oxidation (RTO) process, silicon wafers are generally ramped up to an elevated temperature (circa 900 C) in an ambient atmosphere of inert gas (such as nitrogen and/or argon) that contains a small percentage of dry oxygen (typically 1-10%). After the wafer is heat stabilized at an oxidation process temperature, a higher concentration of oxygen is introduced, followed by the introduction of steam. A final step may involve purging the steam and ramping down the temperature in an ambient atmosphere of inert gas.
  • This dry/wet oxidation process is used to endow the silicon oxide with better electrical properties, such as lower leakage, higher breakdown voltage, and lower interface trap density, compared to a dry process where silicon oxide is prepared using oxygen without steam.
  • the quality of the resulting silicon oxide in the dry/wet process is an average between the properties of dry and wet silicon oxide, depending upon the amount of dry silicon oxide growth during the ramp up and stabilization steps (the first dry step) in the process. As device geometries are reduced and oxide films become thinner, a greater percentage of the oxide thickness is the oxide grown in the first dry step. This results in an oxide film with poor properties. Therefore, new methods for growing high quality oxides are needed.
  • MOS metal-oxide-silicon
  • dielectric constant (k) greater than silicon oxides which have a k of about 3.9.
  • Silicon nitride (having a k of about 8), and higher dielectric constant metal oxides such as hafnium oxide HfO (having a k of about 20-25), zirconium oxide ZrO 2 (having a k of about 20-25), and hafnium (Hf) and zirconium (Zr) silicates are considered alternative materials to silicon oxide to provide gate dielectrics with high capacitance without compromising the leakage current.
  • interfacial oxide layers are needed for better electrical properties, such as mobility.
  • interfacial oxide layers for gate stacks are conventionally produced by high temperature thermal or steam oxidation, or wet chemical oxidation. With these conventional techniques it is difficult to control oxide thickness and quality, and as stated above, such control is becoming increasing critical. There exists a need for fabrication of improved interfacial oxide layers, particularly interfacial oxide layers formed with better control in thickness, uniformity, and quality.
  • the present invention provides an improved oxidation method in the fabrication of semiconductors. More specifically, the present invention provides a method of producing interfacial oxide layers for high k gate stacks by ozone oxidation at a low temperature. Of particular advantage, the present invention promotes the formation of improved interfacial oxide layers as compared to conventional fabrication methods using high temperature thermal or steam oxidation and wet chemical oxidation. The present invention further provides a method of producing high dielectric constant (k) gate stacks which includes an interfacial oxide layer formed by the ozone oxidation method of the present invention.
  • k dielectric constant
  • an interfacial oxide layer is formed by ozone oxidation at a low temperature on the top surface of a substrate such as a silicon wafer.
  • the ozone oxidation can be performed at a low temperature either thermally or photochemically.
  • the interfacial oxide layer formed by the present ozone oxidation method has controlled thickness, uniformity, and quality.
  • a method of producing a gate structure including an interfacial oxide layer formed by ozone oxidation at a low temperature is provided.
  • an interfacial oxide layer is formed by ozone oxidation at a low temperature on the top surface of a silicon substrate.
  • a dielectric material is then deposited on the top surface of the interfacial oxide layer.
  • the top surface of the interfacial oxide layer is nitrided prior to the deposition of the dielectric material.
  • the deposition of dielectric materials can be performed by chemical vapor deposition, physical vapor deposition, jet vapor deposition, aerosol decomposition, or atomic layer deposition.
  • FIGS. 1A and IB are simplified cross-sectional schematic diagrams of two different apparatus suitable for carrying out the method of the present invention.
  • FIG. 2 is a cross-sectional view of a gate stack structure including an interfacial oxide layer formed by ozone oxidation according to one embodiment of the present invention.
  • FIG. 3 is graph illustrating interfacial oxide growth on a silicon substrate according to two embodiments of the present invention.
  • the present invention provides a method of producing an interfacial oxide layer for gate structures.
  • an interfacial oxide layer is formed by ozone oxidation at a low temperature on the top surface of a substrate such as a silicon wafer.
  • the ozone oxidation can be performed at a low temperature either thermally or photochemically.
  • the interfacial oxide layer formed by the present ozone oxidation method has controlled thickness, uniformity, and quality.
  • the present method comprises a step of forming an interfacial oxide layer by ozone oxidation at a low temperature of a silicon substrate.
  • the ozone oxidation can be performed thermally or photochemically.
  • the ozone oxidation is carried out at a temperature in the range of approximately 25°C to 600°C.
  • the ozone oxidation is carried out at a temperature in the range of approximately 250°C to 450°C. These temperature ranges are significantly less than conventional oxidation treatment methods.
  • oxidation is carried out with ozone at a concentration in the range of approximately 120 g/m to 240 g/m , with an ozone exposure time of approximately 30 seconds.
  • the ozone oxidation reaction can be summarized in the following equations:
  • Ozone is disassociated into oxygen molecules and atomic oxygen under thermal or photochemical conditions.
  • the temperature of the method is carried out at the lower end of the recited range.
  • the atomic oxygen reacts with silicon on the top surface of the silicon substrate to form an interfacial oxide layer.
  • the method of the present invention may be carried out in any suitable equipment known in the art.
  • Oxidation systems are well known in the industry. Examples of suitable systems include that described in U.S. Patent No. 6,300,600, entitled Hot Wall Rapid Thermal Processor, and U.S. Provisional Patent Application Serial No. 60/428,526, filed November 22, 2002, entitled Thermal Processing System and Method for Using the Same, both of which are incorporated herein by reference in their entirety.
  • the oxidation method may also be carried out in an atomic layer deposition system. As such systems are well known, they are not described in detail herein but two examples are shown in a simplified manner in FIGS. 1 A and IB. Referring to FIG. 1 A, a hot wall chamber type system 101 is partially shown in a cross sectional view.
  • This type of system processes a batch of wafers.
  • a plurality of wafers 100 are stacked vertically in the chamber.
  • Heater elements (not shown) are provided to heat the environment of the wafer 100. Gases are conveyed to and from the chamber 101 via inlet 104 and outlet 105, respectively.
  • a cold wall chamber type system 102 is partially shown in a cross sectional view.
  • a single wafer 100 is processes in the chamber.
  • the wafer is supported and heated by a heated support or chuck 103.
  • Gases are conveyed to and from the chamber 102 via inlet 104 and outlet 105, respectively.
  • Those skilled in the art will recognize that other system may be used to carry out the method of the present invention.
  • an interfacial oxide layer is first formed on the top surface of a substrate by ozone oxidation at a low temperature.
  • the temperature is in the range of approximately 25°C to 600°C. In another example the temperature is in the range of approximately 250°C to 450°C.
  • Dielectric materials are then deposited on the top of the interfacial oxide layer by a variety of deposition methods.
  • a silicon substrate or wafer 200 is provided as the substrate of a gate structure.
  • the substrate is placed in a chamber and exposed to ozone to oxidize the top surface of the substrate.
  • the substrate is exposed to ozone at a concentration in the range of approximately 120 g/m3 to 240 g/m3, for an exposure time of about 30 seconds.
  • Oxygen gas may also be conveyed to the chamber.
  • oxygen is conveyed to the chamber at a total flow rate of about 200 seem.
  • Ozone oxidation is performed either thermally or photochemically at a temperature in the range of approximately 25°C to 600°C, more usually in a range of approximately 250°C to 450°C, to form an interfacial oxide layer 202 on the top surface of the silicon substrate.
  • the interfacial oxide layer is comprised of SiO 2 .
  • the thickness of the interfacial oxide layer may vary as desired, and in one example interfacial oxide layers having a thickness in the range of approximately 3 A to 9 A are grown.
  • layers of dielectric materials are deposited sequentially on the top of the interfacial oxide layer 202.
  • one or more dielectric layers 204 are formed atop the interfacial layer 202.
  • the dielectric layer 204 may be comprised of a mid-k dielectric material such as silicon nitride, or alternatively may be comprised of a high-k dielectric material such as HfO 2 , ZrO 2 , hafnium silicate, zirconium silicate and the like.
  • the dielectric layer 204 may be comprised of a plurality of layers.
  • the top surface of the interfacial oxide layer be thermally nitrided in NH 3 to form a nitrided oxide (SiON) layer 206 prior to deposition of mid- and/or high-k dielectric layers.
  • a nitrided oxide (SiON) layer 206 prior to deposition of mid- and/or high-k dielectric layers.
  • a gate electrode 208 is formed on the top of the dielectric layers 204.
  • the gate electrode may be formed of polysilicon, polySi-Ge, a metal gate material and the like, and is formed by well known conventional techniques.
  • the dielectric layers 204 on the top surface of the interfacial layer 202 can be formed by a variety of methods well known in the art, and typically are formed by conventional deposition techniques including but not limited to chemical vapor deposition (CVD) such as thermal CVD, plasma CVD, laser CVD, and photo assisted CVD, physical vapor deposition (PVD), jet vapor deposition, aerosol decomposition, or atomic layer deposition (ALD) such as thermal ALD and photo-assisted ALD.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the interfacial oxide thickness increased with the ozone concentration and temperature.

Abstract

A new method of forming an interfacial oxide layer for gate structures is provided. The method comprises ozone oxidation of a silicon substrate at low temperatures to form an interfacial oxide layer. A method of making gate stacks is also provided which includes forming an interfacial oxide layer on the top surface of a silicon substrate by ozone oxidation at a low temperature, and depositing dielectric layers on the top of the interfacial oxide layer.

Description

OZONE OXIDATION OF SILICON SUBSTRATES FOR FORMATION OF AN INTERFACIAL LAYER FOR HIGH-K GATE STACKS
CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Provisional Patent Application Serial No. 60/399,463 filed July 29, 2002, entitled "Ozone Oxidation of Silicon Substrates for Formation of an Interfacial Layer for Higl -K Gate Stacks," the entire disclosure of which is hereby incorporated by reference. This application is related to U.S. Provisional Patent Application Serial No. 60/396,733 filed July 19, 2002, entitled "Steam Oxidation for the Formation of Thin Gate and Capacitor Dielectrics with Improved Electrical Properties;" and U.S. Provisional Patent Application Serial No. 60/396,742 filed July 19, 2002, entitled "Low Temperature Ozone of Gate and Capacitor Dielectrics," the disclosures of both or which are hereby incorporated by reference in their entirety.
FIELD OF THE INVENTION The present invention relates generally to the field of semiconductors. More specifically, the present invention relates to methods of forming interfacial layers for high dielectric constant (high-kj gate stacks by ozone oxidation of silicon substrates at low temperatures.
BACKGROUND OF THE INVENTION Oxidation processes are often an important step in the fabrication of semiconductor devices. Various equipment is known in the art for conducting oxidation of semiconductor devices. h a batch furnace, or in a single wafer system using a Rapid Thermal Oxidation (RTO) process, silicon wafers are generally ramped up to an elevated temperature (circa 900 C) in an ambient atmosphere of inert gas (such as nitrogen and/or argon) that contains a small percentage of dry oxygen (typically 1-10%). After the wafer is heat stabilized at an oxidation process temperature, a higher concentration of oxygen is introduced, followed by the introduction of steam. A final step may involve purging the steam and ramping down the temperature in an ambient atmosphere of inert gas. This dry/wet oxidation process is used to endow the silicon oxide with better electrical properties, such as lower leakage, higher breakdown voltage, and lower interface trap density, compared to a dry process where silicon oxide is prepared using oxygen without steam.
However, the quality of the resulting silicon oxide in the dry/wet process is an average between the properties of dry and wet silicon oxide, depending upon the amount of dry silicon oxide growth during the ramp up and stabilization steps (the first dry step) in the process. As device geometries are reduced and oxide films become thinner, a greater percentage of the oxide thickness is the oxide grown in the first dry step. This results in an oxide film with poor properties. Therefore, new methods for growing high quality oxides are needed.
As the future device scale aggressively reduces, alternative high-k dielectrics to conventional silicon dioxide dielectrics (SiO2) are actively sought. Semiconductor devices of future generation require thin dielectric films for metal-oxide-silicon (MOS) transistor gates and capacitor dielectrics. As oxides are scaled down, the tunneling leakage current becomes significant and limits the useful range for gate oxides to about 1.8 nm or more.
To address this problem, different dielectric materials are being evaluated, particularly materials exhibiting a dielectric constant (k) greater than silicon oxides (which have a k of about 3.9). Silicon nitride (having a k of about 8), and higher dielectric constant metal oxides such as hafnium oxide HfO (having a k of about 20-25), zirconium oxide ZrO2 (having a k of about 20-25), and hafnium (Hf) and zirconium (Zr) silicates are considered alternative materials to silicon oxide to provide gate dielectrics with high capacitance without compromising the leakage current. For advanced high-k or oxide/nitride (ON) gate stacks, high quality thin interfacial oxide layers are needed for better electrical properties, such as mobility. In the prior art, interfacial oxide layers for gate stacks are conventionally produced by high temperature thermal or steam oxidation, or wet chemical oxidation. With these conventional techniques it is difficult to control oxide thickness and quality, and as stated above, such control is becoming increasing critical. There exists a need for fabrication of improved interfacial oxide layers, particularly interfacial oxide layers formed with better control in thickness, uniformity, and quality.
SUMMARY OF THE INVENTION In general, the present invention provides an improved oxidation method in the fabrication of semiconductors. More specifically, the present invention provides a method of producing interfacial oxide layers for high k gate stacks by ozone oxidation at a low temperature. Of particular advantage, the present invention promotes the formation of improved interfacial oxide layers as compared to conventional fabrication methods using high temperature thermal or steam oxidation and wet chemical oxidation. The present invention further provides a method of producing high dielectric constant (k) gate stacks which includes an interfacial oxide layer formed by the ozone oxidation method of the present invention. In one aspect of the present invention, an interfacial oxide layer is formed by ozone oxidation at a low temperature on the top surface of a substrate such as a silicon wafer. The ozone oxidation can be performed at a low temperature either thermally or photochemically. The interfacial oxide layer formed by the present ozone oxidation method has controlled thickness, uniformity, and quality.
In another aspect of the present invention a method of producing a gate structure including an interfacial oxide layer formed by ozone oxidation at a low temperature is provided. In accordance with this embodiment, an interfacial oxide layer is formed by ozone oxidation at a low temperature on the top surface of a silicon substrate. A dielectric material is then deposited on the top surface of the interfacial oxide layer. Preferably the top surface of the interfacial oxide layer is nitrided prior to the deposition of the dielectric material. The deposition of dielectric materials can be performed by chemical vapor deposition, physical vapor deposition, jet vapor deposition, aerosol decomposition, or atomic layer deposition.
BRIEF DESCRIPTION OF THE FIGURES
The foregoing and other objects of the invention will be more clearly understood from the following description when read in conjunction with the accompanying drawings in which:
FIGS. 1A and IB are simplified cross-sectional schematic diagrams of two different apparatus suitable for carrying out the method of the present invention.
FIG. 2 is a cross-sectional view of a gate stack structure including an interfacial oxide layer formed by ozone oxidation according to one embodiment of the present invention.
FIG. 3 is graph illustrating interfacial oxide growth on a silicon substrate according to two embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION hi general, the present invention provides a method of producing an interfacial oxide layer for gate structures. In one aspect of the present invention, an interfacial oxide layer is formed by ozone oxidation at a low temperature on the top surface of a substrate such as a silicon wafer. The ozone oxidation can be performed at a low temperature either thermally or photochemically. The interfacial oxide layer formed by the present ozone oxidation method has controlled thickness, uniformity, and quality.
In particular, the present method comprises a step of forming an interfacial oxide layer by ozone oxidation at a low temperature of a silicon substrate. The ozone oxidation can be performed thermally or photochemically. The ozone oxidation is carried out at a temperature in the range of approximately 25°C to 600°C. In another embodiment the ozone oxidation is carried out at a temperature in the range of approximately 250°C to 450°C. These temperature ranges are significantly less than conventional oxidation treatment methods. In one exemplary embodiment, oxidation is carried out with ozone at a concentration in the range of approximately 120 g/m to 240 g/m , with an ozone exposure time of approximately 30 seconds. The ozone oxidation reaction can be summarized in the following equations:
03 → 02 + O (1)
Si + 20 → Si02 (2)
Ozone is disassociated into oxygen molecules and atomic oxygen under thermal or photochemical conditions. When the oxidation method is carried out with photochemical excitation, the temperature of the method is carried out at the lower end of the recited range. The atomic oxygen reacts with silicon on the top surface of the silicon substrate to form an interfacial oxide layer.
The method of the present invention may be carried out in any suitable equipment known in the art. Oxidation systems are well known in the industry. Examples of suitable systems include that described in U.S. Patent No. 6,300,600, entitled Hot Wall Rapid Thermal Processor, and U.S. Provisional Patent Application Serial No. 60/428,526, filed November 22, 2002, entitled Thermal Processing System and Method for Using the Same, both of which are incorporated herein by reference in their entirety. The oxidation method may also be carried out in an atomic layer deposition system. As such systems are well known, they are not described in detail herein but two examples are shown in a simplified manner in FIGS. 1 A and IB. Referring to FIG. 1 A, a hot wall chamber type system 101 is partially shown in a cross sectional view. This type of system processes a batch of wafers. In this embodiment, a plurality of wafers 100 are stacked vertically in the chamber. Heater elements (not shown) are provided to heat the environment of the wafer 100. Gases are conveyed to and from the chamber 101 via inlet 104 and outlet 105, respectively.
Referring to FIG. IB, a cold wall chamber type system 102 is partially shown in a cross sectional view. In this embodiment, a single wafer 100 is processes in the chamber. The wafer is supported and heated by a heated support or chuck 103. Gases are conveyed to and from the chamber 102 via inlet 104 and outlet 105, respectively. Those skilled in the art will recognize that other system may be used to carry out the method of the present invention.
The present invention of forming an interfacial oxide layer is advantageous in preparing high k gate structures. In preparing such gate structures, an interfacial oxide layer is first formed on the top surface of a substrate by ozone oxidation at a low temperature. In one example the temperature is in the range of approximately 25°C to 600°C. In another example the temperature is in the range of approximately 250°C to 450°C. Dielectric materials are then deposited on the top of the interfacial oxide layer by a variety of deposition methods.
One embodiment of the present invention of making gate stacks is now described in more detail with reference to FIG. 2. A silicon substrate or wafer 200 is provided as the substrate of a gate structure. The substrate is placed in a chamber and exposed to ozone to oxidize the top surface of the substrate. In one example, the substrate is exposed to ozone at a concentration in the range of approximately 120 g/m3 to 240 g/m3, for an exposure time of about 30 seconds. Oxygen gas may also be conveyed to the chamber. In one example oxygen is conveyed to the chamber at a total flow rate of about 200 seem. Ozone oxidation is performed either thermally or photochemically at a temperature in the range of approximately 25°C to 600°C, more usually in a range of approximately 250°C to 450°C, to form an interfacial oxide layer 202 on the top surface of the silicon substrate. In this example the interfacial oxide layer is comprised of SiO2. The thickness of the interfacial oxide layer may vary as desired, and in one example interfacial oxide layers having a thickness in the range of approximately 3 A to 9 A are grown. After the interfacial layer 202 is formed by ozone oxidation, layers of dielectric materials are deposited sequentially on the top of the interfacial oxide layer 202. In one embodiment, one or more dielectric layers 204 (such as a metal oxide layer and the like ) are formed atop the interfacial layer 202. The dielectric layer 204 may be comprised of a mid-k dielectric material such as silicon nitride, or alternatively may be comprised of a high-k dielectric material such as HfO2, ZrO2, hafnium silicate, zirconium silicate and the like. The dielectric layer 204 may be comprised of a plurality of layers.
For preparing high-k gate stacks, it is preferred that the top surface of the interfacial oxide layer be thermally nitrided in NH3 to form a nitrided oxide (SiON) layer 206 prior to deposition of mid- and/or high-k dielectric layers. Forming the nitrided oxide layer 206 avoids additional oxide growth in contact with the high-k metal oxide during the mid- or high dielectric deposition, or a post-gate stack deposition thermal treatment.
To form a gate device, a gate electrode 208 is formed on the top of the dielectric layers 204. The gate electrode may be formed of polysilicon, polySi-Ge, a metal gate material and the like, and is formed by well known conventional techniques. The dielectric layers 204 on the top surface of the interfacial layer 202 can be formed by a variety of methods well known in the art, and typically are formed by conventional deposition techniques including but not limited to chemical vapor deposition (CVD) such as thermal CVD, plasma CVD, laser CVD, and photo assisted CVD, physical vapor deposition (PVD), jet vapor deposition, aerosol decomposition, or atomic layer deposition (ALD) such as thermal ALD and photo-assisted ALD.
Experimental Several experiments were performed with the method of the present invention. Silicon substrates were placed in an oxidation chamber and exposed to ozone to oxidize the surface of the silicon substrate, forming an interfacial oxide layer thereon. The silicon substrates were exposed to ozone for a total ozone exposure time of 30 seconds. Oxygen was also conveyed to the chamber at a total oxygen flow rate of 200 seem. The silicon substrate temperature was varied from 250 °C to 450 °C and the ozone concentration was varied from 120 g/m3 to 240 g/m3. The resultant interfacial oxide growth thickness (A) is summarized in Table 1 below, and is graphically depicted in FIG. 3.
Table 1
Figure imgf000009_0001
As illustrated in Table 1 and FIG. 3, the interfacial oxide thickness increased with the ozone concentration and temperature.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than limiting sense, as it is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the scope of the invention and the scope of the appended claims.

Claims

CLAIMSWhat is claimed:
1. A method of producing an interfacial oxide layer on a semiconductor substrate, comprising: forming an interfacial oxide layer on top of the substrate by ozone oxidation at a temperature in the range of approximately 25°C to 600 °C .
2. The method of claim 1 wherein the ozone oxidation is carried out with photochemical excitation .
3. The method of claim 1 further comprising the step of: exposing the surface of the interfacial oxide layer to NH3 to form a nitrided oxide layer on top of the interfacial oxide layer.
4. A method of forming a gate structure on a substrate, comprising: forming an interfacial oxide layer by ozone oxidation at a low temperature on a top surface of the substrate; and depositing one or more dielectric layers on the top surface of the interfacial oxide layer.
5. The method of claim 4 further comprising: nitriding the top surface of the interfacial oxide layer prior to depositing the one or more dielectric layers.
6. The method of claim 4 wherein the step of forming the interfacial oxide layer is carried out at a temperature ranging from approximately 250°C to 450°C.
7. The method of claim 4 wherein the step of depositing one or more dielectric layers is performed by chemical vapor deposition, physical vapor deposition, jet vapor deposition, aerosol decomposition, or atomic layer deposition.
8. The method of claim 4 further comprising: depositing a gate electrode atop the one or more dielectric layers.
9. The method of claim 4 where said one or more dielectric layers are comprised of any of the following materials: silicon nitride, HfO , ZrO2, hafnium silicate and zirconium silicate.
10. The method of claim 4 wherein the step of forming the interfacial oxide layer is carried out with photochemical excitation.
PCT/US2003/023798 2002-07-29 2003-07-29 Methods of forming interfacial layers for high-k gates by ozone oxidation WO2004012237A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003265324A AU2003265324A1 (en) 2002-07-29 2003-07-29 Methods of forming interfacial layers for high-k gates by ozone oxidation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39946302P 2002-07-29 2002-07-29
US60/399,463 2002-07-29

Publications (2)

Publication Number Publication Date
WO2004012237A2 true WO2004012237A2 (en) 2004-02-05
WO2004012237A3 WO2004012237A3 (en) 2004-09-10

Family

ID=31188587

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/023798 WO2004012237A2 (en) 2002-07-29 2003-07-29 Methods of forming interfacial layers for high-k gates by ozone oxidation

Country Status (3)

Country Link
AU (1) AU2003265324A1 (en)
TW (1) TW200414356A (en)
WO (1) WO2004012237A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6325017B1 (en) * 1997-02-27 2001-12-04 Micron Technology, Inc. Apparatus for forming a high dielectric film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6325017B1 (en) * 1997-02-27 2001-12-04 Micron Technology, Inc. Apparatus for forming a high dielectric film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KUROKAWA A. ET AL.: 'Ultrathin silicon dioxide formation by ozone on ultraflat si surface' MAT. RES. SOC. SYMP. PROC. vol. 567, 02 April 1999 - 08 April 1999, pages 21 - 26, XP000897802 *

Also Published As

Publication number Publication date
WO2004012237A3 (en) 2004-09-10
AU2003265324A8 (en) 2004-02-16
AU2003265324A1 (en) 2004-02-16
TW200414356A (en) 2004-08-01

Similar Documents

Publication Publication Date Title
KR100848423B1 (en) Dielectric coating and method of forming a dielectric coating
JP4281082B2 (en) Surface preparation method before deposition
US7498270B2 (en) Method of forming a silicon oxynitride film with tensile stress
JP4895803B2 (en) Dielectric film and gate stack forming method, and dielectric film processing method
US7429540B2 (en) Silicon oxynitride gate dielectric formation using multiple annealing steps
US20040175961A1 (en) Two-step post nitridation annealing for lower EOT plasma nitrided gate dielectrics
US20030185980A1 (en) Thin film forming method and a semiconductor device manufacturing method
JP2007516599A (en) Surface preparation before deposition on germanium
US6866890B2 (en) Method of forming a dielectric film
JP2006237371A (en) Method of depositing metallic gate on high-k dielectric film, method of improving interface between the high-k dielectric film and the metallic gate, and substrate processing system
KR20050033831A (en) Manufacturing method of insulator film and insulator film, and manufacturing method of semiconductor device and semiconductor device
US20020009900A1 (en) Growth of ultrathin nitride on Si (100) by rapid thermal N2 treatment
KR101033399B1 (en) Method for oxidation of objects to be treated
WO2004012237A2 (en) Methods of forming interfacial layers for high-k gates by ozone oxidation
JP2008258614A (en) Method of growing thin oxynitride film on substrate
KR19990088398A (en) A method to locate particles of a predetermined species within a solid and resulting structures
JP2002540628A (en) Method of fabricating high dielectric constant dielectric stack with low buffer oxide
JP4933256B2 (en) Method for forming a semiconductor microstructure
JP2006269620A (en) Method and apparatus for wet film formation using ald
JP4416354B2 (en) Semiconductor device manufacturing method and manufacturing apparatus thereof
JP2006093240A (en) Method of forming film
KR20040086495A (en) Method of manufacturing semiconductor device, semiconductor device and apparatus for manufacturing semiconductor device
KR20010063732A (en) Method of manufacturing a semiconductor device utilizing a gate dielelctric
WO2004010465A2 (en) Thin dielectric formation by steam oxidation
WO2004010468A2 (en) Low temperature ozone anneal of gate and capacitor dielectrics

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP