WO2004010465A2 - Thin dielectric formation by steam oxidation - Google Patents

Thin dielectric formation by steam oxidation Download PDF

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Publication number
WO2004010465A2
WO2004010465A2 PCT/US2003/022059 US0322059W WO2004010465A2 WO 2004010465 A2 WO2004010465 A2 WO 2004010465A2 US 0322059 W US0322059 W US 0322059W WO 2004010465 A2 WO2004010465 A2 WO 2004010465A2
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Prior art keywords
steam
wafer
temperature
oxidation
chamber
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PCT/US2003/022059
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French (fr)
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WO2004010465A3 (en
Inventor
Yoshihide Senzaki
Yakov Brichko
Robert B. Herring
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Aviza Technology, Inc.
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Priority to AU2003251914A priority Critical patent/AU2003251914A1/en
Publication of WO2004010465A2 publication Critical patent/WO2004010465A2/en
Publication of WO2004010465A3 publication Critical patent/WO2004010465A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to the oxidation of semiconductor wafers. More particularly, the present invention relates to the steam oxidation of silicon wafers to form thin gate and capacitor dielectric layers with improved electrical properties.
  • Oxidation processes are often an important step in the fabrication of semiconductor devices.
  • Various equipment is known in the art for conducting oxidation of semiconductor devices.
  • silicon wafers are generally ramped up to an elevated temperature (circa 900°C) in an ambient atmosphere of inert gas (such as nitrogen and/or argon) that contains a small percentage of dry oxygen (typically 1-10%).
  • inert gas such as nitrogen and/or argon
  • a higher concentration of oxygen is introduced, followed by the introduction of steam.
  • a final step may involve purging the steam and ramping down the temperature in an ambient atmosphere of inert gas.
  • This dry/wet oxidation process is used to endow the silicon oxide with better electrical properties, such as lower leakage, higher breakdown voltage, and lower interface trap density, compared to a dry process where silicon oxide is prepared using oxygen without steam.
  • the quality of the resulting silicon oxide in the dry/wet process is an average between the properties of dry and wet silicon oxide, depending upon the amount of dry silicon oxide growth during the ramp up and stabilization steps (the first dry step) in the process. As device geometries are reduced and oxide films become thinner, a greater percentage of the oxide thickness is the oxide grown in the first dry step. This results in an oxide film with poor properties. Therefore, new methods for growing high quality oxides are- needed.
  • improved oxide properties can be obtained in a single wafer Rapid Thermal Process ("RTP") by beginning steam oxidation without stabilizing the wafer in dry oxygen.
  • RTP Rapid Thermal Process
  • the method introduces steam during, rather than after, heating, to initiate steam oxidation.
  • the only oxidants employed during the method are steam and a mixture of steam and other oxidants.
  • Other oxidants that may be utilized with the steam include atomic oxygen (O), oxygen gas (O 2 ) and ozone (O 3 ).
  • the method of the present invention comprises the following steps: (i) loading a silicon wafer into a reactor chamber; (ii) raising the temperature of the wafer in the presence of steam; and (iii) cooling the wafer and removing it from the reactor chamber.
  • FIGS. 1A and IB are flow charts comparing the steps in the prior art and the present invention, respectively;
  • FIG. 2 is a graph of leakage current density (Jg) versus Vgs for a 900 °C wet oxidation using various oxygen flows during the temperature ramp and stabilization as practiced in the prior art.
  • FIG. 3 is a graph of leakage current density (Jg) versus Vgs for wet oxidation processes at different process temperatures and compares the prior art with the present invention.
  • FIG. 4 is a series of Weibull plots for wet oxidation processes with and without a ramp and stabilization step at 900 °C.
  • the present invention provides a method of oxidation without the step of stabilizing the wafer in dry oxygen.
  • Steam is introduced into an oxidation system, and particularly a process chamber, upon bringing each silicon substrate into a heater zone of the chamber.
  • Thermal stabilization of the substrates in an inert ambient followed by a higher concentration of oxygen is not necessary as is done in the prior art.
  • all of the silicon oxide is grown in the presence of steam. The inventors have discovered that the silicon oxide grown by this all wet oxidation cycle exhibits better electrical properties than silicon oxide grown using a dry plus wet oxidation cycle.
  • the all wet oxidation method of the present invention results in shorter processing times which is important for achieving high throughput in a single wafer process.
  • the temperature ramp and stabilization step typically took 60 to 90 seconds before the steam was introduced into the chamber.
  • the steam is introduced substantially simultaneously as the temperature ramp is started, which results in a shorter time for the process and, thereby, increases the number of wafers per hour that can be processed.
  • the invention is particularly suitable for use in the production of gate oxides but may be used for many other processes.
  • the invention may be utilized for the production of nitrided gate oxides, i.e., oxides formed by steam oxidation followed by nitric oxide (NO) or nitrous oxide (N 2 O) anneal or plasma nitridation.
  • the invention is useful for forming bottom oxides for oxide-nitride-oxide (ONO) stacks for capacitor applications or gate applications for FLASH memory devices.
  • the electrical properties of the ONO stacks can be further improved by using a sequential ammonia/nitrous oxide (NH /N 2 O) two-step anneal of the nitride layer and a N 2 O anneal of the top oxide layer deposited by CVD.
  • a sequential ammonia/nitrous oxide (NH /N 2 O) two-step anneal of the nitride layer and a N 2 O anneal of the top oxide layer deposited by CVD a sequential ammonia/nitrous oxide (NH /N 2 O) two-step anneal of the nitride layer and a N 2 O anneal of the top oxide layer deposited by CVD.
  • NH /N 2 O sequential ammonia/nitrous oxide
  • FIGS. 1 A and IB a side by side flow chart comparison of the method steps required by previous dry/wet oxidation processes versus the preferred wet only process used in the instant invention are shown .
  • a wafer is loaded into the chamber, ramped to an elevated temperature (circa 900°C) in the presence of steam, and then cooled and removed from the reactor.
  • the entire SiO 2 formation is in the presence of steam.
  • the wafer is ramped in the presence N 2 /O 2 to an elevated temperature, followed by the introduction of steam, and then cooled and removed from the reactor.
  • the silicon wafers are typically processed through a dilute hydrogen fluoride (HF) bath to remove the native oxide present on the surface of the wafers.
  • HF dilute hydrogen fluoride
  • the silicon wafers are placed into a reaction chamber using automation techniques commonly found in semiconductor processing equipment.
  • the process chamber can have any configuration known in the art to provide a means for supporting the wafer, heating the wafer, and exposing the wafer to various gasses in a controlled manner. As such systems are well known, they are not described further herein.
  • the heating of the silicon wafers can be accomplished by any means known in the art.
  • Illustrative heating methods include a resistively heated stage, a lamp heating mechanism, a radiant heating mechanism that employs resistively heated coils such as those found in a furnace, and the like.
  • the process chamber is elevated to a temperature within the range of about 500°C to 1300°C at a ramp rate of about
  • the chamber is elevated to a temperature within the range of about 700°C to 1100°C at a ramp rate of about 30°C/sec to
  • a gas distribution system is typically used and can be any gas distribution system known in the art.
  • Illustrative gas distribution systems include a showerhead design, a gas ring design, a gas injector design and the like.
  • the gas flow rate is typically in the range of 50 seem to 30,000 seem for a time period of about 0.1 sec to 3.6 sec.
  • the gas flow rate is in the range of 100 seem to 20,000 seem for a time period of about 0.5 sec to 1.0 sec.
  • the silicon wafer support can be any support known in the art.
  • Illustrative supports include a plate design, a ring design, a pin design and the like.
  • Example 1 To better illustrate the invention and the benefits therein, namely the improved electrical characteristics obtained and the higher throughput achieved compared to conventions dry/wet oxidation processes, the following illustrative example is provided.
  • Example 1 To better illustrate the invention and the benefits therein, namely the improved electrical characteristics obtained and the higher throughput achieved compared to conventions dry/wet oxidation processes, the following illustrative example is provided.
  • Example 1 To better illustrate the invention and the benefits therein, namely the improved electrical characteristics obtained and the higher throughput achieved compared to conventions dry/wet oxidation processes, the following illustrative example is provided.
  • silicon wafers were ramped to 900°C while flowing a mixture of nitrogen and oxygen.
  • concentration of oxygen in such processes can vary from 0% (pure nitrogen) to 100% (pure oxygen).
  • Typical flow rates are in the range of 0 slpm to 20 slpm.
  • Steam was then introduced for a period of time to grow a SiO 2 film of desired thickness (in this example 30 A). The wafers were then either annealed within the same chamber to further optimize the film properties or cooled down and removed from the chamber.
  • the temperature of the silicon wafers was ramped to 900°C while steam was introduced from the outset of temperature ramping and directly into the chamber.
  • the temperature ramp and stabilization of the silicon wafers did not occur in an atmosphere of nitrogen and oxygen as practiced in the prior art.
  • the flow of steam was stopped.
  • the wafers were then either annealed within the same chamber to further optimize the film properties, or the wafer is cooled down and removed from the chamber.
  • FIG. 2 is a plot of Jg vs Vgs for the prior art method for several different flows of dry oxygen (from 0 slpm to 20 slpm) during the process of ramping and stabilizing the temperature before the introduction of the steam. It can be seen that the value of Jg is not sensitive to the flow of oxygen during this step.
  • FIG. 3 shows the benefits of the present invention by plotting Jg vs Vgs for both the prior art method (with a nitrogen flow during the temperature ramp step) and the method of the present invention (which introduces steam during the temperature ramp step).
  • the leakage current density for the present invention is significantly lower than the prior art in the ' region of interest around -1 volt indicating improved electrical properties of the film.
  • FIG. 4 also shows the benefits of the present invention by providing Weibull plots for the leakage current density for two versions of prior art methods where the wafer is treated with either oxygen or nitrogen during the temperature ramp and stabilization step as well as the present invention where the steam is introduced at the beginning of this step.
  • the present invention clearly shows lower values of Jg, a desirable result.
  • the examples cited here used a film thickness of 30 A and a growth temperature of 900°C. It will be clear to those skilled in the art that these are merely illustrative and SiO 2 layers of any thickness can be generated using any temperature commonly used to grow SiO 2 films used in semiconductor device manufacture.

Abstract

The present invention relates to the steam oxidation of silicon wafers to form thin gate and capacitor dielectrics with improved electrical properties. In the present invention, improved oxide properties are obtained in a single wafer Rapid Thermal Process ('RTP') by beginning steam oxidation without stabilizing the silicon wafer in dry oxygen.

Description

STEAM OXIDATION METHOD FOR THE FORMATION OF THIN GATE AND CAPACITOR DIELECTRICS WITH IMPROVED ELECTRICAL PROPERTIES
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to, and claims priority to, United States Provisional Patent Application No. 60/396,733, entitled Steam Oxidation For The Formation Of Thin Gate And Capacitor Dielectrics With Improved Electrical Properties, filed July 19, 2002, the disclosure of which is hereby incorporated by reference in its entirety.
FIELD OF THE INVENTION
In general the present invention relates to the oxidation of semiconductor wafers. More particularly, the present invention relates to the steam oxidation of silicon wafers to form thin gate and capacitor dielectric layers with improved electrical properties.
BACKGROUND OF THE INVENTION
Oxidation processes are often an important step in the fabrication of semiconductor devices. Various equipment is known in the art for conducting oxidation of semiconductor devices.
In a batch furnace, or in a single wafer system using a Rapid Thermal Oxidation (RTO) process, silicon wafers are generally ramped up to an elevated temperature (circa 900°C) in an ambient atmosphere of inert gas (such as nitrogen and/or argon) that contains a small percentage of dry oxygen (typically 1-10%). After the wafer is heat stabilized at an oxidation process temperature, a higher concentration of oxygen is introduced, followed by the introduction of steam. A final step may involve purging the steam and ramping down the temperature in an ambient atmosphere of inert gas. This dry/wet oxidation process is used to endow the silicon oxide with better electrical properties, such as lower leakage, higher breakdown voltage, and lower interface trap density, compared to a dry process where silicon oxide is prepared using oxygen without steam.
However, the quality of the resulting silicon oxide in the dry/wet process is an average between the properties of dry and wet silicon oxide, depending upon the amount of dry silicon oxide growth during the ramp up and stabilization steps (the first dry step) in the process. As device geometries are reduced and oxide films become thinner, a greater percentage of the oxide thickness is the oxide grown in the first dry step. This results in an oxide film with poor properties. Therefore, new methods for growing high quality oxides are- needed.
SUMMARY OF THE INVENTION
According to the present invention, improved oxide properties can be obtained in a single wafer Rapid Thermal Process ("RTP") by beginning steam oxidation without stabilizing the wafer in dry oxygen. The method introduces steam during, rather than after, heating, to initiate steam oxidation. The only oxidants employed during the method are steam and a mixture of steam and other oxidants. Other oxidants that may be utilized with the steam include atomic oxygen (O), oxygen gas (O2) and ozone (O3).
In one aspect, the method of the present invention comprises the following steps: (i) loading a silicon wafer into a reactor chamber; (ii) raising the temperature of the wafer in the presence of steam; and (iii) cooling the wafer and removing it from the reactor chamber.
BRIEF DESCRIPTION OF DRAWINGS
The invention will be described in the following detailed description and with reference to the following figures:
FIGS. 1A and IB are flow charts comparing the steps in the prior art and the present invention, respectively;
FIG. 2 is a graph of leakage current density (Jg) versus Vgs for a 900 °C wet oxidation using various oxygen flows during the temperature ramp and stabilization as practiced in the prior art.
FIG. 3 is a graph of leakage current density (Jg) versus Vgs for wet oxidation processes at different process temperatures and compares the prior art with the present invention. FIG. 4 is a series of Weibull plots for wet oxidation processes with and without a ramp and stabilization step at 900 °C.
DETAILED DESCRIPTION OF THE INVENTION
In general, the present invention provides a method of oxidation without the step of stabilizing the wafer in dry oxygen. Steam is introduced into an oxidation system, and particularly a process chamber, upon bringing each silicon substrate into a heater zone of the chamber. Thermal stabilization of the substrates in an inert ambient followed by a higher concentration of oxygen is not necessary as is done in the prior art. In the present invention all of the silicon oxide is grown in the presence of steam. The inventors have discovered that the silicon oxide grown by this all wet oxidation cycle exhibits better electrical properties than silicon oxide grown using a dry plus wet oxidation cycle.
In addition, the all wet oxidation method of the present invention results in shorter processing times which is important for achieving high throughput in a single wafer process. In the prior art, the temperature ramp and stabilization step typically took 60 to 90 seconds before the steam was introduced into the chamber. In the present invention, the steam is introduced substantially simultaneously as the temperature ramp is started, which results in a shorter time for the process and, thereby, increases the number of wafers per hour that can be processed.
The invention is particularly suitable for use in the production of gate oxides but may be used for many other processes. For example, the invention may be utilized for the production of nitrided gate oxides, i.e., oxides formed by steam oxidation followed by nitric oxide (NO) or nitrous oxide (N2O) anneal or plasma nitridation. Further, the invention is useful for forming bottom oxides for oxide-nitride-oxide (ONO) stacks for capacitor applications or gate applications for FLASH memory devices. In the latter instance, the electrical properties of the ONO stacks can be further improved by using a sequential ammonia/nitrous oxide (NH /N2O) two-step anneal of the nitride layer and a N2O anneal of the top oxide layer deposited by CVD.
Referring to FIGS. 1 A and IB, a side by side flow chart comparison of the method steps required by previous dry/wet oxidation processes versus the preferred wet only process used in the instant invention are shown . As illustrated in FIG. IB, in the instant invention, a wafer is loaded into the chamber, ramped to an elevated temperature (circa 900°C) in the presence of steam, and then cooled and removed from the reactor. The entire SiO2 formation is in the presence of steam. In contrast, in the prior art method shown in FIG. 1 A, the wafer is ramped in the presence N2/O2 to an elevated temperature, followed by the introduction of steam, and then cooled and removed from the reactor.
The silicon wafers are typically processed through a dilute hydrogen fluoride (HF) bath to remove the native oxide present on the surface of the wafers. This type of pre- treatment is common in the manufacture of semiconductor devices and well known to those skilled in the art.
The silicon wafers are placed into a reaction chamber using automation techniques commonly found in semiconductor processing equipment. The process chamber can have any configuration known in the art to provide a means for supporting the wafer, heating the wafer, and exposing the wafer to various gasses in a controlled manner. As such systems are well known, they are not described further herein.
The heating of the silicon wafers can be accomplished by any means known in the art.
Illustrative heating methods include a resistively heated stage, a lamp heating mechanism, a radiant heating mechanism that employs resistively heated coils such as those found in a furnace, and the like. In one embodiment of the present invention the process chamber is elevated to a temperature within the range of about 500°C to 1300°C at a ramp rate of about
10°C/sec to 300°C/sec to carry out steam oxidation. Preferably, the chamber is elevated to a temperature within the range of about 700°C to 1100°C at a ramp rate of about 30°C/sec to
200°C/sec. To convey steam to oxidize the wafer, a gas distribution system is typically used and can be any gas distribution system known in the art. Illustrative gas distribution systems include a showerhead design, a gas ring design, a gas injector design and the like. According to the present invention, the gas flow rate is typically in the range of 50 seem to 30,000 seem for a time period of about 0.1 sec to 3.6 sec. Preferably, the gas flow rate is in the range of 100 seem to 20,000 seem for a time period of about 0.5 sec to 1.0 sec.
The silicon wafer support can be any support known in the art. Illustrative supports include a plate design, a ring design, a pin design and the like.
To better illustrate the invention and the benefits therein, namely the improved electrical characteristics obtained and the higher throughput achieved compared to conventions dry/wet oxidation processes, the following illustrative example is provided. Example 1
Using a prior art dry/wet oxidation method such as that depicted in FIG. 1A, silicon wafers were ramped to 900°C while flowing a mixture of nitrogen and oxygen. The concentration of oxygen in such processes can vary from 0% (pure nitrogen) to 100% (pure oxygen). Typical flow rates are in the range of 0 slpm to 20 slpm. Steam was then introduced for a period of time to grow a SiO2 film of desired thickness (in this example 30 A). The wafers were then either annealed within the same chamber to further optimize the film properties or cooled down and removed from the chamber. Using the wet oxidation method of the present invention, the temperature of the silicon wafers was ramped to 900°C while steam was introduced from the outset of temperature ramping and directly into the chamber. The temperature ramp and stabilization of the silicon wafers did not occur in an atmosphere of nitrogen and oxygen as practiced in the prior art. After the appropriate amount of time elapsed to grow a SiO2 film of target thickness (in this example 30 A) the flow of steam was stopped. The wafers were then either annealed within the same chamber to further optimize the film properties, or the wafer is cooled down and removed from the chamber.
The electrical properties of the silicon oxide films obtained by these methods were then evaluated using techniques known by those skilled in the art. For example, data was collected using a mercury probe which is one common technique. The improvement in the oxide electrical properties was determined by measuring the leakage current density (Jg) in units of amps per square centimeter as a function of voltage (Vgs) in units of volts. The particular region of interest is for voltages around -1 volt. The goal is to minimize the leakage current density. FIG. 2 is a plot of Jg vs Vgs for the prior art method for several different flows of dry oxygen (from 0 slpm to 20 slpm) during the process of ramping and stabilizing the temperature before the introduction of the steam. It can be seen that the value of Jg is not sensitive to the flow of oxygen during this step.
FIG. 3 shows the benefits of the present invention by plotting Jg vs Vgs for both the prior art method (with a nitrogen flow during the temperature ramp step) and the method of the present invention (which introduces steam during the temperature ramp step). The leakage current density for the present invention is significantly lower than the prior art in the ' region of interest around -1 volt indicating improved electrical properties of the film.
FIG. 4 also shows the benefits of the present invention by providing Weibull plots for the leakage current density for two versions of prior art methods where the wafer is treated with either oxygen or nitrogen during the temperature ramp and stabilization step as well as the present invention where the steam is introduced at the beginning of this step. The present invention clearly shows lower values of Jg, a desirable result. The examples cited here used a film thickness of 30 A and a growth temperature of 900°C. It will be clear to those skilled in the art that these are merely illustrative and SiO2 layers of any thickness can be generated using any temperature commonly used to grow SiO2 films used in semiconductor device manufacture. The preceding description is illustrative rather than limiting and is intended to provide a written description of the inventions sufficient to enable one of ordinary skill in the art to practice the full scope and any best mode of the inventions to which patent rights are claimed. Other embodiments and modifications may be readily apparent to those skilled in the art. All such embodiments and modifications should be considered part of the inventions if they fall within the scope of the appended claims and any equivalents thereto.
Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims

What is claimed:
1. A method of oxidizing a semiconductor wafer characterized in that steam oxidation is initiated without first stabilizing the wafer in dry oxygen.
2. The method of claim 1, where steam is introduced during heating to initiate steam oxidation and oxidants are employed with the steam.
3. The method of claim 2 where the other oxidants are comprised of any one of, or a mixture of any of: atomic oxygen (O), oxygen gas (O2), ozone (O3), nitrous oxide (N2O) and nitric oxide (NO).
4. The method of claim 1 further comprising the following steps: raising the temperature of the wafer in the presence of steam in a process chamber; and cooling the wafer.
5. The method of claim 1 wherein the steam oxidation is carried out at a temperature in the range of about 500°C to 1300°C.
6. The method of claim 4 wherein the temperature is raised at a ramp rate in the range of about 10°C/sec to 300°C/sec.
7. A method of oxidizing the surface of a semiconductor wafer in a process chamber, comprising the steps of: ramping the temperature of the wafer to an oxidizing temperature while conveying steam to the wafer, wherein the oxidizing temperature is in the range of about 500°C to 1300°C.
8. The method of claim 7 wherein the method is carried out in a single wafer chamber.
9. The method of claim 7 wherein the method is carried out iri a rapid thermal processing (RTP) chamber.
10. The method of claim 7 further comprising oxidizing the surface of the semiconductor wafer to form a dielectric layer thereon.
PCT/US2003/022059 2002-07-19 2003-07-16 Thin dielectric formation by steam oxidation WO2004010465A2 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037273A (en) * 1997-07-11 2000-03-14 Applied Materials, Inc. Method and apparatus for insitu vapor generation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037273A (en) * 1997-07-11 2000-03-14 Applied Materials, Inc. Method and apparatus for insitu vapor generation

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