CN1334696A - 电子电路组件 - Google Patents
电子电路组件 Download PDFInfo
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Abstract
一种适合于小型化的平面安装型电子电路组件。在氧化铝基板1上以薄膜形式形成包括电容器C1~C7和电阻R1~R3以及电感元件L1~L3的电路元件和与这些电路元件相连接的导电图形P,把二极管D1和晶体管Tr1的半导体裸芯片与导电图形P的连接区进行引线接合,并且在氧化铝基板1的侧面上设置与导电图形P的接地电极和输入输出电极相连接的端面电极3。
Description
本发明涉及平面安装型的电子电路组件。
一般,这种平面安装型的电子电路组件是在设在基板上的导电图形的焊区上分别焊接电阻或电容器等芯片零件和晶体管等半导体零件,用屏蔽外壳覆盖这些电路零件而构成的。当在基板的侧面设置端面电极并把电子电路组件平面安装到母基板上时,端面电极被焊接到母基板的焊区上。通常,这样的基板通过沿着方格状的分割线对大幅基板进行细分割而得到,但此时,在大幅基板上穿设多个通孔,在各个通孔内形成作为端面电极的材料的镀层,然后,如果沿横切通孔的中心的分割线进行细分割,就能在所分割的各个基板的侧面上形成端面电极。
近年来,芯片零件和半导体零件等电路零件小型化的技术显著进步,如外形尺寸为0.6×0.3mm的超小型芯片电阻和芯片电容器已实用化。因此,在上述现有的电子电路组件中,如果使用这种超小型的电路零件,在缩窄该零件间距的状态下把这些电路零件安装到基板上,就能使电子电路组件小型化到某种程度。但是,在芯片零件和半导体元件等电路零件的小型化上是有限度的,而且,当多个电路零件安装到基板上时,各电路零件的焊接部分必须不能短路,因此,缩窄零件间的间距是有限度的,它们成为妨碍电子电路组件进一步小型化的主要因素。而且,由于从通孔形成端面电极,基板上的有限的安装空间因端面电极而变窄,这点也妨碍了电子电路组件的小型化。
鉴于这种现有技术的情况,本发明的目的是提供适合于小型化的平面安装型的电子电路组件。
为了实现上述目的,在本发明的电子电路组件中,在氧化铝基板上以薄膜形式形成包括电容器和电阻以及电感元件的电路元件和与这些电路元件相连接的导电图形,在上述氧化铝基板上搭载半导体裸芯片,同时,把该半导体裸芯片与上述导电图形进行引线接合,并且,在上述氧化铝基板的侧面上设置与上述导电图形相连接的端面电极。
并且,在上述氧化铝基板的侧面上用低温烧结材料以厚膜形式形成与上述导电图形相连接的端面电极。
根据这样的构成,使用薄膜技术高精度地形成包括电容器和电阻以及电感元件的电路元件,而且,半导体元件与裸芯片引线接合,因此,能够在氧化铝基板上高密度地安装所需要的电路零件,而实现适合小型化的平面安装型的电子电路组件。
在上述构成中,在以薄膜形式所形成的电容器和电感元件的表面上最好设置Cu层,这样,能够提高谐振电路的Q。
而且,由于用低温烧结材料以厚膜形式形成端面电极,就能够空间效率高地形成所希望的厚膜的端面电极,同时,能够防止端面电极烧结时烧损以薄膜形式所形成的电路元件。
在上述构成中,最好在以厚膜形式所形成的端面电极上设置Au镀层,这样,当把端面电极焊接到母基板的焊区上时,能够防止低温烧结材料的Ag析出到焊锡中的吃银现象。
而且,在上述构成中,端面电极最好以厚膜形式仅形成在氧化铝基板的相对的两边上,这样,在从大幅基板得到多个氧化铝基板联结成长方形的分割片之后,对于该分割片的各个氧化铝基板,可以同时以厚膜形式形成端面电极,适合于大量生产。
而且,在本发明的电子电路组件中,安装有在长方形平板状的氧化铝基板上以薄膜形式形成包括电容器和电阻以及电感元件的电路元件;在上述氧化铝基板上所引线接合的半导体裸芯片,在上述氧化铝基板相对的两个边的各自的拐角部上设置接地电极,同时,在远离上述拐角部的位置上设置输入电极和输出电极。
根据这样的构成,由于在氧化铝基板相对的两个边的各自的拐角部上设置接地电极,同时,在远离上述拐角部的位置上设置输入电极和输出电极,因此,即使在从大幅基板得到多个氧化铝基板联结成长方形的分割片的半成品的状态下进行各种调整/检查,也能通过接地电极解除对相邻的氧化铝基板上的电路的不良影响。
在上述构成中,最好在氧化铝基板上安装屏蔽外壳以便于覆盖电路元件和半导体裸芯片,把该屏蔽外壳焊接到接地电极上,这样,就能提高屏蔽效果。
在氧化铝基板上以薄膜形式形成包括电容器和电阻以及电感元件的电路元件和与这些电路元件相连接的导电图形,把在该氧化铝基板上搭载的半导体裸芯片与导电图形进行引线接合,同时,在氧化铝基板的侧面用低温烧结材料以厚膜形式形成与导电图形相连接的端面电极,因此,能在氧化铝基板上高密度地安装所需要的电路构成元件,而谋求电子电路组件的小型化。而且,由于用低温烧结材料以厚膜形式形成端面电极,就能够空间效率高地形成所希望的厚膜的端面电极,同时,能够防止端面电极3烧结时烧损以薄膜形式所形成的电路元件。
而且,由于在氧化铝基板的相对的两边的各个拐角部设置接地电极(GND),在远离这些拐角部的位置上设置输入电极和输出电极,因此,不仅能在氧化铝基板上高密度地安装所需要的电路构成元件,而谋求电子电路组件的小型化,而且,即使在从大幅基板得到多个氧化铝基板联结成长方形的分割片的半成品的状态下进行各种调整/检查的情况下,也能通过接地电极解除对相邻的氧化铝基板上的电路的不良影响。
下面参照附图来对本发明的实施例进行说明。
图1是本发明实施例所涉及的电子电路组件的透视图;
图2是表示电路构成布局的氧化铝基板的平面图;
图3是氧化铝基板的内表面图;
图4是电路构成的示意图;
图5是表示端面电极的透视图;
图6是端面电极的断面图;
图7(a)和图7(b)表示半导体裸芯片与连接区的关系的示意图;
图8(a)~图8(j)表示电子电路组件的制造工序的示意图;
图9为另一个电路构成的示意图;
图10表示另一个电路构成布局的氧化铝基板的平面图。
本实施例是向频率调谐型提升放大器的应用例,该频率调谐型提升放大器,为了提高便携型电视机的接收性能(特别是接收灵敏度和抗干扰特性),而与未图示的超高频(UHF)调谐器相组合而使用,具有这样的功能:选择希望频率的电视(TV)信号,同时,放大选择的电视信号并输入到超高频调谐器。
图1表示了所涉及的频率调谐型提升放大器(电子电路组件)的外观,如该图所示,该频率调谐型提升放大器由搭载后述的电路构成元件的氧化铝基板1和安装在该氧化铝基板1上的屏蔽外壳2所构成,由焊接在未图示的母基板上的平面安装零件形成。氧化铝基板1形成为长方形平板状,通过把大幅基板切断成长方形的分割片后,进一步把该分割片进行细分割而得到氧化铝基板1。屏蔽外壳2是把金属板弯曲加工成箱形而得到的,氧化铝基板1上的电路构成元件由该屏蔽外壳2覆盖。
如图2所示,在氧化铝基板1的表面上设置有电路构成元件和与它们连接的导电图形。如图3所示,在氧化铝基板1的内表面上设置有作为背面电极的导电图形。本实施例所涉及的频率调谐型提升放大器为了进行电视信号的选择和放大而具有调谐电路和放大电路,成为如图4所示的电路构成,对图2所示的各电路构成元件赋予与图4的电路图相对应的标号。但是,图4仅表示了电路构成的一个例子,本发明可适用于具有除此之外的电路构成的电子电路组件。
如图4所示,频率调谐型提升放大器具有:作为调谐电路和放大电路的电路构成元件的电容器C1~C7、电阻R1~R3、电感元件L1~L3、二极管D1、晶体管Tr1、导电路径S1,S2等,这些电路构成元件和与其连接的导电图形设置在氧化铝基板1的表面上。该导电图形使用溅射例如Cr和Cu等的薄膜技术而形成,在图2中,赋予标号P,而通过阴影线来表示。
下面对频率调谐型提升放大器的电路构成进行简单说明,为了选择和放大希望频率的电视信号,由以下结构构成:由电感元件L2,L3和电容器C3,C4以及二极管D1组成的调谐电路;由晶体管Tr1及其周边电路元件(电阻R1~R3,电容器C6)和不平衡/平衡变换元件T组成的放大电路。多个频率的电视信号经过电容器C1被输入调谐电路。调谐电路的调谐频率(谐振频率)通过加在二极管D1的负极上的电压(Vct1)的控制而变化,因此,通过与希望的电视信号的频率相一致,来选择出希望的电视信号,经过电容器C5而输入到放大电路的晶体管Tr1的基极。在晶体管Tr1的基极中,偏置电压施加于基极偏置分压电阻R1,R2上,晶体管Tr1的集电极电流(≈发射极电流)通过发射极电阻R3的电阻值来设定。由晶体管Tr1所放大的电视信号从集电极被输出,在集电极上设置不平衡/平衡变换元件T。该不平衡/平衡变换元件T由相互结合的一对导电路径S1,S2组成的电感元件所构成,从导电路径S2的两端输出平衡的电视信号,输入到上述超高频调谐器。
如图2所示,在氧化铝基板1的端部形成接地电极(GND)和输入电极(Vcc,Vct1,RFin)以及输出电极(RFout),它们由导电图形P的一部分所构成。接地电极和输入电极以及输出电极仅形成在长方形的氧化铝基板1相对的两个长边上,而不形成在其外的两个相对的短边上。即,在氧化铝基板1的一方的长边上的两个拐角部形成接地电极(GND),在这些接地电极(GND)之间形成Vcc电极和Rin电极以及Vct1电极。而且,在氧化铝基板1的另一方的长边上的两个拐角部及其附近的三处形成接地电极(GND),在这些接地电极(GND)之间形成两个RFout电极。而且,如后所述,氧化铝基板1的两个长边对应于把大幅基板切断成长方形的分割片时的分割线,氧化铝基板1的两个短边对应于把该分割片进一步细分割时的分割线。
另一方面,如图3所示,设在氧化铝基板1的内表面的导电图形P1(背面电极)与各个接地电极(GND)和输入电极(Vcc,Vct1,RFin)以及输出电极(RFout)相对,如图5和图6所示,两者通过端面电极3而导通。该端面电极3是在Ag厚膜层上依次层叠Ni基底镀层和Au镀层,最下层的Ag厚膜层以厚膜形式形成不包括玻璃成份的Ag浆料之后,以200℃烧结其的低温烧结材料制成。而且,中间层的Ni基底镀层容易附着Au镀层,最上层的Au镀层是为了防止当把端面电极3焊接到未图示的母基板的焊接区上时最下层的Ag析出到焊锡中。而且,在屏蔽外壳2安装到氧化铝基板1上的电子电路组件的成品中,弯折形成在屏蔽外壳2的侧面的脚片2a焊接在与接地电极(GND)导通的端面电极3上,屏蔽外壳2成为在氧化铝基板1的四个角上接地的状态。
在上述的各个电路构成元件中,电容器C1~C7薄膜这样形成:在下部电极上通过SiO2等电介体膜层叠上部电极,使用溅射等方式来形成这些薄膜。在上部电极的表面上设有Cu层,通过该Cu层来提高谐振电路的Q。电容器C1~C7的下部电极和上部电极与导电图形P相连接,如图2所示,在电容器C7与Vcc电极间的导电图形P、电容器C7与RFout电极间的导电图形P、电容器C2与Vct1电极间的导电图形P上分别设置放电用的接近部(气隙)G。该接近部G由分别设置在相对并排设置的导电图形P上的一对突出部所构成,两个突出部的尖端相互以预定的间隙相对。在此情况下,由于导电图形P和接地电极(GND)的尺寸精度可以通过薄膜技术提高,因此,能够缩窄接近部G的间隙尺寸,能够低电压下放电。而且,在各个电容器C1~C7中,电容器C1和C3~C5形成单纯的长方形,但是,电容器C2和C7形成为把两个以上的长方形进行组合的异形。即,电容器C2是从一个矩形的一边突出两个矩形的凹形,电容器C7为三个矩形在长边方向上错开的连续形状。这些电容器C2和C7是需要比较大的电容值的接地电容器,当使接地电容器C2和C7为这样的异形时,就能有效利用氧化铝基板1上的有限空间,而高密度地安装所希望的电容值的电容器。
而且,在各个电容器C1~C7中,电容器C6由大小不同的两个接地电容器所构成,两者通过相互分离的一对导电图形P并联连接。即,如图2所示,两个接地电容器C6的各自的一方的电极部与同接地电极(GND)连接的接地用导电图形P相连接,但是,两个接地电容器C6的各自的另一方的电极部通过相互分离的两个导电图形P而与晶体管T r1的连接区SL相连接。如图4所示,电容器C6设在晶体管Tr1的发射极与接地之间,由于上述连接区SL是晶体管Tr1的发射极电极进行引线接合的位置,则电容器C6的电容值通过经过导电图形P并联连接的两个接地电容器来进行设定。因此,从晶体管Tr1的发射极电极经过电容器C6而到达接地的导电图形P的全体的电感减少了,而提高了由接地电容器C6所产生的连接区SL的接地效果,而且,由于各个接地电容器C6和各个导电图形P所产生的寄生谐振频率变高,通过把该频率设定到晶体管Tr1的工作点频率以上,就能消除寄生振动。
电阻R1~R3使用溅射等薄膜技术来形成例如TaSiO2等电阻膜,根据需要在其表面上设置SiO2等电介体膜。如图2所示,三个电阻R1~R3中,电阻R1和R2在氧化铝基板1上的相互接近位置上并排设置以薄膜形式形成,剩下的电阻R3以薄膜形式形成在远离电阻R1和R2的位置上。这样,由于使电阻R1和R2薄膜形成在接近的位置上,即使各个电阻R1和R2的电阻值相对于希望值产生偏差,也能使电阻R1和R2全体的偏差比率成为相同的。如图4所示,电阻R1和R2是晶体管Tr1的基极偏置用分压电阻,R1/(R1+R2)×Vcc的电压施加在晶体管Tr1的基极上。在此,由于作为基极偏置用分压电阻的电阻R1和R2全体的偏差的比率如上述那样始终是相同的,就不需要与这些电阻R1和R2相对应的电阻值的平衡调整。另一方面,电阻R3是晶体管Tr1的发射极电阻,电流从Vcc电极流到晶体管Tr1的集电极和发射极,接着通过电阻R3接地。在此,在各电阻R1~R3中,由于由作为发射极电阻的电阻R3所产生的晶体管Tr1的对放大率的作用最大,则仅调整电阻R3来进行输出调整,以使电流值成为恒定的。
而且,如图9所示,当在晶体管Tr1上串联连接另一个晶体管Tr2的电路构成的情况下,通过在氧化铝基板1上的相互接近的位置上形成作为两个晶体管Tr1,Tr2的基极偏置用分压电阻的电阻R1,R2,R4薄膜,就不需要与这些电阻R1,R2,R4相对应的电阻值的平衡调整。因此,即使在此情况下,通过仅调整作为发射极电阻的电阻R3,就能设定两个晶体管Tr1,Tr2。
而且,使用溅射Cr和Cu等的薄膜技术来形成电感元件L1~L3和导电路径S1,S2,并与导电图形P相连接。在各个电感元件L1~L3的表面上设置Cu层,通过该Cu层来提高谐振电路的Q。电感元件L1和L2都形成为方形的旋涡状,各自的一端与Vct1电极和接地用的导电图形P引线接合。电感元件L2是设定大致的谐振频率的谐振频率设定用的,电感元件L3连接在电感元件L2的另一端上。电感元件L3是用于调整谐振频率的调整用导电图形,如图2的虚线所示,通过调整减小电感元件L3,增加电感元件L2的匝数来调整谐振频率。在此情况下,如果调整后的电感元件L3的导体宽度变为与谐振频率设定用的电感元件L2的导体宽度相同,电感元件L2和电感元件L3的特性阻抗不变。
如上所述,不平衡/平衡变换元件T通过由相互结合的一对导电路径S1,S2组成的电感元件所构成,这些导电路径S1,S2薄膜形成在氧化铝基板1上。这些导电路径S1,S2在氧化铝基板1上形成为旋涡状,以便于通过预定的间隙相对,一方的导电路径S1的两端与晶体管Tr1的集电极电极和连接在电容器C7上的导电图形P相连接,另一方的导电路径S2的两端连接在一对RFout电极上。在此情况下,由于薄膜形成的导电路径S1,S2的尺寸精度较高,所以能够通过缩窄两个导电路径S1,S2间的间隙确保所希望的耦合度,能够在氧化铝基板1上的有限的空间内设置小型的不平衡/平衡变换元件T。而且,如图10所示,可以在氧化铝基板1上以锯齿状形成通过预定间隙相对的一对导电路径S1,S2。
而且,二极管D1和晶体管Tr1是这样形式的:在以薄膜形式形成在氧化铝基板1上的导电图形P的连接区中搭载半导体裸芯片,把该半导体裸芯片与导电图形P进行引线接合。即,如图2所示,二极管D1的半导体裸芯片为方形形状,设在其下表面的一方的电极用膏状焊锡和导电浆料等导电性粘接剂而固定在连接区中,设在半导体裸芯片的上表面的另一方的电极与导电图形P的预定部位进行引线接合。而且,晶体管Tr1的半导体裸芯片也成为方形形状,设在其下表面的集电极电极使用导电性粘接剂固定在连接区中,基极电极和发射极电极被引线接合在导电图形P的预定部位上。与上述的端面电极3相同,在这些连接区上也依次层叠Ni基底镀层和Au镀层。在此,如图7(a)或图7(b)所示,相对于半导体裸芯片4的下表面面积,连接区5的面积形成得较小,通过采用这样的构成,由于在半导体裸芯片4的下方确保了导电性粘接剂的蓄积部,就能预先防止导电性粘接剂从半导体裸芯片4的外形溢出而与周围的导电图形P发生短路的事故。而且,在连接区5的内部设有开口5a,由此,剩余的导电性粘接剂存留在开口5a中,因此,能够更确实地防止导电性粘接剂的溢出。
下面主要使用图8(a)~图8(j)来对上述那样构成的电子电路组件的制造工序进行说明。
首先,如图8(a)所示,在氧化铝基板1的整个表面上溅射TaSiO2等,然后,把其腐蚀成所希望的形状,而形成电阻膜6,由此,构成相当于电阻R1~R3的部分。接着,如图8(b)所示,从电阻膜6上溅射Cr和Cu等,把其腐蚀成所希望的形状,而形成下部电极7,然后,如图8(c)所示,从下部电极7上溅射SiO2等,把其腐蚀成所希望的形状,而形成电介体膜8。接着,如图8(d)所示,从电介体膜8上溅射Cr和Cu等,把其腐蚀成所希望的形状,而形成上部电极9。其结果,通过下部电极7或者上部电极9来构成相当于导电图形P和电感元件L1~L3以及导电路径S1,S2的部分,通过下部电极7和电介体膜8以及上部电极9的层叠体,来构成相当于电容器C1~C7的部分。接着,用镀或者薄膜技术在相当于电感元件L1~L3和导电路径S1,S2以及电容器C1~C7的部分的表面上形成Cu层,然后,如图8(e)所示,在除导电图形P的部分上形成保护膜10。接着,如图8(f)所示,在氧化铝基板1的整个内表面上溅射Cr和Cu等,把其腐蚀成所希望的形状,而形成背面电极11,由此,构成相当于内表面上的导电图形P1的部分。
以上说明的图8(a)~图8(f)的工序是对由刻有纵横方格状延伸的分割沟的氧化铝材料制成的大幅基板进行的,以下说明的图8(g)~图8(j)的工序是对通过沿着一个方向的分割沟切断该大幅基板而得到的长方形的分割片进行的。
即,在把大幅基板切断成长方形的分割片之后,如图8(g)所示,在作为该分割片的切断面的氧化铝基板1的两端面上以厚膜的形式形成Ag层12,用Ag层12来导通设在氧化铝基板1的内外两面上的导电图形P,P1的接地电极(GND)和输入电极(Vcc,Vct1,RFin)以及输出电极(RFout)。该Ag层12相当于上述的端面电极3的Ag厚膜层,是由不包括玻璃成份的Ag膏组成的低温烧结材料。而且,能够对一个长方形分割片进行相应的Ag层12的厚膜形成工序,但是,如果使多个分割片存在若干间隙而重合的状态,就能对多个分割片同时以厚膜形式形成Ag层12,适合于大量生产。接着,在Ag层12和半导体裸芯片所搭载的连接区的各个表面上依次镀上Ni基底层和Au层,然后,如图8(h)所示,在各连接区上使用膏状焊锡和导电浆料等导电性粘接剂来固定二极管D1和晶体管Tr1的半导体裸芯片。在此情况下,如上述那样,由于相对于半导体裸芯片的下表面面积,连接区的面积形成得较小,因此,能够防止导电性粘接剂从半导体裸芯片溢出,导电性粘接剂不会与半导体裸芯片的周围的导电图形P产生不希望的短路。接着,如图8(i)所示,把各个半导体裸芯片与导电图形P的预定部位进行引线接合,然后,如图8(j)所示,调整作为发射极电阻的电阻R3,来进行输出调整,同时,调整作为调整用导电图形的电感元件L3,来调整谐振频率。在此情况下,谐振频率的调整在分割成各个氧化铝基板1之前的长方形分割片的状态下进行,由于在各个氧化铝基板1的拐角部设置接地电极(GND),接地电极(GND)必然位于设在相邻的氧化铝基板1上的输入电极(Vcc,Vct1,RFin)以及输出电极(RFout)之间,谐振频率的调整不会对相邻的氧化铝基板1的电路产生不良影响。
接着,在长方形分割片的各个氧化铝基板1上安装屏蔽外壳2,把该屏蔽外壳2的脚片2a焊接到与接地电极(GND)导通的端面电极3上,然后,沿着另一方的分割沟把分割片细分割成各个氧化铝基板1,就能得到图1所示的电子电路组件。
根据这样构成的上述实施例所涉及的电子电路组件,在氧化铝基板1上以薄膜形式形成电容器C1~C7、电阻R1~R3、电感元件L1~L3、导电路径S1,S2等电路元件和与这些电路元件相连接的导电图形P,同时,在该氧化铝基板1上对二极管D1和晶体管Tr1的半导体裸芯片进行引线接合,并且,由于在氧化铝基板1的侧面上设置与导电图形的接地电极和输出输入电极相连接的端面电极3,因此,使用薄膜技术和半导体元件的引线接合就能在氧化铝基板1上高密度地安装所需要的电路构成元件,能够实现适合于小型化的平面安装型的电子电路组件。而且,由于在以薄膜形式所形成的电容器C1~C7和电感元件L1~L3以及导电路径S1,S2的表面上设置Cu层,能够提高谐振电路的Q。
而且,由于用低温烧结材料以厚膜形式形成端面电极3,就能够空间效率高地形成所希望的厚膜的端面电极3,同时,能够防止端面电极3烧结时烧损以薄膜形式所形成的电路元件。而且,由于在以厚膜形式所形成的端面电极3上设置Au镀层,当把端面电极3焊接到母基板的焊区上时,能够防止低温烧结材料的Ag析出到焊锡中的吃银现象。并且,由于仅在氧化铝基板的相对的两边上形成以厚膜形式形成端面电极3,因此,在从大幅基板得到长方形的分割片之后,对于该分割片的各个氧化铝基板,就能够同时以厚膜形式形成端面电极3,从而适合于大量生产。
而且,在氧化铝基板1的相对的两边的各个拐角部设置接地电极(GND),同时,在这些接地电极的内侧设置输入电极(Vcc,Vct1,RFin)和输出电极(RFout),因此,即使在从大幅基板得到长方形的分割片的半成品的状态下进行各种调整/检查的情况下,这些调整也不会对在分割片上相邻的其它氧化铝基板的电路产生不良影响,而能够简单地进行各种调整。而且,由于在氧化铝基板1的四个拐角的接地电极上焊接屏蔽外壳2的脚片2a,就能实现屏蔽效果高的电子电路组件。
Claims (8)
1.一种电子电路组件,其特征在于,在氧化铝基板上以薄膜形式形成包括电容器和电阻以及电感元件的电路元件和与这些电路元件相连接的导电图形,在上述氧化铝基板上引线接合半导体裸芯片,同时,把该半导体裸芯片与上述导电图形进行引线接合,并且,在上述氧化铝基板的侧面上设置与上述导电图形相连接的端面电极。
2.根据权利要求1所述的电子电路组件,其特征在于,在上述电路元件中,在上述电容器和上述电感元件的表面上设置Cu层。
3.根据权利要求1所述的电子电路组件,其特征在于,用低温烧结材料以厚膜形式形成上述端面电极。
4.根据权利要求3所述的电子电路组件,其特征在于,在上述端面电极上设置Au镀层。
5.根据权利要求3所述的电子电路组件,其特征在于,仅在上述氧化铝基板相对的两边上以厚膜形式形成上述端面电极。
6.根据权利要求4所述的电子电路组件,其特征在于,仅在上述氧化铝基板的相对的两边上以厚膜形式形成上述端面电极。
7.一种电子电路组件,其特征在于,包括:在长方形平板状的氧化铝基板上以薄膜形式形成包括电容器和电阻以及电感元件的电路元件;在上述氧化铝基板上所引线接合的半导体裸芯片,在上述氧化铝基板的相对的两个边的各自的拐角部上设置接地电极,同时,在远离上述拐角部的位置上设置输入电极和输出电极。
8.根据权利要求7所述的电子电路组件,其特征在于,在上述氧化铝基板上安装屏蔽外壳以便于覆盖上述电路元件和上述半导体裸芯片,把该屏蔽外壳焊接到上述接地电极上。
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JP2000160247A JP3244676B2 (ja) | 2000-05-30 | 2000-05-30 | 電子回路ユニット |
JP2000160239A JP2001339242A (ja) | 2000-05-30 | 2000-05-30 | 電子回路ユニット |
JP2000160303A JP3246907B2 (ja) | 2000-05-30 | 2000-05-30 | 電子回路ユニット |
JP160247/2000 | 2000-05-30 | ||
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EP (1) | EP1160869A3 (zh) |
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CN101026154B (zh) * | 2006-02-17 | 2010-05-26 | Tdk株式会社 | 薄膜器件 |
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EP1160869A2 (en) | 2001-12-05 |
US6700177B2 (en) | 2004-03-02 |
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KR100450354B1 (ko) | 2004-09-30 |
KR20010109153A (ko) | 2001-12-08 |
US20010048150A1 (en) | 2001-12-06 |
TW498602B (en) | 2002-08-11 |
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