CN1320695C - 具有嵌入天线的无引线芯片载体的构造和制造方法 - Google Patents

具有嵌入天线的无引线芯片载体的构造和制造方法 Download PDF

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Publication number
CN1320695C
CN1320695C CNB028149823A CN02814982A CN1320695C CN 1320695 C CN1320695 C CN 1320695C CN B028149823 A CNB028149823 A CN B028149823A CN 02814982 A CN02814982 A CN 02814982A CN 1320695 C CN1320695 C CN 1320695C
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substrate
path
connection welding
signal connection
semiconductor chip
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CN1543689A (zh
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R·科西奥里
M·米加海德
H·S·哈森
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Skyworks Solutions Inc
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Skyworks Solutions Inc
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Abstract

一种可以在顶面上接受半导体小片的基片。天线图案制作在基片的底面上。天线偶合于通路，并通过该通路到基片信号连接焊点和半导体小片信号连接焊点而可以访问。在一个实施方案中，在基片中至少有一通路。该至少一个通路在半导体小片的信号连接焊点和印刷电路板之间提供电气连接。至少一个通路在基片连接焊点和印刷电路板之间提供电气连接。至少一个通路也在半导体小片的信号连接焊点和电气连接到印刷电路板的焊接区之间提供电气连接。

Description

具有嵌入天线的无引线芯片载体的构造和制造方法
                            发明背景
本申请为题名“无引线芯片载体的设计和构造”(序列号No.09/713,834，2000年11月15日提交，转让予本申请的受让人)的待批专利申请的部分继续申请，要求该申请的申请日权益，原文全部综合在此作为参考。
1.发明领域
本发明一般属于半导体芯片封装领域。更具体地说，本发明属于无引线芯片载体的设计和构造领域。
2.背景技术
半导体制造工业不断地面临着更小和更复杂化小片的要求。这些更小和更复杂化小片必须在更高的频率下运行。要求更小、更复杂化和更快的器件不但在制造小片本身，而且也在制造各种用于安置和对“芯片外”器件提供电气连接方面的封装、构造或载体方面导致新的挑战。
作为一个例子，要求更高的频率意味着，其中之一就是，“芯片上”“芯片外”的寄生干扰必须减少到最低限度。例如，寄生感应、电容和电阻等这些有害地影响小片和它相关联芯片外部件必须尽量减少。由于RF(“无线电频率”)半导体器件在高频下运行，这些器件(即RF器件)组成器件中特别要求非常低寄生效应的重要类别。
最近，表面安装芯片和芯片载体相对于分立半导体封装而言已经获得欢迎。分立半导体封装典型地具有大量“针脚”，这需要占用相对较大的安装空间(也称作“占地面积”)把分立半导体封装件电气连接在印刷电路板上。此外，关于制造分立半导体封装件成本和时间，和关于在印刷电路板上钻孔所需成本和时间均为附加的理由，即为何诸如表面安装器件和芯片载体等替代方案得到欢迎。
在本行业中曾经作出多种努力企图获得不同的芯片载体设计。日本公开号10313071，出版于1998年11月24日，题名为“电子零件和接线板器件”，其中Minami Masumi为发明者，披露一种半导体器件发出热量的发散构造。该构造在线路板中提供金属封装的通孔，它通过在线路板底部上散热式样传递从裸芯片发出的热量，然后传到散热板上。
日本公开号02058538，出版于1990年2月27日，题名为“安装电子部件的基片”，其中Fujikawa Osamu为发明者，披露一种基片，其中心区域包括夹入在金属镀层顶面和底面之间的8个导热性树脂充填孔。然后在基片金属镀层顶面的中心区域用银浆连接剂固定电子部件以便改进散热性和潮湿抵抗力。
日本公开号09153679，出版于1997年6月10日，题名为“堆置玻璃陶瓷线路板”，其中Miyanishi Kenji为发明者，披露一种包括七层堆置玻璃陶瓷的玻璃陶瓷线路板。该多层堆置玻璃陶瓷线路板还包括多个金或铜通孔，并在覆盖通孔的顶面和底面上具有表面导体。顶部导体的功能为IC(集成电路)芯片的热汇集点。
日本公开号10335521，出版于1998年12月18日，题名为“半导体器件”，其中Yoshida Kazuo为发明者，披露一种形成在基底上的热通路，其中有半导体芯片安装在热通路上方。热通路孔的上部以如此方式形成在陶瓷基片上，使其径向地向外时变得较浅。
芯片安装在印刷电路板上的传统芯片载体构造具有不少缺点。例如，传统芯片载体引入太多的寄生效应而仍不能对于小片提供低的对地连接感应和电阻。传统芯片载体也具有非常有限的散热能力和承受由于不良散热而导致伴随的可靠性问题。作为例子，在高频应用中，例如RF应用，单个小片可产生好几瓦的功率。由于半导体小片和芯片载体由不同材料制成，各有不同的热膨胀系数，它们将对于小片所产生的热作出不同的反应。由此产生的热应力可能造成碎裂或是小片从载体分离，而且这样可能导致电气和机械故障。因此成功的散热十分重要而要求新颖的构造和方法。
要求运行在高频下的较小、更复杂和更快的器件，诸如无线通讯器件和蓝牙RF收发器，也已导致对于小型天线增长的需要。这样，无线通讯器件尺寸的减小已经造成对于集成在同一封装壳体(其中半导体小片偶合于天线)内小型天线的需求。如以上所述，运行在高频下的较小和更复杂的半导体小片需要一种构造来支持、安置和电气连接半导体小片到印刷电路板上，而能提供低的寄生效应、有效的散热性和低的接地感应和电阻。
因此，需要一种新颖的和可靠的构造和方法，它能够安置、支持并且电连接半导体小片到嵌入在构造中的天线，而且它能克服单个半导体封装件和传统芯片载体所面临的问题。更具体地说，这里存在一种新颖和可靠构造和方法的需要，它能够在安置、支持和电连接到半导体小片的结构中嵌入天线，而提供低的寄生效应、有效的散热性和低的接地感应和电阻。
                            发明概要
本发明目的是制造一种具有嵌入天线的无引线芯片载体的构造和方法。本发明披露一种可提供半导体小片所产生热量有效散热的构造。本发明还披露一种构造，它包括嵌入天线并且也提供低的寄生效应和对于半导体小片低的地面连接感应和电阻。
在一个实施方案中，本发明包括具有可接受半导体小片的顶面的基片。例如该基片包括诸如聚四氟乙烯材料的有机材料或者FR4基的片状材料。在更深入的例子中，基片还可以包括陶瓷材料。按照本发明的一个方面，在基片的底面上图案制作天线。该天线可以容易地通过连接到一个通路访问，通过该通路到基片信号连接焊点和半导体小片信号连接焊点。
在一个实施方案中，本发明包括至少在基片上一个通路。发明中至少一个通路对于半导体信号连接焊点和印刷电路板之间提供电连接。至少一个通路可包括诸如铜的导电和导热材料。至少一个通路在基片连接焊点和印刷电路板之间提供电气连接。基片连接焊点通过信号连接导线连接到半导体小片的信号连接焊点。至少一个通路也对半导体小片的信号连接焊点和电气连接于印刷电路板上的焊接区提供电气连接。
                       附图简要说明
图1阐明本发明一个实施方案的剖面图。
图2A和2B各自阐明在本发明一个实施方案中示例性通路的顶视和剖面图。
图3阐明本发明一个实施方案在完成“锯割单体化”步骤后的顶视图。
图4阐明本发明一个实施方案在完成“锯割单体化”步骤后的底视图。
图5阐明本发明一个实施方案示例性制造过程的流程图。
图6阐明本发明一个实施方案在完成“锯割单体化”步骤后的底视图。
图7阐明本发明一个实施方案示例性嵌入天线的底视图。
图8阐明本发明一个实施方案示例性嵌入天线的剖面图。
图9阐明本发明实施方案示例性嵌入天线的另一个剖面图。
图10阐明本发明一个实施方案示例性嵌入天线的顶视图。
                         发明的详细描述
本发明目的是一种具有嵌入天线的无引线芯片载体的构造和方法。下列描述属于本发明各种实施方案和实现手段特定信息。本行业熟练人士将认识到本发明可以一种不同于在本申请中特定的讨论的方式实施。此外，为避免使概念模糊本发明对于一些特定的细节未予讨论。在本申请中未予描述的特定细节均在本行业普通熟练人士的知识范畴以内。
在本申请的附图和它们的有关的详细描述仅指本发明实施方案的例子。为保持简洁，其它采用本发明原理的实施方案不再具体在本申请中描述并且也不在附图中阐明。
在图1中的构造100显示按照本发明实施方案代表性构造的剖面图。构造100显示固定于图1中的印刷电路板(“PCB”)150。参照构造100，半导体小片110通过小片附片112固定于小片附片焊点111。应注意，“半导体小片”，诸如半导体小片110，在本申请中也以“芯片”或“半导体芯片”提及。小片附片焊点可以是AUS-5钎焊掩模并且它(即小片附片焊点111)涉及直接处于半导体小片110下的钎焊掩模段。在本申请的以后段落中将更详细地讨论钎焊掩模的形成图案制作。小片附片焊点111的厚度可以是，例如，10.0到30.0微米。小片附片112可以包括银充填的环氧树脂或bismalemide。一般小片附片112可以是导电或者绝缘的热定型连接剂，或者是其综合物。不过在本发明实施方案中，小片附片112是导电和导热的。
钎焊掩模113施加于基片120的顶面118。钎焊掩模113的厚度可以是，例如，10.0到30.0微米。钎焊掩模113可以是AUS-5；不过，钎焊掩模113可以包括其它材料。钎焊掩模115施加于基片120的底面124。钎焊掩模115的厚度可以是，例如，10.0到30.0微米。钎焊掩模115也可以是AUS-5；不过钎焊掩模115可以包括其它材料。支承垫片117制造在基片120的顶面118，并且在一个实施方案中，支承垫片可以是铜质。不过，支承垫片可以包括其它材料。例如，支承垫片117可以是铝、钼、钨或金。应注意，在本发明一个实施方案中，半导体小片110可以直接焊接在支承垫片117上。支承垫片117的制造还将在下文中联系图5予以描述。
基片下连接区域114制造在基片120的顶面118上。在图1中的构造100中，基片下连接区域可以包括镀镍的铜。不过，基片下连接区域114可以是铝、钼、钨或金。基片下连接区域114的制造还将在下文中联系图5予以描述。下连接导线116的第一端连接在半导体小片110的半导体小片接地连接焊点108上。下连接导线116的第二端连接在基片下连接区域114上。下连接导线可以是金或包括其它诸如铝的金属。下连接导线116的直径可以是大约30.0微米或选择其它直径。
基片120可以包括两层有机片材，诸如聚四氟乙烯。不过，基片120可以包括其它有机材料，诸如FR4基的片材。在本发明一个实施方案中，基片可以是陶瓷材料。在图1的构造100中，基片120的厚度122大约为20.0微米；不过，在本发明其它实施方案中基片120厚度可以不同。
继续参看图1，通路128(也认作第一组通路)，和通路126及通路130(也认作第二组通路)均位于基片内部。通路126、通路130和通路128从基片的顶面118延伸到底面124。通路126、通路130和通路128可以包括导热材料。通路126、通路130和通路128可以包括铜，并且实际上，在代表性构造100中，通路126、通路130和通路128用铜充填。不过，通路126、通路130和通路128可以用其它材料充填而并不偏离本发明范围。在本发明另一实施方案中，通路126、通路130和通路128可以不完全用金属充填。一般，通路126、通路130和通路128具有相似构造。如此，通过说明性例子，代表性通路126的构造可以联系图2A和2B更详细地描述，并且具体对于用虚线142包围的区域(这对应于图2B中虚线242包围的区域)。
如图1所示，信号连接导线134的第一端连接在半导体小片110上的半导体小片信号连接焊点104上。信号连接导线134的第二端连接在基片信号连接焊点132上。信号连接导线134可以是金或者包括诸如铝的其它金属。信号连接导线134的直径可以是30.0微米或其它选择的直径。如还在图1中所示，信号连接导线140的第一端连接到在半导体小片110上的半导体小片信号连接焊点106上。信号连接导线140的第二端连接在基片信号连接焊点138上。信号连接导线140可以是金或可以包括其它诸如铝的金属。信号连接导线140的直径可以是30.0微米或其它选择的直径。
在图1中，基片信号连接焊点132制造在基片120的顶面118上。在构造100中，基片信号连接焊点132可以包括镀镍的铜。基片信号连接焊点132还可以包括在镀镍的铜上一层镀金。不过，基片信号连接焊点132可以包括其它材料。例如，基片信号连接焊点132可以是铝、钼、钨或金。基片信号连接焊点132的制造将在以下联系图5描述。在图1的构造100中，基片信号连接焊点132重叠通路130。在本发明另一实施方案中，不是重叠通路130，而是基片信号连接焊点132“邻接”通路130。
相似于基片信号连接焊点132，基片信号连接焊点138制造在基片120的顶面118上。在构造100中，基片信号连接焊点138可以包括镀镍的铜。基片信号连接焊点138包括在镀镍的铜上一层镀金。不过，基片信号连接焊点138可以包括其它材料。例如，基片信号连接焊点138可以是铝、钼、钨或金。基片信号连接焊点138的制造将在以下联系图5描述。在图1的构造100中，基片信号连接焊点138重叠通路126。在本发明另一实施方案中，基片信号连接焊点138邻接通路126。
如图1所示，焊接区144制造在基片120的底面124上。在构造100中，焊接区144可以包括铜；不过，焊接区144可以包括诸如铝、钼、钨或金的其它金属。焊接区144的制造将在以下联系图5描述。焊接区144通过焊料147固定在印刷电路板(“PCB”)150上。在构造100中焊接区144重叠通路126。在本发明另一实施方案中，不是重叠通路126，而是焊接区144邻接通路126。
相似于焊接区144，焊接区146制造在基片120的底面124上。在构造100中，焊接区146可以包括铜；不过，焊接区146可以包括诸如铝、钼、钨或金的其它金属。焊接区146的制造将在以下联系图5描述。在图1的构造100中，焊接区146通过焊料147固定在印刷电路板150上。不过，行业中其他已知的方法也可以用来把焊接区246固定在PCB150上。在构造100中焊接区146重叠通路130。在本发明另一实施方案中，焊接区144邻接通路126。
在图1中还显示，热传播器148制造在基片120的底面124上。在构造100中，热传播器148制造在基片120的底面上。在构造100中，热传播器148可以是铜；不过，热传播器148可以包括诸如铝、钼、钨或金的其它金属。在代表性构造100中，热传播器148通过焊料147固定在印刷电路板150上。不过，本行业中其它已知方法也可以用来固定热传播器148在PCB150上。热传播器148的制造将在以下联系图5详细地描述。
图2A显示在图2B中区域242的顶视图，区域242对应于图1中区域142。具体地说，基片220、通路226和基片信号连接焊点238各自对应于图1中的基片120、通路126和基片信号连接焊点138。图2A也显示通孔262。通孔262不能在图1中沿图2A 1-1线的剖面图中看见。不过，由于图2B为沿图2A中B-B线的剖面图，可以在图2B中看见通孔262。通路226、连接焊点238和通孔262将联系图2B在以下详细地描述。
图2B显示沿图2A中B-B线的区域242的剖面图。不过，在图1中区域242显示沿图2A中1-1-线的剖面图。具体地说，顶面218、基片220、底面224、通路226、基片信号连接焊点238和焊接区244各自对应于图1中的顶面118、基片120、底面124、通路126、基片信号连接焊点138和焊接区144。
在图2B中，焊接区焊点厚度252可以是大约12.7到30.0微米。通路钻孔直径254可以是150.0微米，而连接焊点厚度256可以是大约12.7到30.0微米。通路壁厚度258可以是大约20.0微米。通孔直径260约为110.0微米。应该注意，为阐明方便起见，图2A和2B中各种尺寸未按比例绘制。
通路226的制造从基片220开始。在本发明一个实施方案中，在基片224的顶面218和底面224上覆盖铜层。在基片224的顶面218和底面224上覆盖的铜层的厚度可以是，例如，15.0微米。不过，可以在基片224的顶面218和底面224上覆盖其它金属。例如，在基片224的顶面218和底面224上覆盖的金属层可以是铝、钼、钨或金。其次，穿过基片220在预定位置钻出具有通路钻孔直径254的通路孔。基片220然后镀铜以便在通路孔内部产生铜层(对应于通路壁厚258)。不过，基片220可以镀以其它金属。如此，通路226制成具有如图2A和2B中显示的通路孔262。以上阐明制造通路226的过程也适用于制造在图1中构造100的通路130和通路128。
在图3中构造300阐明按照本发明一个实施方案在完成“锯割单体化”步骤后的代表性构造顶视图，简单地说它包括切割基片120(图1)，使其获得诸如图1中构造100的“单体化”构造，也相应于图3中构造300。锯割单体化步骤是过程中最后一步，该过程将联系图5更详细地描述。如此构造300包括相应于图1中基片120的基片320。不过，相比于图1中的构造100，在构造300中基片连接焊点邻接而不是重叠通路。例如，基片信号连接焊点338显示为邻接而不是重叠通路326。这不同于图1中基片信号连接焊点138，后者显示为重叠而不是邻接通路126。继续讨论构造300，连接导线340的第一端连接在基片信号连接焊点338上。连接导线340的第二端连接在半导体小片310的半导体小片信号连接焊点306上。应该注意，为保持简明起见，在图3中只有通路326、基片信号连接焊点338、连接导线340和半导体小片信号连接焊点306在此特地讨论。
在图3中构造300的形状可以是正方的。例如，在单体化构造300中基片320的边384和边386均为4.0毫米。提及其它例子，其它方形“封装”尺寸可以是5.0毫米×5.0毫米，6.0毫米×6.0毫米，或7.0毫米×7.0毫米。在另一实施方案中，构造300形状可以是矩形。矩形实施方案的“封装尺寸”可以是3.9毫米×4.9毫米。提及其它例子，矩形实施方案的其它“封装尺寸”可以是4.4毫米×6.5毫米或4.4毫米×7.8毫米。
在图4中构造400显示按照本发明一个实施方案在完成“锯割单体化”后，代表性例子的底视图。构造400包括相应于图1中基片120的基片420。不过，与图1中构造100不同，在构造400中焊接区邻接而不是重叠通路。例如，焊接区444显示为邻接而不是重叠通路426。这与图1中焊接区144不同，其中显示为重叠而不是邻接通路126。此外，连接焊接区和通路到热传播器的轨迹，诸如图4中的轨迹414、430、436和442，在图1构造100中未予显示。
现在更详细地讨论图4，图4显示基片420的底面424。焊接区412、428、432、440和444各自邻接通路402、425、434、438和426。轨迹414连接通路402和热传播器448。轨迹436连接通路434和热传播器448。轨迹430连接焊接区428和热传播器448。轨迹442连接焊接区440和热传播器448。因此，通路402、425、434、和438各自被轨迹414、430、436、和442连接到热传播器448。在图4中所示代表性实施方案中，“焊接区节距”445可以是，例如，500.0微米，而“焊接区宽度”446可以是，例如，250.0微米。应该注意，在图4中，只有通路402、425、426、434和438和焊接区412、428、432、440和444在此具体地讨论以保持简要。在另一实施方案中，诸如在图4中的轨迹414、430、436和442的“接地轨迹”根本未使用。诸如图4中的焊接区412、428、432和440将不接地，而诸如图4中热传播器448将用作普通的“信号”焊接区。
参见图5，现在讨论图1中构造100制造过程作为例子。过程在步骤502开始。在步骤504，在一条铜层基片上钻出通路孔。例如，该长条可以是18英寸×24英寸铜层基片板。在图1中基片120对应于铜层基片长条中一段。典型地，在铜层基片长条上组合多个构造100的单元。在装配过程的下一步中，多个组合构造100单元被分割成为个别的单元。在铜层基片中钻出的通路孔直径可以是大约150.0微米。
典型地，采用多重金刚石钻头一次钻出所有通路的孔。在步骤506，通路孔的侧壁在无电的镀槽中镀铜。在背景知识方面，无电镀层涉及一种通过还原性化学镀槽在各种材料上沉积诸如铜、镍、银、金或鈀的方法。无电镀槽产生的结果是，通路提供在铜层基片的顶面和底面之间的电气和导热连接。在一个实施方案中，在完成无电镀层过程后，通路孔直径，例如图2B中通路孔直径260，为大约110.0微米。
在步骤508，通路孔充满着铜。由于对热流提供更大的截面，对通路孔增加额外的铜可增加通路的导热率。另外，对电流的流动提供更大的截面面积可增加通路的导电率。在本实施方案中，通路孔部分地(或几乎完全)充填着铜，而在另一实施方案中，通路孔完全地充满着铜。在本发明一个实施方案中，通路充满着钨。在该实施方案中，充钨通路的强度足够容许直接连接在通路上。
在步骤510，采用掩模在基片的顶面和底面上的金属化镀层上制成导体图案。在本代表性实施方案中，金属化镀层可以是铜。在步骤512，多余的铜被蚀去，结果在基片的顶面和底面造成限定的金属互相连接或者金属轨迹图案，也称作印刷电路。例如，在图4构造400中，在底面424上的金属化镀层上图案包括热传播器448、焊接区412、418、428、432和440以及轨迹414、430、436和442。
在步骤514，在基片的顶面和底面上施加钎焊掩模，由此覆盖在基片上顶面和底面上暴露的铜层图案。钎焊掩模改进用来固定半导体小片到基片顶面上小片附片的连接质量。例如，在图1构造100中，钎焊掩模113改进用来固定半导体小片110到基片120的顶面118的小片附片112的质量。钎焊掩模也可防止基片信号连接焊点、基片下连接区域和焊接区的污染。
在步骤516，钎焊掩模被蚀去以暴露在印刷电路区域的铜，在该区域中将进行连接和钎焊。例如，钎焊掩模被蚀去以暴露图1中的基片下连接区域114、基片信号连接焊点132、138、焊接区144、146和热传播器148。在步骤518，在印刷电路区域暴露的铜(在该处将进行连接和钎焊)，被镀以一层镍，接着在镀镍的铜上镀一层金。金/镍镀层可保护暴露的铜被氧化。另外，金/镍镀层制备暴露的铜以便连接在印刷电路的连接焊点和基片下连接区域上，诸如图1中的基片信号连接焊点132和138和基片下连接区域114。此外，金/镍镀层制备暴露的铜以便钎焊在印刷电路的焊接区和热传播器上，诸如图1中的焊接区144和146和热传播器148。
在步骤520，半导体小片用小片固定材料固定于小片附片焊点上。在图1的构造100中，例如，半导体小片110用小片附片112固定于小片附片焊点111上。如以前所说明，小片附片焊点可以是AUS-5钎焊掩模并且它(即小片附片焊点111)属于直接处于半导体小片110下面的钎焊掩模段。小片附片材料，例如，在图1中所示附片112，可以包括充填银的环氧树脂或bismalemide。一般，小片附片材料可以是导电或电绝缘的热固性粘结剂，或者它们的组合。在本发明另一实施方案中，半导体小片可直接钎焊在支承垫片上，诸如在图1中的支承垫片117。
在步骤522，在半导体小片连接焊点、诸如在图1中半导体小片信号连接焊点104和106，和印刷电路连接焊点、诸如图1中基片信号连接焊点132和138之间执行连接。在图3构造300中，例如，在半导体小片连接焊点306和基片信号连接焊点338之间执行导线连接。在图1构造100中，用于导线连接的连接导线，诸如信号连接导线134和140，可以包括金。在步骤524，半导体小片和连接导线，诸如在图1中半导体小片110，信号连接导线134和140，和下连接导线116，用适当的模塑化合物封装。模塑化合物对在随后制造过程或者使用中提供防止化学污染或物理变化的保护。模塑化合物，例如，可包括各种化学化合物，诸如多功能环氧树脂、新紫胶和联苯树脂，或者其组合物。
在步骤526，包含多个构造100的组合单元的长条被锯割单体化成为单独的单元。在锯割单体化中单独的构造100的组合单元从包含多个构造100的组合单元的长条上切割，以形成大量诸如构造100的构造。应该注意，参照图5描述的过程只是制造图1构造100的一种方法。也应该注意，对于联系图5而讨论总体方法或者各个别的步骤作出的变化或修改对本行业熟练人士是十分明显的。在步骤528，制造图1构造100的代表性过程在此结束。
在图6中构造600阐明按照本发明一个实施方案代表性构造在完成“锯割单体化”后的顶视图。不过，半导体小片和连接导线不是如图6所示。构造600包括对应于图1基片120的基片620。不过，不同于图1中构造100，在构造600中基片连接焊点用轨迹连接到通路上。例如，轨迹610连接基片信号连接焊点638和通路626。相反，在图1构造100中，连接焊点重叠通路。例如，在图1中基片信号连接焊点138重叠通路126。
图6显示基片620的顶面618。轨迹604连接基片连接焊点606和通路602。如以前所说明，轨迹610连接基片连接焊点638和通路626。轨迹616连接基片连接焊点617和通路614。图6也显示小片附片焊点611的顶视图。应该注意，在图6中，为简明起见，只具体讨论通路602、626和614，轨迹604、610和616，和基片连接焊点606、617和638。
在图6构造600中，通路602位于小片附片焊点611附近。通路602可连接到共同接地连接点，在图6中未示，诸如图1构造100中的支承垫片117。通路614位于小片附片焊点611的角上。在构造600中，通路614可连接到共同接地连接点，在图6中未示，诸如图1构造100中的支承垫片117。在图6构造600中，“周边”通路，诸如通路626，典型地作为“信号”通路的功能。
如以前所说明，在图6构造600中，轨迹604、610和616各自连接基片连接焊点606、638和617到通路602、626和614。轨迹604、610和616具有不同的长度。如图6所示，基片连接焊点606、638和637各自处于离通路602、626和614不同的距离。另外，轨迹604和616具有不同的宽度。如此，在图6中的构造600在利用各种基片连接焊点和通路位置、轨迹长度和轨迹宽度方面提供设计灵活性。
如以前所说明，在技术上需要在安置、支承和电气连接半导体小片到嵌入在构造中的天线而提供低寄生效应、有效的散热和低接地感应及电阻的构造。图7到10阐明的本发明实施方案针对这样构造的技术需要。
在图7中的构造700阐明按照本发明一个实施方案代表性嵌入天线构造的底视图。构造700包括对应于图1基片120的基片720。不过，不同于图1中构造100，构造700包括天线轨迹754和756和通路752。此外，在构造700中的热传播器748形状为方形环，而在构造100中热传播器148的形状为圆盘。在本实施方案中，热传播器748的功能也作为防备不需要的电磁幅射到达天线轨迹754和756的屏蔽。热传播器748也屏蔽从天线轨迹754和756放射不需要的电磁幅射到达诸如焊接区746的焊接区。应该注意，在本申请中，热传播器748也称为“屏蔽”。
现在更详细地讨论图7，图7显示基片720底面724。焊接区744和746各自邻接通路726和730。焊接区744和746各自对应图1中构造100的焊接区144和146，并一般包括与144和146同样的材料。如图7所示，焊接区744、746、758和760制造在基片720底面。焊接区744、746、758和760可包括铜或其它诸如铝、钼、钨或金等金属。
继续关于图7，通路726、730、752和728均位于基片720内。通路726、730和728各自对应于图1中构造100的通路126、130和128，并一般包括如通路126、130和128同样的材料。通路726、730、752和728可包括导热材料。通路726、730、752和728可包括铜，并且实际上在代表性构造700中通路726、730、752和728均充满铜。不过，通路726、730、752和728可以用其它材料充填而不致偏离本发明范围。在本发明另一实施方案中，通路726、730、752和728不一定完全充满金属。
如图7所示，热传播器748制造在基片720底面724上。在构造700中，热传播器748可包括铜或其它诸如铝、钼、钨或金等金属。天线轨迹754和756，也集体地称作“天线构造”，在基片720底面724上做成图案，并连接到通路752。在本实施方案中，天线轨迹754和756具有“U”形。在其它实施方案中，天线轨迹可以具有不同形状。虽然在本实施方案中，“天线构造”包括两个天线轨迹，即天线轨迹754和756，在其它实施方案中，“天线构造”可包括单个的天线轨迹。天线轨迹754和756可包括铜或其它诸如铝、钼、钨或金等金属。在图7所示代表性实施方案中，焊接区节距745可以是，例如，500.0微米，而焊接区宽度747可以是，例如，250.0微米。应该注意，在图7中只有通路726、728、730和752，和焊接区744、746、758和760特地在此讨论以保持简要性。
在图8中构造800阐明本发明嵌入天线实施方案的剖面图，其底视图显示在图7的构造700中。在图8中构造800对应于图7中沿8-8线的构造700剖面图。不过，不同于图7中构造700，在构造800中焊接区重叠、而不是邻接通路。例如，焊接区844显示为重叠而不是邻接通路826。这不同于图7中焊接区744，该图显示邻接而不是重叠通路726。在构造800中基片820对应于构造700中基片720。在构造800中通路826、830和828各自对应于构造700中通路726、730和728。在构造800中焊接区844和846各自对应于构造700中焊接区744和746。在构造800中天线轨迹854和856各自对应于构造700中天线轨迹754和756。应该注意，在图8中构造800显示为固定于PCB 850。
现在更详细地讨论图8，图8显示半导体小片810通过小片附片812固定于小片附片焊点811。小片附片焊点811对应于图1中构造100的小片附片焊点111，一般包括与小片附片焊点111同样的材料。小片附片焊点811可以是AUS-5钎焊掩模，并且它(即小片附片焊点811)涉及直接处于半导体小片810下面的钎焊掩模段。不过，小片附片焊点811可包括其它钎焊掩模材料。小片附片焊点811的厚度为，例如，10.0微米到30.0微米。小片附片812对应于图1中构造100的小片附片112。小片附片812包括充填银的环氧树脂或bismalemide.一般，小片附片812可以是导电或电气绝缘的热塑性粘结剂，或它们的组合物。不过，在本发明实施方案中，小片附片812是导电和导热的。
如图8所示，钎焊掩模813施加于基片820的顶面818。钎焊掩模813对应于图1中构造100的钎焊掩模113，并且一般包括与钎焊掩模113同样的材料。钎焊掩模813的厚度可以是，例如，10.0微米到30.0微米。钎焊掩模813可以是AUS-5；不过，钎焊掩模813可以包括其它材料。钎焊掩模815施加于基片820的底面824。钎焊掩模815的厚度可以是，例如，10.0微米到30.0微米。钎焊掩模815可以是AUS-5；不过，钎焊掩模815可以包括其它材料。支承垫片817制造在基片820的顶面818上，并对应于图1中构造100的支承垫片117。在一个实施方案中，支承垫片817可以是铜；不过，支承垫片可以包括铜或其它诸如铝、钼、钨或金等其它金属材料。应该注意，在本发明一个实施方案中，半导体小片可直接钎焊在支承垫片817上。
基片下连接区域814制造在基片820的顶面818上。基片下连接区域814对应于图1中构造100的基片下连接区域114，并一般包括与基片下连接焊点114同样的材料。在图8中构造800中，基片下连接区域814可包括镀镍的铜。基片下连接区域814还可包括在镀镍的铜上一层镀金层。不过，基片下连接区域814可包括其它诸如铝、钼、钨或金等金属。在图8中也显示，下连接导线816的第一端连接在半导体小片810的半导体小片接地连接焊点808上，而下连接导线816的第二端连接到基片下连接区域814。下连接导线816对应于在图1中构造100的下连接导线116，并一般包括与下连接导线116同样的材料。下连接导线816可以是金，或包括其它诸如铝等金属材料。下连接导线816直径大约为30.0微米或其它选择的直径。
如图8中所示，基片820对应于图1中构造100的基片120，并一般包括与基片120同样的材料。在构造800中，基片820可包括两层有机叠层片，诸如聚四氟乙烯或其他如FR4基的叠层片，或陶瓷材料。在图8中构造800中，基片820的厚度大约为200.0微米；不过，在其他实施方案中基片820的厚度可以不同。
继续关于图8，通路828，也称作第一组通路，和通路826及830，也称作第二组通路，均位于基片820内。通路826、830和828从基片820的顶面818延伸到底面824。通路826、830和828各自对应于在图1中构造100的通路126、130和128，并一般包括如通路126、130和128相同的材料。通路826、830和828可包括导热材料。通路826、830和828可包括铜，而实际上，在代表性构造800中通路826、830和828均用铜充填。不过通路826、830和828可充填其它金属而并不偏离本发明范围。在本发明另一实施方案中，通路826、830和828不完全用金属充填。
如图8所示，信号连接导线834的第一端连接在半导体小片810的半导体小片信号连接焊点804上，而信号连接导线834的第二端连接在基片连接焊点832上。信号连接导线834对应于图1中构造100的信号连接导线134，并一般包括如信号连接导线134同样的材料。信号连接导线834可以是金或包括其它诸如铝的金属。信号连接导线834的直径可为30.0微米或其它选择的直径。在图8中还显示信号连接导线840的第一端连接到半导体小片上半导体小片信号连接焊点806上，而信号连接导线840的第二端连接在基片信号连接焊点838上。信号连接导线840可以是金或包括其它诸如铝的金属。信号连接导线840的直径可为30.0微米或其它选择的直径。
在图8中，基片信号连接焊点832制造在基片820的顶面818上。基片信号连接焊点832对应于图1中构造100的基片信号连接焊点132，并一般包括如基片信号连接焊点132同样的材料。在构造800中，基片信号焊点832可包括镀镍的铜，并还可包括在镀镍的铜上一层镀金层。不过，基片信号连接焊点832可以包括其它诸如铝、钼、钨或金等金属。在图8中构造800中，基片信号连接焊点832重叠通路830。在本发明另一实施方案中，不是重叠通路830，而是基片信号连接焊点832邻接通路830。
相似于基片信号连接焊点832，基片信号连接焊点838也制造在基片820的顶面818上。基片信号连接焊点838对应于图1中构造100的基片信号连接焊点138，并一般包括如基片信号连接焊点138同样的材料。在构造800中，基片连接焊点838可包括镀镍的铜。基片信号连接焊点838还可包括在镀镍的铜上一层镀金层。不过，基片信号连接焊点838也可包括其它诸如铝、钼、钨或金等金属。在构造800中，基片信号连接焊点重叠通路826。在本发明其它实施方案中，基片信号连接焊点838邻接通路826。
如图8中所示，焊接区844制造在基片820的底面824上。焊接区844对应于图1中构造100的焊接区144，并一般包括如焊接区144同样的材料。在构造800中，焊接区844可包括铜；不过焊接区844可包括其它诸如铝、钼、钨或金等金属。焊接区844通过钎焊料847固定在PCB 850上。不过，可以用其他行业中熟知的方法把焊接区844固定在PCB 850上。在构造800中，焊接区844重叠通路826。在本发明另一实施方案中，焊接区844邻接通路826。
继续关于图8，焊接区846制造在基片820的底面824上。焊接区846对应于图1的焊接区146，并一般包括如焊接区146同样的材料。在构造800中，焊接区846可为铜；不过，焊接区846可包括其它诸如铝、钼、钨或金等金属。在图8中构造800中，焊接区846通过钎焊料851固定在PCB 850上。不过，可以用其它行业中熟知的方法固定焊接区846到PCB 850上。在构造800上，焊接区846重叠通路830。在本发明另一实施方案中，焊接区846“邻接”通路830。
图8也显示图7热传播器748的剖面部分图。为便于引证，热传播器748的剖面部分848简单地称作热传播器848。如图8所示，热传播器848制造在基片820的底面824上。在图8的构造800中，热传播器848通过钎焊料849固定在PCB850上。不过，可以用其它行业中熟知的方法固定热传播器848到PCB 850上。
在图8中也显示天线轨迹854和856的剖面部分，他们各自对应图7中构造700的天线轨迹754和756。不过，为便于参考，图8中天线轨迹854和856的剖面部分简单地称为天线轨迹854和856。图8阐明天线轨迹854和856如何被热传播器848从两侧所屏蔽。更具体地说，从图8可见，焊接区844和846被热传播器848从天线轨迹854和856屏蔽。应该注意，热传播器848也在本申请中称作“屏蔽”。
图9中构造700阐明本发明另一嵌入天线实施方案剖面图，其底视图显示为在图7中的构造700。图9中构造900对应于图7中沿9-9线的构造700的剖面图。与图8所示构造700的剖面图不同，图9所示构造的剖面图取自在图7中显示通路752的剖面，以及天线轨迹754及756和热传播器748的剖面。应该注意，图8所示构造700的剖面图不是取自通路752(图7)所处位置。
在构造900中，基片920对应于构造700中的基片720，并也对应于图8中构造800的基片820。通路926对应于构造700的通路726，并且也对应于构造800的通路826。通路952对应于构造700的通路752。焊接区944和946各自对应于构造700的焊接区744和746，并也对应于构造800的焊接区844和846。图9也显示图7中热传播器748的剖面部分948。为便于参考，热传播器748的剖面部分948也简单地称为热传播器948。
图9中也显示天线轨迹954和956的剖面部分，它们对应于图7的构造700中天线轨迹754和756。不过为便于参考，在图9中的天线轨迹954和956剖面部分简单地称为天线轨迹954和956。图9阐明天线轨迹如何被热传播器948从两侧屏蔽。更具体地说，在图9中可见，焊接区944和946被热传播器948从天线轨迹954和956屏蔽。
现在讨论图9中其它元件，半导体小片910显示为通过小片附片912固定于小片附片焊点911。半导体小片910、小片附片焊点911和小片附片912各自对应于在图8中构造800的半导体小片810、小片附片焊点811和小片附片812。钎焊掩模913施加于基片920的顶面918，而钎焊掩模915施加于基片920的底面924。在构造900中的钎焊掩模913和915各自对应于在构造800中的钎焊掩模813和815。支承垫片917制造在基片920的顶面918上，并对应于构造800的支承垫片817。基片下连接区域914制造在基片920的顶面918上，并对应于构造800中的基片下连接区域814。
在图9中也显示，下连接导线917的第一端连接在半导体小片的半导体小片接地连接焊点908上，而下连接导线916的第二端连接在基片下连接区域914上。构造900中的下连接导线916、半导体小片接地连接焊点908和半导体小片910各自对应于在图8中构造800的下连接焊点816、半导体小片接地连接焊点808和半导体小片810。通路926和952位于基片920内，并从基片920的顶面918延伸到底面924。
继续关于图9，信号连接导线934的第一端连接到半导体小片910的半导体小片信号连接焊点904上，而信号连接导线934的第二端连接到基片信号连接焊点932上。信号连接导线940的第一端连接到半导体小片910的半导体小片信号连接焊点906上，而信号连接导线940的第二端连接到基片信号连接焊点938上。基片信号连接焊点932和938制造在基片920的顶面918上。
在图9中还显示轨迹919连接基片信号连接焊点932和通路952。轨迹919制造在基片920的顶面918上。在构造900中，轨迹919可包括铜或其它诸如铝、钼、钨或金等金属。焊接区944和946制造在基片920的底面924上。在图9的构造900中，焊接区944和946各自被钎焊料947和951固定在PCB 950上。
在图9中也显示天线轨迹954和956制造在基片920的底面924上，并由通路952连接到轨迹919。在另一实施方案(未在任何图中显示)中，天线轨迹954和956可钎焊在PCB 950上，并由PCB上一个轨迹连通到焊接区，例如图9中焊接区944。在这样的实施方案中，必须在热传播器(或“屏蔽”)948中做一开口，使轨迹可从天线轨迹954和956连通到焊接区，例如焊接区944。在这样实施方案中天线轨迹954和956也可连接到连接焊点，诸如半导体小片信号连接焊点906，例如路经图9中的焊接区944、通路926、基片信号连接焊点938和信号连接导线940。
图10中构造1000阐明本发明嵌入天线实施方案的顶视图，其底视图显示为图7中构造700，而其两代表性剖面图显示为图8和9的构造800和900。构造1000包括基片1020，它对应于图9中基片920(或图8中基片800)。不过，不同于图9中构造900，和图8中构造800，在构造1000中基片信号连接焊点邻接，而不是重叠通路。例如，基片信号连接焊点1038显示为邻接，而不是重叠通路1026。这不同于图9中基片信号连接焊点938，其中显示重叠，而不是邻接通路926。相似地，这不同于图8中基片信号连接焊点838，其中显示为重叠，而不是邻接通路826。
在图10中构造1000中，半导体小片1010对应于图8中构造800的半导体小片810，并也对应于图9中构造900的半导体小片910。轨迹1019和通路1026及1052各自为构造900中轨迹919和通路926及952的顶视图。基片焊点1032和1038各自对应于图9中构造900的基片信号连接焊点932和938。信号连接导线1034和1040各自对应于图9中构造900的信号连接导线934和940。应该注意，在图10中，只有通路1026和1052、基片信号连接焊点1032和1038以及信号连接导线1032和1040在此特地讨论以保持简明性。
现在更详细地讨论图10，半导体小片1010固定在基片1020的顶面1018上。信号连接导线1034的第一端连接到基片信号连接焊点1032上，而信号连接导线1034的第二端连接到半导体小片1010的半导体小片信号连接焊点1004上。信号连接导线1040的第一端连接到基片信号连接焊点1038上，而信号连接导线1040的第二端连接到半导体小片1010的半导体小片信号连接焊点1006上。轨迹1019连接基片信号连接焊点1032和通路1052。如图10中虚线所示，通路1052和轨迹1019的一部分均位于半导体小片1010下面。也应该注意，本发明的嵌入天线实施方案(其不同视图阐明在构造700、800、900和1000中)利用相似于图5所描述的过程步骤制造，因此这些过程步骤不再在此重复。
现在利用图8中构造800作为本发明嵌入天线实施方案的特定的、代表性剖面图，讨论在图7、8、9和10中所示本发明嵌入天线实施方案的电气和热学特性。在构造800中，下连接导线816在半导体小片810上的半导体小片接地连接焊点808和基片下连接区域814之间提供电接地连接。基片下连接区域814位于半导体小片810极近处。利用基片下连接区域814极近半导体小片810的位置，构造800在半导体小片接地连接焊点808和基片下连接区域814之间提供最小的电气接地长度。
支承垫片817的功能是通过向半导体小片接地连接焊点提供较大下共同接地连接而作为半导体小片810的“接地平面”。如此，半导体小片接地焊点808通过下连接导线816电连接到基片下连接区域814，而基片下连接区域814为支承垫片817的一部分。由于基片下连接区域814为支承垫片817的一部分，构造800在半导体小片接地焊点808和支承垫片817之间提供最小的电气接地连接长度。另外，通路828在电气上连接支承垫片817和热传播器848。如此，基片下连接区域814、支承垫片817、通路828和热传播器848联合在半导体小片接地焊点808和热传播器848之间提供具有最小长度、最低电阻和最低感应的接地连接。
此外，在图8的构造800中，可以使用大量的通路828。由于通路828在电气上与支承垫片817和热传播器848之间平行连接，它们(即通路828)在支承垫片817和热传播器848之间提供比较如果由单独的通路提供的电阻和感应途径低许多的电阻和感应途径。如此，通过利用多通路，诸如，图8中的通路828，构造800在支承垫片817和热传播器848之间提供低电阻、低感应、最小长度的电气接地连接。
本发明的一个优点是基片下连接区域814具有足够的尺寸容许称为“双重连接”的程序以进一步使下连接导线816所产生的寄生感应和电阻尽量减少。在“双重连接”中，在半导体小片接地焊点和基片下连接区域之间平行地连接两条下连接导线。在构造800中，可以在图8中半导体小片810上的半导体小片接地焊点808和基片下连接区域814之间连接两条下连接导线。在半导体小片接地焊点808和基片下连接区域814之间两条平行下连接导线所产生的寄生感应和电阻将为大约单个下连接导线所产生寄生感应和电阻的一半。
在图8中所示本发明实施方案中，基片信号连接焊点832和838各自重叠通路830和826。另外焊接区846和844各自重叠通路830和826。如此，通路830和826在基片信号连接焊点和焊接区846和844之间各自提供最短长度的电气连接。如此，通过利用各自“重叠”通路830和826，构造800使基片信号连接焊点832和838和焊接区846和844之间产生的寄生感应最小化。换言之，不需要互连线连接到通路830和826这一事实，导致寄生感应和电阻的减少，否则互相连接线将引入这些感应和电阻。
此外，如参看图8中构造800所见，本实施方案通过支承垫片817、通路828和热传播器848使多余的热量从半导体小片810经热传导散去。在构造800中，通路828可以用诸如铜之类的金属充填。对通路828添加额外的铜可增加其截面积。如此，提供可以通过其导热的较大横截面积可增加通路828的热传导率。在构造800中，支承垫片817可以是诸如铜的导热金属。另外，支承垫片817的大表面面积为半导体小片810产生的热量的导热提供较大的管道。相似地，热传播器848，它也用作天线轨迹854和856的屏蔽，可以是诸如铜的导热金属，并且热传播器848的大表面面积为流过通路828的热传导提供较大的管道。通路828也为支承垫片817和热传播器848之间提供有效并且“多重”的热连接。如此，通过利用支承垫片817、通路828和热传播器848，构造800提供发散半导体小片810所产生热量的有效机制。
应该注意，由于用不同材料制造构造800和PCB 850，在图8中构造800和PCB之间可能存在其热膨胀系数的差别。结果，当由于运行或环境因数而构造800发热时，构造800与PCB 850相比可能以不同膨胀率膨胀。构造800和PCB 850在膨胀率方面的差别造成在连接构造800和PCB 850之间的“钎焊接头”相应的应变。“钎焊接头”包括PCB 850和焊接区844和846之间个别钎焊连接(各自在图8中称作钎焊点847和851)，和在PCB 850和热传播器848之间的钎焊接连接(也称作钎焊点849)。不过，热传播器848比较焊接区844和846在尺寸上大得多。热传播器848在比例上较大的尺寸容许热传播器848在其“钎焊接头”上吸收相应较大的总体应变。因此，通过在其“钎焊接头”上吸收大量总体应变，热传播器848增加构造800的物理可靠性。
参看图9，可见天线轨迹954和956通过通路952、轨迹919、基片信号连接焊点932和信号连接导线934，电连接到半导体小片910上的半导体小片信号连接焊点904。换言之，半导体小片910通过半导体小片信号连接焊点904、信号导线934、基片信号连接焊点932、轨迹919和通路952偶合于天线轨迹954和956。半导体小片910和天线轨迹954和956由支承垫片917互相“屏蔽”，而支承垫片917通过通路(在图9中未示)，诸如图8中的通路828，和热传播器948接地。如此，本发明的实施方案提供一种构造和方法，它可以安置、支持和电气连接半导体小片到构造中嵌入的天线。此外，本发明实施方案提供一种构造和方法可在构造(可安置、支持和电气连接到半导体小片)中嵌入天线，而同时提供低寄生效应、有效的散热和低接地感应及电阻。
从以上对发明的描述可以明白，可以采用各种技术实现本发明的概念而不必偏离其范围。此外，虽然描述本发明涉及某些特定实施方案，本行业熟练人士可以认识到，在形式和细节方面可以作出变化而不致偏离发明的精神和范围。例如，虽然在以上描述的发明的代表性嵌入天线实施方案中，天线构造图案制作在基片的底面，天线构造也可图案制作在基片的顶面。所描述的实施方案应在各方面均认为是说明性的而不是限制性的。应该理解，本发明并不限于这里描述的特定实施方案，也可以作出很多再布置、改型、和代替方案而不致偏离发明的范围。
如此，制造具有嵌入天线的无引线芯片载体的构造和方法已经予以描述。

Claims (12)

1.一种构造，包括：
基片，具有顶面和底面；
半导体小片，固定在所说基片的所说顶面；
天线，固定在所说基片；
印刷电路板，永久地固定在所说基片的所说底面；
第一通路，在所说基片上；
所说第一通路，在小片信号连接焊点和所说印刷电路板之间提供电气连接。
2.按权利要求1所述的构造，其特征在于，所说天线图案制作在所说基片的底面，所说天线偶合于第一基片信号连接焊点。
3.按权利要求2所述的构造，其特征在于，所说第一通路在第二基片信号连接焊点和所说印刷电路板之间提供电气连接，其中所说第二基片信号连接焊点电连接到所说小片信号连接焊点。
4.按权利要求2所述的构造，其特征在于，所说第一通路在所说小片信号连接焊点和焊接区之间提供电气连接，所说焊接区电气连接到所说印刷电路板。
5.按权利要求2所述的构造，其特征在于，还包括固定于所说基片的所说底面的热传播器。
6.按权利要求5所述的构造，其特征在于，所说热传播器为所说天线的屏蔽。
7.一种制造可接受半导体小片的构造的方法，所说方法包括下列步骤：
在基片上钻出第一孔；
在所说第一孔中充填金属以形成第一通路；
把天线固定于所说基片；
在所说基片顶面上图案制作支承垫片，而在所说基片底面上图案制作热传播器，所说第一通路在所说热传播器和所说支承垫片之间提供电气连接，所说支承垫片适合于接受所说半导体小片。
8.按权利要求7所述的方法，其特征在于，所说固定步骤包括在所说基片上的所说底面上图案制作天线的步骤，所说天线偶合于第一基片信号连接焊点。
9.按权利要求8所述的方法，其特征在于，还包括固定所说基片的所说底面到印刷电路板的步骤。
10.按权利要求9所述的方法，其特征在于，所说第一通路在小片信号连接焊点和焊接区之间提供电气连接，所说焊接区电气连接到所说印刷电路板。
11.按权利要求7所述的方法，其特征在于，所说热传播器为所说天线的屏蔽。
12.按权利要求11所述的方法，其特征在于，所说固定步骤包括在所说基片的所说底面上图案制作天线的步骤，所说天线偶合于第一基片信号连接焊点。
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