TW202336962A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202336962A
TW202336962A TW111128755A TW111128755A TW202336962A TW 202336962 A TW202336962 A TW 202336962A TW 111128755 A TW111128755 A TW 111128755A TW 111128755 A TW111128755 A TW 111128755A TW 202336962 A TW202336962 A TW 202336962A
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semiconductor device
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板倉悟
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日商鎧俠股份有限公司
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Abstract

本發明提供一種具有高可靠性之半導體裝置。 半導體裝置具備：配線基板，其具有表面；晶片積層體，其設置於上述表面之上方，包含第1半導體晶片；第2半導體晶片，其設置於上述表面與上述晶片積層體之間；間隔物，其設置於上述表面與上述第1半導體晶片之間，沿上述表面連續包圍上述第2半導體晶片，且包含具有較矽之熱傳導率更高之熱傳導率之材料；及絕緣密封層，其覆蓋上述晶片積層體。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
NAND(Not-AND：反及)型快閃記憶體等之半導體裝置具備積層於配線基板上之複數個半導體晶片。
於實施形態中欲解決之課題之一係提供一種具有高可靠性之半導體裝置。
實施形態之半導體裝置具備：配線基板，其具有表面；晶片積層體，其設置於上述表面之上方，包含第1半導體晶片；第2半導體晶片，其設置於上述表面與上述晶片積層體之間；間隔物，其設置於上述表面與上述第1半導體晶片之間，沿上述表面連續包圍上述第2半導體晶片，包含具有較矽之熱傳導率高之熱傳導率之材料；及絕緣密封層，其覆蓋上述晶片積層體。
以下，參照圖式對實施形態進行説明。圖式所記載之各構成要件之厚度與平面尺寸之關係、各構成要件之厚度之比例等有時與實物不同。又，於實施形態中，對實質上相同之構成要件添附相同之符號並適當省略說明。
於本說明書中，「連接」除特別指定之情形外，不僅包含物理性連接，亦包含電性連接。
(半導體裝置之第1構造例) 圖1係顯示半導體裝置之第1構造例之俯視模式圖。圖2至圖7係用於說明半導體裝置之第1構造例之剖視模式圖。圖1至圖7顯示X軸、垂直於X軸之Y軸、以及垂直於X軸及Y軸之Z軸。另，X軸係例如平行於配線基板1之表面1b之方向，Y軸係平行於表面1b且垂直於X軸之方向，Z軸係垂直於表面1b之方向。圖1顯示X-Y平面之一例。圖1為求方便，未圖示一部分之構成要件或以虛線圖示。圖2顯示圖1之線段A1-B1之X-Z剖面之一例。圖3顯示圖1之線段A2-B2之Y-Z剖面之一例。圖4顯示圖1之線段A1-B1之X-Z剖面之另一例。圖5顯示圖1之線段A2-B2之Y-Z剖面之另一例。圖6顯示圖1之線段A3-B3之X-Z剖面之一例。圖7顯示圖1之線段A4-B4之Y-Z剖面之一例。
半導體裝置100具備配線基板1、晶片積層體2、半導體晶片3、間隔物41、絕緣密封層5、及導電性屏蔽層6。
配線基板1具有設置於表面1a之複數個外部連接端子11、設置於表面1a之相反側之表面1b之複數個接合焊墊12、及複數個接合焊墊13。配線基板1之例包含印刷配線板(PWB：Printed Wiring Board)。
外部連接端子11例如使用金、銅、焊料等形成。外部連接端子11亦可例如使用錫-銀系、錫-銀-銅系之無鉛焊料形成。又，亦可使用複數個金屬材料之積層形成外部連接端子11。另，圖1中，雖使用導電性球形成外部連接端子11，但亦可使用凸塊形成外部連接端子11。
接合焊墊12及接合焊墊13經由配線基板1之內部配線連接於複數個外部連接端子11。接合焊墊12及接合焊墊13含有例如銅、銀、金或鎳等之金屬元素。例如，亦可藉由電解鍍覆法或無電解鍍覆法等形成包含上述材料之鍍覆膜而形成接合焊墊12及接合焊墊13。又，亦可使用導電性膏形成接合焊墊12及接合焊墊13。
晶片積層體2設置於配線基板1之表面1b之上方。晶片積層體2包含複數個半導體晶片20。半導體晶片20之例包含記憶體晶片。複數個半導體晶片20經由間隔物41依序積層於配線基板1之表面1b之上方。晶片積層體2具有：第1晶片積層體，其包含於間隔物41之上彼此逐段積層之4個半導體晶片20；及第2晶片積層體，其包含於間隔物41上彼此逐段積層之4個半導體晶片20。換言之，彼此逐段積層之複數個半導體晶片20彼此部分重疊。另，半導體晶片20之數量及積層構造並不限定於圖1至圖7所示之數量及積層構造。
複數個半導體晶片20各自具有複數個連接焊墊21。各連接焊墊21經由對應之接合導線22連接於各接合焊墊12。接合導線22例如含有金、銀、銅、鋁等之金屬元素。複數個半導體晶片20之一個與另一個例如經由接著層接著。最下段之半導體晶片20例如經由接著層接著於間隔物4。該等接著層之例包含黏晶薄膜(DAF：Die Attach Film)。另，圖1為求方便，以虛線顯示接合焊墊12、半導體晶片20、連接焊墊21、及接合導線22。
半導體晶片3如圖7所示，設置於配線基板1與晶片積層體2之間。半導體晶片3具有複數個連接焊墊31。圖6及圖7所示之半導體晶片3之連接焊墊31雖經由接合導線32電性連接於配線基板1之接合焊墊13，但並不限定於此，亦可使用經由形成於配線基板1或半導體晶片3上之凸塊而將配線基板1與半導體晶片3接合之覆晶接合。
半導體晶片3之例包含記憶體控制器晶片。半導體晶片3搭載於配線基板1之表面1b，經由配線基板1電性連接於半導體晶片20。半導體晶片3亦可經由接著層設置於表面1b。於半導體晶片20為記憶體晶片、半導體晶片3為記憶體控制器晶片之情形時，半導體晶片3控制例如對半導體晶片20寫入資料及讀取資料等動作。
間隔物41係為了於配線基板1與晶片積層體2之間形成用於搭載半導體晶片3之空間而設置。藉此可於晶片積層體2之下方搭載半導體晶片3，故可減小半導體裝置之尺寸。
間隔物41設置於配線基板1與最下段之半導體晶片20之間。間隔物41如圖1所示，沿表面1b連續包圍半導體晶片3。間隔物41經由接著層42與配線基板1接著。接著層42之例包含黏晶薄膜。
間隔物41含有具有較矽之熱傳導率高之熱傳導率之材料。間隔物41含有例如銅等之金屬。間隔物41亦可包含例如氮化鋁等熱傳導率高之陶瓷。再者，若間隔物41之熱傳導率高於矽之熱傳導率，則間隔物41亦可包含矽。間隔物41亦可具有包含陶瓷等絕緣體之基體、與藉由鍍覆處理形成於基體之表面之金屬等導電膜。間隔物41於常溫之熱傳導率較佳為例如170 W·m/K以上。若為200 W·m/K以上則更佳。
間隔物41係例如準備預先加工成所需形狀之包含上述材料之構件，經由接著層42將該構件接著於配線基板1，藉此而形成。
圖2及圖3所示之間隔物41雖較接著層42厚，但並不限定於此，如圖4及圖5所示，間隔物41亦可較接著層42薄。藉由使間隔物41較薄，可削減間隔物41之成本。
絕緣密封層5密封晶片積層體2及半導體晶片3。絕緣密封層5含有氧化矽(SiO 2)等無機填充材料，例如使用將無機填充材料與有機樹脂等混合之密封樹脂，藉由轉注模塑法、壓縮模塑法、注射模塑法等模塑法形成。另，圖1為求方便，省略絕緣密封層5之圖示。
導電性屏蔽層6例如覆蓋配線基板1之側面之至少一部分與絕緣密封層5。導電性屏蔽層6於防止自絕緣密封層5內之半導體晶片20或配線基板1之配線層放射之無用電磁波之洩漏方面，較佳為以電阻率低之金屬層形成，例如應用包含銅、銀、鎳等之金屬層。導電性屏蔽層6之厚度較佳為基於該電阻率設定。另，亦可藉由露出配線基板1內之導通孔之一部分並與導電性屏蔽層6接觸，而將導電性屏蔽層6連接於與接地端子等之外部連接端子連接之配線。另，圖1為求方便，省略導電性屏蔽層6之圖示。
於配線基板1與晶片積層體2之間形成矽間隔物之情形時，雖矽間隔物具有與半導體晶片20之基板之熱傳導率同等之熱傳導率，但難以沿表面1b加工成環狀等之複雜形狀。因此，於沿表面1b以包圍半導體晶片3之方式形成矽間隔物之情形時，有必要使用黏晶機形成複數個矽間隔物。隨著間隔物之構成構件之數量增加，加工時間變長，成本增加。
相對於此，於本實施形態之半導體裝置中，藉由使用與矽相比更容易加工之金屬或陶瓷等材料於配線基板1與晶片積層體2之間形成間隔物，可僅以一個間隔物連續包圍半導體晶片3。因此，可抑制成本之增加。再者，因該等材料之熱傳導率高於矽，故可降低間隔物之熱阻。因此，可提高半導體裝置之散熱性，因而可提高半導體裝置之可靠性。
(半導體裝置之第2構造例) 圖8係顯示半導體裝置之第2構造例之俯視模式圖。圖9至圖12係用於說明半導體裝置之第2構造例之剖視模式圖。圖8至圖12顯示X軸、垂直於X軸之Y軸、以及垂直於X軸及Y軸之Z軸。圖8顯示X-Y平面之一例。圖8為求方便，未圖示一部分之構成要件或以虛線圖示。圖9顯示圖8之線段A5-B5之X-Z剖面之一例。圖10顯示圖8之線段A6-B6之Y-Z剖面之一例。圖11顯示圖8之線段A5-B5之X-Z剖面之另一例。圖12顯示圖8之線段A6-B6之Y-Z剖面之另一例。
半導體裝置100具備配線基板1、晶片積層體2、半導體晶片3、間隔物41、絕緣密封層5、及導電性屏蔽層6。另，關於配線基板1、晶片積層體2、及導電性屏蔽層6，因與半導體裝置之第1構造例相同，因而此處省略說明，可適當援用第1構造例之說明。
間隔物41具有凹部43。凹部43形成連接表面1b之間隔物41之外側區域與間隔物41之內側區域之通路。圖8雖圖示於X軸方向延伸之2個凹部43、與於Y軸方向延伸之2個凹部43，但凹部43之數量並不限定於圖8所示之數量。再者，圖9及圖10所示之凹部43雖面向配線基板1設置，但並不限定於此，凹部43亦可如圖11及圖12所示面向最下段之半導體晶片20設置。又，凹部43之形狀只要可連接間隔物41之外側區域與間隔物41之內側區域，即可不特別限定。凹部43係例如於準備用於形成預先加工成所需形狀之間隔物41之構件時，形成於該構件。間隔物41之其他說明與第1構造例之間隔物41之說明相同。
絕緣密封層5於包含凹部43之通路內延伸且覆蓋半導體晶片3。絕緣密封層5之其他說明與第1構造例之絕緣密封層5相同。
藉由於間隔物41形成凹部43，於形成絕緣密封層5之密封步驟中，因密封樹脂容易經由凹部43流動至配線基板1與晶片積層體2之間之區域，故可充分密封半導體晶片3，可抑制空隙之產生。因此，可提供具有高可靠性之半導體裝置。
另，半導體裝置之第2構造例可與半導體裝置之其他構造例適當組合。
(半導體裝置之第3構造例) 圖13係顯示半導體裝置之第3構造例之俯視模式圖。圖14及圖15係用於說明半導體裝置之第3構造例之剖視模式圖。圖13至圖15顯示X軸、垂直於X軸之Y軸、以及垂直於X軸及Y軸之Z軸。圖13顯示X-Y平面之一例。圖13為求方便，未圖示一部分之構成要件，或以虛線圖示。圖14顯示圖13之線段A7-B7之X-Z剖面之一例。圖15顯示圖13之線段A7-B7之X-Z剖面之另一例之一部分。
半導體裝置100具備配線基板1、晶片積層體2、半導體晶片3、間隔物41、絕緣密封層5、及導電性屏蔽層6。另，關於晶片積層體2、半導體晶片3、及導電性屏蔽層6，因與半導體裝置之第1構造例相同，因而此處省略說明，可適當援用第1構造例之說明。
配線基板1於表面1b進而具備接合焊墊14。接合焊墊14經由配線基板1之內部配線而連接於複數個外部連接端子11。接合焊墊14包含例如可應用於接合焊墊12及接合焊墊13之材料。配線基板1之其他說明與第1構造例之配線基板1相同。
間隔物41具有作為導體之表面，電性連接於配線基板1。圖13及圖14所示之間隔物41雖經由接合導線44電性連接於配線基板1之接合焊墊14，但並不限定於此，間隔物41亦可如圖15所示經由凸塊45電性連接於配線基板1之接合焊墊14。接合焊墊14例如連接於外部連接端子11之接地端子。凸塊45形成於間隔物41之表面。於對間隔物41之表面實施鍍覆處理之情形時，凸塊45形成於藉由鍍覆處理所形成之導電膜之表面。凸塊45之材料例如可舉出可應用於外部連接端子11之材料等。間隔物41之其他說明與第1構造例之間隔物41相同。
絕緣密封層5覆蓋接合導線44或凸塊45，且覆蓋半導體晶片3。絕緣密封層5之其他說明與第1構造例之絕緣密封層5相同。
藉由間隔物41與配線基板1電性連接，可將間隔物41連接於例如接地端子等外部連接端子。藉此，因可使用間隔物41形成電磁屏蔽，故可防止自絕緣密封層5內之半導體晶片20或配線基板1之配線層放射之無用電磁波洩漏，因而可提供具有高可靠性之半導體裝置。另，並不限定於此，間隔物41亦可為浮動狀態。
另，半導體裝置之第3構造例可與半導體裝置之其他構造例適當組合。
雖已說明本發明之若干實施形態，但該等實施形態係作為例子而提示者，並非意欲限定發明之範圍。該等新穎實施形態可以其他各種形態實施，可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化皆包含於發明之範圍或主旨，且包含於申請專利範圍所記載之發明與其均等之範圍內。 [相關申請案]
本申請案享受以日本專利申請案2022-034338號(申請日：2022年3月7日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
1:配線基板 1a:表面 1b:表面 2:晶片積層體 3:半導體晶片 4:間隔物 5:絕緣密封層 6:導電性屏蔽層 11:外部連接端子 12:接合焊墊 13:接合焊墊 14:接合焊墊 20:半導體晶片 21:連接焊墊 22:接合導線 31:連接焊墊 32:接合導線 41:間隔物 42:接著層 43:凹部 44:接合導線 45:凸塊 100:半導體裝置
圖1係顯示半導體裝置之第1構造例之俯視模式圖。 圖2係用於說明半導體裝置之第1構造例之剖視模式圖。 圖3係用於說明半導體裝置之第1構造例之剖視模式圖。 圖4係用於說明半導體裝置之第1構造例之剖視模式圖。 圖5係用於說明半導體裝置之第1構造例之剖視模式圖。 圖6係用於說明半導體裝置之第1構造例之剖視模式圖。 圖7係用於說明半導體裝置之第1構造例之剖視模式圖。 圖8係顯示半導體裝置之第2構造例之俯視模式圖。 圖9係用於說明半導體裝置之第2構造例之剖視模式圖。 圖10係用於說明半導體裝置之第2構造例之剖視模式圖。 圖11係用於說明半導體裝置之第2構造例之剖視模式圖。 圖12係用於說明半導體裝置之第2構造例之剖視模式圖。 圖13係顯示半導體裝置之第3構造例之俯視模式圖。 圖14係用於說明半導體裝置之第3構造例之剖視模式圖。 圖15係用於說明半導體裝置之第3構造例之剖視模式圖。
3:半導體晶片
12:接合焊墊
13:接合焊墊
21:連接焊墊
22:接合導線
31:連接焊墊
32:接合導線
41:間隔物
100:半導體裝置

Claims (10)

  1. 一種半導體裝置，其具備： 配線基板，其具有表面； 晶片積層體，其設置於上述表面之上方，包含第1半導體晶片； 第2半導體晶片，其設置於上述表面與上述晶片積層體之間； 間隔物，其設置於上述表面與上述第1半導體晶片之間，沿上述表面連續包圍上述第2半導體晶片，且包含具有較矽之熱傳導率更高之熱傳導率之材料；及 絕緣密封層，其覆蓋上述晶片積層體。
  2. 如請求項1之半導體裝置，其中上述間隔物包含金屬。
  3. 如請求項1之半導體裝置，其中上述間隔物包含陶瓷。
  4. 如請求項1之半導體裝置，其中上述間隔物之表面係導體。
  5. 如請求項4之半導體裝置，其中上述間隔物電性連接於上述配線基板。
  6. 如請求項5之半導體裝置，其進而具備將上述間隔物與上述配線基板電性連接之接合導線。
  7. 如請求項5之半導體裝置，其進而具備將上述間隔物與上述配線基板電性連接之凸塊。
  8. 如請求項1之半導體裝置，其中上述間隔物經由接著層接合於上述表面；且 上述間隔物薄於上述接著層。
  9. 如請求項1之半導體裝置，其中上述間隔物具有於上述表面上將上述間隔物之外側之第1區域與上述間隔物之內側之第2區域相連接之通路；且 上述絕緣密封層於上述通路內延伸且覆蓋上述第2半導體晶片。
  10. 如請求項1之半導體裝置，其中上述第1半導體晶片係記憶體晶片；且 上述第2半導體晶片係記憶體控制器晶片。
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