TWI832703B - 半導體裝置以及半導體裝置的製造方法 - Google Patents
半導體裝置以及半導體裝置的製造方法 Download PDFInfo
- Publication number
- TWI832703B TWI832703B TW112105463A TW112105463A TWI832703B TW I832703 B TWI832703 B TW I832703B TW 112105463 A TW112105463 A TW 112105463A TW 112105463 A TW112105463 A TW 112105463A TW I832703 B TWI832703 B TW I832703B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- wafer
- semiconductor
- sealing body
- wiring substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 196
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000007789 sealing Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000002470 thermal conductor Substances 0.000 abstract description 52
- 239000012212 insulator Substances 0.000 abstract description 49
- 239000011347 resin Substances 0.000 abstract description 21
- 229920005989 resin Polymers 0.000 abstract description 21
- 235000012431 wafers Nutrition 0.000 description 123
- 238000010586 diagram Methods 0.000 description 42
- 239000011810 insulating material Substances 0.000 description 20
- 230000004048 modification Effects 0.000 description 18
- 238000012986 modification Methods 0.000 description 18
- 125000006850 spacer group Chemical group 0.000 description 13
- 239000012790 adhesive layer Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000000227 grinding Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08123—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting directly to at least two bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/182—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本發明的半導體裝置包括:配線基板;第一半導體晶片,設置於配線基板的上方,具有第一表面以及第二表面,所述第一表面具有與配線基板電性連接的連接端子,所述第二表面為第一表面的相反側;晶片積層體,設置於配線基板的上方,包含第二半導體晶片;密封絕緣體,覆蓋第一半導體晶片及晶片積層體,含有樹脂;以及導熱體,設置於密封絕緣體與第二表面之間,具有第一區域以及第二區域,且具有較樹脂的導熱率高的導熱率,所述第一區域沿著位於配線基板的面內方向的第一方向延伸,所述第二區域在將與配線基板的面內方向及第一方向垂直的方向設為第二方向時自第一區域的第一方向側的端部沿著第二方向延伸。
Description
本發明是有關於一種半導體裝置。
與非(NAND)型快閃記憶體等半導體裝置包括積層於配線基板上的多個半導體晶片。
一實施方式提供一種具有高可靠性的半導體裝置。
實施方式的半導體裝置包括:配線基板;第一半導體晶片,設置於配線基板的上方,具有第一表面以及第二表面,所述第一表面具有與配線基板電性連接的連接端子,所述第二表面為第一表面的相反側;晶片積層體,設置於配線基板的上方,包含第二半導體晶片;密封絕緣體,覆蓋第一半導體晶片及晶片積層體,含有樹脂;以及導熱體,設置於密封絕緣體與第二表面之間,具有第一區域以及第二區域,且具有較樹脂的導熱率高的導熱率,所述第一區域沿著位於配線基板的面內方向的第一方向延伸,所述第二區域在將與配線基板的面內方向及第一方向垂直的方向設為第二方向時自第一區域的第一方向側的端部沿著第二方向延伸。
藉由所述結構,可提供一種具有高可靠性的半導體裝置。
以下,參照圖式對實施方式進行說明。圖式中記載的各構成元件的厚度與平面尺寸的關係、各構成元件的厚度的比率等有時與實物不同。另外,在實施方式中,對實質上相同的構成元件標註相同的符號並適宜省略說明。
在本說明書中,所謂「連接」,除了特別指定的情況以外,不僅包含物理連接,而且亦包含電性連接或熱連接。
(第一實施方式)
圖1至圖4是表示半導體裝置的第一結構例的示意圖。圖1至圖4表示X軸、與X軸垂直的Y軸、以及與X軸及Y軸垂直的Z軸。再者,X軸例如是與配線基板1的表面1b平行的方向,Y軸是與表面1b平行且是與X軸垂直的方向,Z軸是與表面1b垂直的方向。圖1表示自Z軸方向觀察的半導體裝置的上表面的一例。為方便起見,圖1未圖示或以虛線圖示一部分構成元件。圖2表示自Y軸方向觀察的半導體裝置的側面的一例。圖3表示圖1的線段A1-A2處的X-Z剖面的一例。圖4表示圖1的線段A3-A4處的Y-Z剖面的一例。
半導體裝置100包括:配線基板1、晶片積層體2、半導體晶片3、導熱體4、以及密封絕緣體5。
配線基板1具有:設置於表面1a的多個外部連接端子11、設置於表面1a的相反側的表面1b的多個導電性墊12、以及多個導電性墊13。配線基板1的例子包含印刷配線板(printed wire board,PWB)。
外部連接端子11例如使用金、銅、焊料等形成。外部連接端子11例如亦可使用錫-銀系、錫-銀-銅系的無鉛焊料形成。另外,亦可使用多種金屬材料的積層形成外部連接端子11。再者,圖2至圖4圖示了使用導電性球形成的外部連接端子11。
導電性墊12及導電性墊13經由配線基板1的內部配線而連接於外部連接端子11。導電性墊12及導電性墊13例如含有銅、金、鈀或鎳等金屬元素。例如,亦可藉由利用電解鍍敷法或無電解鍍敷法等形成包含所述材料的鍍敷膜而形成導電性墊12及導電性墊13。
晶片積層體2設置於配線基板1的表面1b的上方。晶片積層體2包含多個半導體晶片20。半導體晶片20的例子包含記憶體晶片。作為記憶體晶片,可使用非揮發性記憶體晶片或者揮發性記憶體晶片。作為非揮發性記憶體晶片,可使用NAND記憶體晶片、相變記憶體晶片、電阻變化記憶體晶片、鐵電記憶體晶片、磁性記憶體晶片等。作為揮發性記憶體晶片,可使用動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)晶片等。
多個半導體晶片20經由接著層21而依序積層於配線基板1的表面1b的上方。接著層21的例子包含晶片黏結膜(Die Attach Film,DAF)。圖1至圖4示出:第一晶片積層體,包含彼此逐步積層於表面1b上的四個半導體晶片20;第二晶片積層體,包含彼此逐步積層於第一晶片積層體上的四個半導體晶片20;第三晶片積層體,包含彼此逐步積層於表面1b上的四個半導體晶片20;以及第四晶片積層體,包含彼此逐步積層於第三晶片積層體上的四個半導體晶片20。換言之,彼此逐步積層的多個半導體晶片20彼此部分重疊。再者,半導體晶片20的數量及積層結構並不限定於圖1至圖4所示的數量及積層結構。
多個半導體晶片20各者在表面具有未圖示的多個連接墊。各連接墊經由對應的接合線22而連接於各導電性墊12。接合線22例如含有金、銀、銅、鈀等金屬元素。多個半導體晶片20其中之一與另一個例如經由接著層21而接著。最下段的半導體晶片20例如亦可經由接著層21而接著於表面1b或間隔件。第二晶片積層體及第四晶片積層體的最下段的半導體晶片20下的接著層21較其他接著層21厚,與第一晶片積層體及第三晶片積層體的最上段的半導體晶片20連接的接合線22的一部分埋入至所述厚的接著層21。再者,為方便起見,圖2以虛線表示半導體晶片20、接著層21、及接合線22。
半導體晶片3設置於配線基板1的表面1b的上方。半導體裝置的第一結構例表示在表面1b中多個晶片積層體2設置於半導體晶片3的周圍的例子。半導體晶片3藉由倒裝晶片接合而接合於配線基板1的導電性墊13。半導體晶片3具有包括連接端子31的表面3a、以及表面3a的相反側的表面3b。連接端子31電性連接於配線基板1的導電性墊13。
連接端子31例如使用金、銅、焊料等形成。連接端子31例如亦可使用錫-銀系、錫-銀-銅系的無鉛焊料形成。另外,亦可使用多種金屬材料的積層形成連接端子31。再者,在圖1至圖4中,使用導電性球形成連接端子31,但亦可使用凸塊形成連接端子31。
半導體晶片3的例子包含記憶體控制器晶片。半導體晶片3搭載於配線基板1的表面1b,經由配線基板1的內部配線而電性連接於半導體晶片20。半導體晶片3經由底部填充樹脂32而設置於表面1b。底部填充樹脂32的例子為環氧系熱硬化性樹脂。在半導體晶片20是記憶體晶片、半導體晶片3是記憶體控制器晶片的情況下,半導體晶片3例如對針對半導體晶片20的資料寫入及資料讀出等動作進行控制。
導熱體4具有下板41(第一區域)以及側板42(第二區域)。導熱體4經由接著層44而接著於半導體晶片3的表面3b。接著層44的例子包含DAF。導熱體4與晶片積層體2相離地設置。較佳為在導熱體4與晶片積層體2之間僅存在密封絕緣體5,但並不限定於此。在自Y軸方向觀察時,導熱體4的側板42與晶片積層體2亦可一部分重疊。圖4以雙點鏈線表示下板41的區域與側板42的區域的界面。
下板41是沿著Y軸方向延伸的大致平板,設置於密封絕緣體5與表面3b之間,下表面與接著層44相接。下板41的Y軸方向(沿著位於配線基板1的面內方向的一個方向的方向)的端面(側面)41a自密封絕緣體5露出。側板42是在下板41的Y軸方向的兩端部自朝向Z軸方向的端面(上表面)41b沿著Z軸方向延伸的平板。即,側板42沿著與配線基板1的面內方向及下板41的Y軸方向垂直的方向(Z軸方向)延伸。因此,存在兩塊側板42。此處,側板42亦可僅自下板41的Y軸方向的其中一個端部的端面41b延伸。在此情況下,僅存在一塊側板42。側板42的朝向Y軸方向的端面(側面)42a及朝向Z軸方向的端面(上表面)42b自密封絕緣體5露出。側板42亦可在Z軸方向的上側的端部與未圖示的散熱器相接。下板41的朝向Y軸方向的端面41a亦可不自密封絕緣體5露出。側板42的Y軸方向的端面42a亦可不自密封絕緣體5露出。側板42的Z軸方向的端面42b亦可不自密封絕緣體5露出。散熱器亦可形成於密封絕緣體5上。密封絕緣體5的上表面與側板42的端面42b亦可大致齊平。密封絕緣體5的側面與側板42的端面42a亦可大致齊平。
導熱體4具有較密封絕緣體5中所包含的樹脂的導熱率高的導熱率。導熱體4具有較密封絕緣體5高的導熱率。導熱體4例如使用含有銅等金屬的材料形成。導熱體4例如可藉由如下方式形成:準備預先加工成所期望的形狀的包含所述材料的構件,經由接著層44將該構件接著於半導體晶片3的表面3b。
導熱體4亦可具有與密封絕緣體5相接的氧化物表面或與密封絕緣體5相接的凹凸表面。藉此,可提高導熱體4與密封絕緣體5的密接性。
密封絕緣體5以覆蓋晶片積層體2及半導體晶片3的方式設置,對晶片積層體2及半導體晶片3進行密封。密封絕緣體5含有氧化矽(SiO
2)等無機填充材料、以及環氧系熱硬化性樹脂等樹脂,例如使用將無機填充材料與有機樹脂等混合而成的密封樹脂,藉由傳遞模製法、壓縮模製法、射出模製法等模製法形成。再者,為方便起見,圖1省略密封絕緣體5的圖示。
半導體裝置100亦可在密封絕緣體5的表面具有導電性屏蔽件。導電性屏蔽件例如覆蓋配線基板1的側面的至少一部分以及密封絕緣體5。進而,導電性屏蔽件亦可覆蓋導熱體4。導電性屏蔽件例如能夠藉由利用濺鍍等進行成膜而形成。就防止自密封絕緣體5內的半導體晶片20或配線基板1的內部配線放射的無用電磁波的洩漏的方面而言,導電性屏蔽件較佳為由電阻率低的金屬層形成,例如應用包含銅、不鏽鋼(steel used stainless,SUS)、鎳等的金屬層。導電性屏蔽件的厚度較佳為基於其電阻率而設定。再者,亦可藉由使配線基板1內的通孔的一部分露出並使其與導電性屏蔽件接觸,而將導電性屏蔽件連接於與接地端子等外部連接端子11連接的配線。
本實施方式的半導體裝置的結構並不限定於第一結構例。圖5至圖8是用於對半導體裝置的第二結構例進行說明的示意圖。圖5表示自Z軸方向觀察的半導體裝置的上表面的一例。為方便起見,圖5未圖示或以虛線圖示一部分構成元件。圖6表示自Y軸方向觀察的半導體裝置的側面的一例。圖7表示圖5的線段A1-A2處的X-Z剖面的一例。圖8表示圖5的線段A3-A4處的Y-Z剖面的一例。
與第一結構例相比,半導體裝置的第二結構例更具有設置於配線基板1與晶片積層體2之間的間隔件61、以及設置於間隔件61的上方及半導體晶片3的上方的間隔件62,不同之處在於,在半導體晶片3的上方具有晶片積層體2、換言之在配線基板1與晶片積層體2之間具有半導體晶片3。此處,對與第一結構例不同的部分進行說明,對於其他部分,可適宜援用第一結構例的說明。
間隔件61及間隔件62是為了在配線基板1與晶片積層體2之間形成用於搭載半導體晶片3的空間而設置。藉此,可在晶片積層體2的下方搭載半導體晶片3,因此可減小半導體裝置100的尺寸。
間隔件61設置於配線基板1與最下段的半導體晶片20之間。間隔件62設置於半導體晶片3與最下段的半導體晶片20之間。間隔件61經由接著層21而與配線基板1接著。間隔件61及間隔件62例如含有矽。
圖5至圖8示出:第一晶片積層體,包含彼此逐步積層於表面1b上的四個半導體晶片20;第二晶片積層體,包含彼此逐步積層於第一晶片積層體上的四個半導體晶片20;第三晶片積層體,包含彼此逐步積層於第二晶片積層體上的四個半導體晶片20;以及第四晶片積層體,包含彼此逐步積層於第三晶片積層體上的四個半導體晶片20。換言之,彼此逐步積層的多個半導體晶片20彼此部分重疊。圖5至圖8表示第一晶片積層體至第四晶片積層體各自的最下段的半導體晶片20較其他段的半導體晶片20厚的例子,但並不限定於此,例如所有半導體晶片20的厚度亦可相同。
如以第一結構例及第二結構例為例所列舉般,本實施方式的半導體裝置的結構例具有導熱體4。藉此,可容易使來自半導體晶片3的熱經由導熱體4而移動至半導體裝置100的外部。
為了提高半導體裝置100的散熱性,可考慮加厚半導體晶片3而使其自密封絕緣體5露出的方法。然而,當加厚半導體晶片3時,半導體晶片3佔據了配線基板1的表面1b的中央部,因此半導體晶片20的佈局的自由度降低。
與此相對,在本實施方式的半導體裝置中,藉由形成導熱體4,可抑制半導體晶片20的佈局的自由度的降低,並且提高半導體裝置100的散熱性,因此可提高半導體裝置的可靠性。
(第二實施方式)
本實施方式對第一實施方式的半導體裝置100中的導熱體4的變形例進行說明。此處,對與第一實施方式不同的部分進行說明,對於其他部分,可適宜援用第一實施方式的說明。
圖9及圖10是表示半導體裝置的第一結構例的變形例的示意圖。圖9表示自Z軸方向觀察的半導體裝置的上表面的一例。為方便起見,圖9未圖示或以虛線圖示一部分構成元件。圖10表示自Y軸方向觀察的半導體裝置的側面的一例。
圖11及圖12是用於對半導體裝置的第二結構例的變形例進行說明的示意圖。圖11表示自Z軸方向觀察的半導體裝置的上表面的一例。為方便起見,圖11未圖示或以虛線圖示一部分構成元件。圖12表示自Y軸方向觀察的半導體裝置的側面的一例。
下板41設置於密封絕緣體5與表面3b之間,與接著層44相接。側板42自密封絕緣體5露出,並且以自Y軸方向觀察與晶片積層體2重疊的方式沿X軸方向及Z軸方向延伸。上板43(第三區域)形成於側板42的Z軸方向的端面42b上,且以自Z軸方向觀察與晶片積層體2重疊的方式沿X軸方向及Y軸方向延伸。上板43的朝向Z軸方向的端面43a自密封絕緣體5露出。側板42的Y軸方向的端面42b與密封絕緣體5的側面亦可齊平。上板43的Z軸方向的端面43a與密封絕緣體5的上表面亦可齊平。圖10及圖12以雙點鏈線表示側板42的區域與上板43的區域的界面。
側板42的XZ方向的面積、及上板43的XY方向的各自的面積較下板41的Y軸方向的端面41a的面積大。藉由如此般增大側板42及上板43的面積,可提高半導體裝置100的散熱性。
導熱體4例如可藉由如下方式形成:準備具有下板41及側板42的第一構件,經由接著層44而將該構件接著於半導體晶片3的上表面,形成晶片積層體2後,將具有上板43的第二構件接著於第一構件。並不限定於此,例如亦可藉由如下方式形成:準備具有下板41的第一構件,經由接著層44而將該構件接著於半導體晶片3的上表面,形成晶片積層體2後,將具有側板42及上板43的第二構件接著於第一構件。因此,可在下板41與側板42之間介隔存在接著層。亦可在側板42與上板43之間介隔存在接著層。
再者,本實施方式可與其他實施方式適宜組合。
(第三實施方式)
本實施方式對在第一實施方式的半導體裝置100中的半導體晶片3的側面形成隔熱材料的例子進行說明。此處,對與第一實施方式不同的部分進行說明,對於其他部分,可適宜援用第一實施方式的說明。
圖13及圖14分別是表示半導體裝置的第一結構例、第二結構例的另一變形例的示意圖。圖13及圖14表示X-Z剖面的一例。
第三實施方式的半導體裝置100與第一實施方式的半導體裝置100相比較,不同之處在於更具有隔熱材料7。
隔熱材料7設置於底部填充樹脂32的周圍,並覆蓋半導體晶片3的側面。隔熱材料7的材料可列舉環氧系熱硬化性樹脂。隔熱材料7的導熱率較密封絕緣體5中所包含的樹脂的導熱率低。隔熱材料7的常溫下的導熱率例如小於1 W/m·K。
在本實施方式中,藉由形成隔熱材料7,可抑制來自半導體晶片3的熱向半導體晶片3側面方向移動。因此,可提高半導體裝置100的散熱效率。
再者,本實施方式可與其他實施方式適宜組合。
(第四實施方式)
本實施方式對半導體裝置100的第二結構例的變形例進行說明。此處,對與第一實施方式不同的部分進行說明,對於其他部分,可適宜援用第一實施方式的說明。
圖15及圖16是表示半導體裝置的第二結構例的另一變形例的示意圖。圖15表示自Z軸方向觀察的半導體裝置的上表面的一例。圖16表示Y-Z剖面的一例。
圖15及圖16所示的半導體裝置100與第一實施方式的半導體裝置100的第二結構例相比較,不同之處在於,間隔件62的結構不同、以及包括導熱體9來代替導熱體4。
導熱體9以覆蓋密封絕緣體5的方式設置。導熱體9具有作為導電性屏蔽件的功能。導熱體9的導熱率較密封絕緣體5中所包含的樹脂的導熱率高。導熱體9例如使用銅、鎳、SUS等材料形成。導熱體9可一部分與配線基板1接觸,亦可與配線基板1的接地配線連接。導熱體9亦可覆蓋密封絕緣體5的側面及上表面。
間隔件62具有導熱體621以及隔熱材料622。導熱體621及隔熱材料622沿Y軸方向延伸,自密封絕緣體5露出而與導熱體9相接。
導熱體621的導熱率較密封絕緣體5中所包含的樹脂的導熱率高。導熱體621例如使用矽形成。導熱體621亦可具有與導熱體4的側板42或上板43相當的構件。隔熱材料622亦可具有與導熱體4的側板42或上板43相當的構件。
隔熱材料622設置於導熱體621與晶片積層體2之間。隔熱材料622的導熱率較佳為較密封絕緣體5中所包含的樹脂的導熱率低。隔熱材料622的導熱率例如小於1 W/m·K。隔熱材料622例如使用聚醯亞胺形成。藉由隔熱材料622可抑制來自半導體晶片3的熱向半導體晶片20移動。因此,可提高半導體裝置100的散熱效率。
如以上所述,在本實施方式的半導體裝置中,藉由形成導熱體621及導熱體9來代替導熱體4,可容易使來自半導體晶片3的熱經由導熱體621及導熱體9而移動至半導體裝置100的外部。藉此,可提高半導體裝置100的散熱性,因此可提高半導體裝置的可靠性。
再者,本實施方式可與其他實施方式適宜組合。
(第五實施方式)
在本實施方式中,對半導體裝置的製造方法進行說明。此處,以半導體裝置的第一結構例為例進行說明,但半導體裝置的第二結構例亦能夠藉由相同的步驟製造。
圖17是用於對半導體裝置的製造方法的例子進行說明的流程圖。圖17所示的流程圖具有:半導體晶片3形成步驟S1、導熱體4形成步驟S2、晶片積層體2形成步驟S3、密封絕緣體5形成步驟S4、外部連接端子11形成步驟S5、研削步驟S6、以及單片化步驟S7。
圖18是用於對半導體晶片3形成步驟S1進行說明的示意圖。圖18是X-Z剖面的一例。藉由半導體晶片3形成步驟S1,如圖18所示,在配線基板1的表面1b的上方形成半導體晶片3,將連接端子31與配線基板1電性連接。半導體晶片3藉由如下方式形成:在表面3b形成接著層44,以連接端子31與表面1b的導電性墊13相接的方式搭載後,藉由底部填充樹脂32對表面3a與表面1b之間進行密封。
圖19及圖20是用於對導熱體4形成步驟S2進行說明的示意圖。圖19是X-Z剖面的一例。圖20是Y-Z剖面的一例。藉由導熱體4形成步驟S2,如圖19及圖20所示,經由接著層44而將導熱體4與表面3b接著,藉此隔著半導體晶片3而於配線基板1的上方形成導熱體4。
圖21是用於對晶片積層體2形成步驟S3進行說明的示意圖。圖21是X-Z剖面的一例。藉由晶片積層體2形成步驟S3,如圖21所示,在表面1b的上方經由接著層21而積層半導體晶片20,並形成接合線22,藉此形成晶片積層體2。
圖22及圖23是用於對密封絕緣體5形成步驟S4進行說明的示意圖。圖22是X-Z剖面的一例。圖23是Y-Z剖面的一例。藉由密封絕緣體5形成步驟S4,如圖22及圖23所示,以覆蓋晶片積層體2、半導體晶片3、及導熱體4的方式形成密封絕緣體5。
圖24是用於對外部連接端子11形成步驟S5進行說明的示意圖。圖24是Y-Z剖面的一例。藉由外部連接端子11形成步驟S5,如圖24所示,在表面1a形成外部連接端子11。
圖25是用於對研削步驟S6進行說明的示意圖。圖25是Y-Z剖面的一例。藉由研削步驟S6,如圖25所示,進行沿厚度方向(Z軸方向)部分研削密封絕緣體5的加工,藉此使導熱體4的一部分露出。密封絕緣體5例如能夠藉由化學機械研磨(Chemical Mechanical Polishing,CMP)進行研削。
圖26是用於對單片化步驟S7進行說明的示意圖。藉由單片化步驟S7,如圖26所示,藉由對每一半導體裝置100切割配線基板1而將半導體裝置100單片化,並且使導熱·體4的另一部分露出。例如,藉由沿厚度方向將導熱體4切斷,可使側板42露出。
可藉由以上的步驟形成半導體裝置100。
再者,本實施方式可與其他實施方式適宜組合。
(第六實施方式)
在本實施方式中,對第五實施方式中的半導體裝置的製造方法的變形例進行說明。此處,以半導體裝置的第一結構例為例進行說明,但半導體裝置的第二結構例亦能夠藉由相同的步驟製造。
圖27是用於對半導體裝置的製造方法的變形例進行說明的流程圖。圖27所示的流程圖與圖17所示的流程圖相比較,不同之處在於,在半導體晶片3形成步驟S1與晶片積層體2形成步驟S3之間更具有半導體晶片20形成步驟S8及隔熱材料7形成步驟S9。此處,對與第五實施方式不同的部分進行說明,對於其他部分,可適宜援用第五實施方式的說明。
圖28是用於對半導體晶片20形成步驟S8進行說明的示意圖。圖28是X-Z剖面的一例。藉由半導體晶片20形成步驟S8,如圖28所示,在表面1b的上方僅形成最下段的半導體晶片20。
圖29是用於對隔熱材料7形成步驟S9進行說明的示意圖。圖29是X-Z剖面的一例。藉由隔熱材料7形成步驟S9,形成覆蓋半導體晶片3的側面的至少一部分的隔熱材料7。
在本實施方式中,藉由在形成隔熱材料7之前形成最下段的半導體晶片20,最下段的半導體晶片20作為隔離壁發揮功能,因此可抑制用於形成隔熱材料7的樹脂流動而擴展。
再者,本實施方式可與其他實施方式適宜組合。
對本發明的若干實施方式進行了說明,但該些實施方式是作為例子而提示,並不意圖限定發明的範圍。該些新穎的實施方式能夠以其他各種形態來實施,可在不脫離發明的主旨的範圍內進行各種省略、置換、變更。該些實施方式或其變形包含於發明的範圍或主旨中,並且包含於申請專利範圍所記載的發明及其均等的範圍內。
[相關申請案的引用]
本申請案以基於2022年06月15日提出申請的在前日本專利申請案第2022-096612號的優先權的利益為基礎,且要求其利益,其全部內容以引用的方式包含於本文中。
1:配線基板
1a、1b、3a、3b:表面
2:晶片積層體
3、20:半導體晶片
4、9、621:導熱體
5:密封絕緣體
7、622:隔熱材料
11:外部連接端子
12、13:導電性墊
21、44:接著層
22:接合線
31:連接端子
32:底部填充樹脂
41:下板
41a、42a:端面(側面)
41b、42b:端面(上表面)
42:側板
43:上板
43a:端面
61、62:間隔件
100:半導體裝置
A1-A2、A3-A4:線段
S1:半導體晶片形成步驟
S2:導熱體形成步驟
S3:晶片積層體形成步驟
S4:密封絕緣體形成步驟
S5:外部連接端子形成步驟
S6:研削步驟
S7:單片化步驟
S8:半導體晶片形成步驟
S9:隔熱材料形成步驟
X、Y、Z:軸
圖1是表示半導體裝置的第一結構例的示意圖。
圖2是表示半導體裝置的第一結構例的示意圖。
圖3是表示半導體裝置的第一結構例的示意圖。
圖4是表示半導體裝置的第一結構例的示意圖。
圖5是用於對半導體裝置的第二結構例進行說明的示意圖。
圖6是用於對半導體裝置的第二結構例進行說明的示意圖。
圖7是用於對半導體裝置的第二結構例進行說明的示意圖。
圖8是用於對半導體裝置的第二結構例進行說明的示意圖。
圖9是表示半導體裝置的第一結構例的變形例的示意圖。
圖10是表示半導體裝置的第一結構例的變形例的示意圖。
圖11是用於對半導體裝置的第二結構例的變形例進行說明的示意圖。
圖12是用於對半導體裝置的第二結構例的變形例進行說明的示意圖。
圖13是表示半導體裝置的第一結構例的另一變形例的示意圖。
圖14是表示半導體裝置的第二結構例的另一變形例的示意圖。
圖15是表示半導體裝置的第二結構例的另一變形例的示意圖。
圖16是表示半導體裝置的第二結構例的另一變形例的示意圖。
圖17是用於對半導體裝置的製造方法的例子進行說明的流程圖。
圖18是用於對半導體晶片3形成步驟S1進行說明的示意圖。
圖19是用於對導熱體4形成步驟S2進行說明的示意圖。
圖20是用於對導熱體4形成步驟S2進行說明的示意圖。
圖21是用於對晶片積層體2形成步驟S3進行說明的示意圖。
圖22是用於對密封絕緣體5形成步驟S4進行說明的示意圖。
圖23是用於對密封絕緣體5形成步驟S4進行說明的示意圖。
圖24是用於對外部連接端子11形成步驟S5進行說明的示意圖。
圖25是用於對研削步驟S6進行說明的示意圖。
圖26是用於對單片化步驟S7進行說明的示意圖。
圖27是用於對半導體裝置的製造方法的變形例進行說明的流程圖。
圖28是用於對半導體晶片20形成步驟S8進行說明的示意圖。
圖29是用於對隔熱材料7形成步驟S9進行說明的示意圖。
1:配線基板
2:晶片積層體
3:半導體晶片
4:導熱體
22:接合線
41:下板
42:側板
100:半導體裝置
A1-A2、A3-A4:線段
X、Y、Z:軸
Claims (11)
- 一種半導體裝置,包括:配線基板;第一半導體晶片,設置於所述配線基板,具有第一表面以及第二表面,所述第一表面具有與所述配線基板電性連接的連接端子,所述第二表面為所述第一表面的相反側;晶片積層體,設置於所述配線基板,包含第二半導體晶片;密封體,覆蓋所述第一半導體晶片及所述晶片積層體;第一構件,設置於所述密封體與所述第二表面之間,具有第一區域以及第二區域,且具有較所述密封體的導熱率高的導熱率,所述第一區域沿著位於所述配線基板的面內方向的第一方向延伸,所述第二區域在將與所述第一方向垂直的方向設為第二方向時自所述第一區域的所述第一方向側的端部沿著所述第二方向延伸;以及第三構件,設置於所述第一構件與所述晶片積層體之間,且具有較所述密封體的導熱率低的導熱率。
- 如請求項1所述的半導體裝置,其中,所述第二區域的朝向所述第一方向側的面自所述密封體露出。
- 如請求項1所述的半導體裝置,其中,所述第二區域的朝向所述第二方向側的面自所述密封體露出。
- 如請求項1至3中任一項所述的半導體裝置,其中,所述晶片積層體設置於所述第一半導體晶片的上方, 所述第一構件與所述晶片積層體相離地設置。
- 如請求項1至3中任一項所述的半導體裝置,其中,所述第一構件具有與所述密封體相接的氧化物表面或與所述密封體相接的凹凸表面。
- 如請求項1至3中任一項所述的半導體裝置,更包括第二構件,所述第二構件設置於所述第一半導體晶片的側面,且具有較所述密封體的導熱率低的導熱率。
- 如請求項1至3中任一項所述的半導體裝置,其中,在沿著所述第一方向觀察時,所述晶片積層體的至少一部分與所述第一構件重疊。
- 如請求項1至3中任一項所述的半導體裝置,其中,在沿著所述第一方向觀察時,所述晶片積層體的全部與所述第一構件重疊。
- 一種半導體裝置的製造方法,包括:將如下第一半導體晶片,即具有包括連接端子的第一表面及與所述第一表面為相反側的第二表面的第一半導體晶片設置於配線基板的上方,將所述連接端子與所述配線基板電性連接,將第一構件設置於所述第一半導體晶片的上方,將具有第二半導體晶片的晶片積層體設置於所述配線基板,形成覆蓋所述第一半導體晶片、所述晶片積層體、及所述第一構件的密封體,將第三構件設置於所述第一構件與所述晶片積層體之間,所 述第三構件具有較所述密封體的導熱率低的導熱率,所述第一構件設置於所述密封體與所述第二表面之間,具有第一區域以及第二區域,且具有較所述密封體的導熱率高的導熱率,所述第一區域沿著位於所述配線基板的面內方向的第一方向延伸,所述第二區域在將與所述第一方向垂直的方向設為第二方向時自所述第一區域的所述第一方向側的端部沿著所述第二方向延伸。
- 如請求項9所述的半導體裝置的製造方法,包含在所述第一半導體晶片的側面形成具有較所述密封體的導熱率低的導熱率的第二構件。
- 如請求項9或10所述的半導體裝置的製造方法,包含將所述密封體的一部分削除而使所述第一構件的一部分自所述密封體露出。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2022-096612 | 2022-06-15 | ||
JP2022096612A JP2023183142A (ja) | 2022-06-15 | 2022-06-15 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202401721A TW202401721A (zh) | 2024-01-01 |
TWI832703B true TWI832703B (zh) | 2024-02-11 |
Family
ID=89085036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112105463A TWI832703B (zh) | 2022-06-15 | 2023-02-16 | 半導體裝置以及半導體裝置的製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20230411239A1 (zh) |
JP (1) | JP2023183142A (zh) |
CN (1) | CN117238911A (zh) |
TW (1) | TWI832703B (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180374773A1 (en) * | 2017-06-26 | 2018-12-27 | Shinko Electric Industries Co., Ltd. | Heat sink and electronic component device |
TW201917840A (zh) * | 2017-10-27 | 2019-05-01 | 南韓商愛思開海力士有限公司 | 包括絕熱壁的半導體封裝 |
TW202119566A (zh) * | 2019-11-06 | 2021-05-16 | 日商鎧俠股份有限公司 | 半導體封裝體 |
-
2022
- 2022-06-15 JP JP2022096612A patent/JP2023183142A/ja active Pending
-
2023
- 2023-02-16 TW TW112105463A patent/TWI832703B/zh active
- 2023-02-24 CN CN202310161377.4A patent/CN117238911A/zh active Pending
- 2023-03-03 US US18/177,962 patent/US20230411239A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180374773A1 (en) * | 2017-06-26 | 2018-12-27 | Shinko Electric Industries Co., Ltd. | Heat sink and electronic component device |
TW201917840A (zh) * | 2017-10-27 | 2019-05-01 | 南韓商愛思開海力士有限公司 | 包括絕熱壁的半導體封裝 |
TW202119566A (zh) * | 2019-11-06 | 2021-05-16 | 日商鎧俠股份有限公司 | 半導體封裝體 |
Also Published As
Publication number | Publication date |
---|---|
US20230411239A1 (en) | 2023-12-21 |
TW202401721A (zh) | 2024-01-01 |
CN117238911A (zh) | 2023-12-15 |
JP2023183142A (ja) | 2023-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20200140267A1 (en) | Seal for microelectronic assembly | |
US8729690B2 (en) | Assembly having stacked die mounted on substrate | |
US7888785B2 (en) | Semiconductor package embedded in substrate, system including the same and associated methods | |
JP5912616B2 (ja) | 半導体装置及びその製造方法 | |
JP6564565B2 (ja) | 半導体パッケージ及びその製造方法 | |
TW201921625A (zh) | 具有橫向偏移堆疊之半導體晶粒之半導體裝置 | |
JP2012160707A (ja) | 積層半導体チップ、半導体装置およびこれらの製造方法 | |
US20120248620A1 (en) | Semiconductor device | |
US20150249075A1 (en) | Semiconductor chips having a dual-layered structure, packages having the same, and methods of fabricating the semiconductor chips and the packages | |
TWI710068B (zh) | 具有分層保護機制的半導體裝置及相關系統、裝置及方法 | |
TW201611225A (zh) | 半導體裝置 | |
JP5358089B2 (ja) | 半導体装置 | |
US20230099787A1 (en) | Semiconductor package and method of fabricating the same | |
KR20200037874A (ko) | 보호 기구를 갖는 반도체 디바이스, 관련 시스템, 디바이스 및 방법 | |
KR101917247B1 (ko) | 적층 반도체 패키지 및 그 제조방법 | |
JP2012015225A (ja) | 半導体装置 | |
TWI688067B (zh) | 半導體裝置及其製造方法 | |
TW201633412A (zh) | 半導體裝置及其製造方法 | |
TWI832703B (zh) | 半導體裝置以及半導體裝置的製造方法 | |
TWI409933B (zh) | 晶片堆疊封裝結構及其製法 | |
JP2008187076A (ja) | 回路装置およびその製造方法 | |
JPWO2013118426A1 (ja) | 半導体装置及びその製造方法 | |
TWI830314B (zh) | 半導體裝置 | |
JP6712051B2 (ja) | 半導体装置、半導体装置の製造方法及び電子装置 | |
CN116454038A (zh) | 封装方法及封装结构 |