TW202119566A - 半導體封裝體 - Google Patents

半導體封裝體 Download PDF

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Publication number
TW202119566A
TW202119566A TW108148281A TW108148281A TW202119566A TW 202119566 A TW202119566 A TW 202119566A TW 108148281 A TW108148281 A TW 108148281A TW 108148281 A TW108148281 A TW 108148281A TW 202119566 A TW202119566 A TW 202119566A
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Taiwan
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chip
memory chip
semiconductor package
controller
memory
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TW108148281A
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English (en)
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TWI744761B (zh
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松本学
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日商鎧俠股份有限公司
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Publication of TWI744761B publication Critical patent/TWI744761B/zh

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Abstract

實施型態提供能夠提升信賴性之半導體封裝體。 實施型態之半導體封裝體具備:基板，其具有第1面；至少一個記憶體晶片，其係包含被設置在第1面上之第1記憶體晶片；控制器晶片，其係在第1面上被設置成從記憶體晶片間隔開，能控制第1記憶體晶片；密封構件，其係密封第1記憶體晶片和控制器晶片；及第1構件，其係覆蓋控制器晶片之周圍的至少一部分，其熱傳導率低於密封構件。

Description

半導體封裝體
本申請享有以日本專利申請第2019-201489號(申請日：2019年11月6日)為基礎申請的優先權。本申請藉由參照該基礎申請包含基礎申請之全部內容。 本發明之實施形態係關於半導體封裝體。
提供具備有半導體記憶體晶片、控制半導體記憶體晶片的控制器晶片的半導體封裝體。
本發明之實施型態提供能夠提升信賴性之半導體封裝體。 實施型態之半導體封裝體具備：基板，其具有第1面；至少一個記憶體晶片，其係包含被設置在第1面上之第1記憶體晶片；控制器晶片，其係在第1面上被設置成從第1記憶體晶片間隔開，能控制第1記憶體晶片；密封構件，其係密封第1記憶體晶片和控制器晶片；及第1構件，其係覆蓋控制器晶片之周圍的至少一部分，其熱傳導率低於密封構件。
以下，針對用以實施發明之實施型態進行說明。 在本說明書中，對一些要素賦予複數表現的例。該些表現的例只是例示，並非否定上述要素被賦予其他表現者。再者，即使針對不被賦予複數表現的要素亦可，即使被賦予另外的表現亦可。 圖面為示意圖，厚度和平面尺寸之關係或各層之厚度的比率等與實際的不同。再者，也具有在圖面間彼此尺寸之關係或比率不同的部分。 再者，先針對+X方向、-X方向、+Y方向、-Y方向、+Z方向及-Z方向予以定義。+X方向係在後述基板21以水平從控制器晶片11朝向半導體記憶體晶片12的方向。-X方向為+X方向之相反方向。在不區別+X方向和-X方向之情況單稱為「X方向」。+Y方向係在基板21以水平與X方向交叉(例如略正交)的方向。-Y方向為+Y方向之相反方向。在不區別+Y方向和-Y方向之情況單稱為「Y方向」。+Z方向係在與基板21垂直之方向，即與X方向及Y方向交叉(例如略正交)的方向，為從基板21朝向控制器晶片11的方向。-Z方向係從基板21朝向焊球25的方向，為+Z方向的相反方向。在不區別+Z方向和-Z方向之情況單稱為「Z方向」。Z方向為例如基板21之厚度方向。 (第1實施形態) 圖1至圖5表示第1實施型態所涉及之半導體封裝體1。半導體封裝體1為半導體裝置之一例。本實施型態所涉及之半導體封裝體為例如BGA-SSD(Ball Grid Array-Solid State Drive)，至少一個半導體記憶體晶片，和控制半導體記憶體晶片的控制器晶片被構成一體以作為一個BGA型的封裝體。如此之半導體封裝體被搭載於個人電腦(PC)或行動電話等之電子機器，當作電子機器之儲存裝置而發揮功能。 圖1係示意性地表示於半導體封裝體1被安裝於電子機器之時所使用的電路基板2之構成的一部分。電路基板2包含主控制器3、訊號線4、電源電路5和電源線6(6a、6b)。本實施型態所涉及之主控制器3及半導體封裝體1具有依照PCI-Express(PCIe)(註冊商標)之規格的介面。在主控制器3和半導體封裝體1之間設置複數條之訊號線4。半導體封裝體1經由訊號線4在與主控制器3之間處理依照PCIe之規格的高速訊號。電源電路5係經由電源線6(6a、6b)分別被連接於主控制器3及半導體封裝體1。電源線6a係連接電源電路5和主控制器3，電源線6b係連接電源電路5和半導體封裝體1。電源電路5係對主控制器3及半導體封裝體1供給電子機器動作用的電力。 主控制器3及半導體封裝體1之通訊介面即使使用SAS(Serial Attached SCSI)、SATA(Serial Advanced Technology Attachment)或USB(Universal Serial Bus)等之其他規格亦可。 被搭載於電子機器的主控制器3係例如CPU，控制包含被連接或搭載於電子機器的儲存裝置的電子機器全體。 接著，針對半導體封裝體1之構成予以說明。 圖2為表示半導體封裝體1之構成之一例的方塊圖。半導體封裝體1具備控制器晶片(控制器)11、半導體記憶體晶片12、DRAM晶片13、振盪器(OSC)14、EEPROM (Electrically Erasable and Programmable ROM)15及溫度感測器16。 控制器晶片11係控制半導體記憶體晶片12之動作的半導體晶片。半導體記憶體晶片12係例如NAND型快閃記憶體晶片(NAND晶片)。NAND晶片係非揮發性記憶體，即使在不進行電力供給之狀態亦保持資料。DRAM晶片(DRAM)13被使用於半導體記憶體晶片12之管理資訊之保管或資料之快取等。 振盪器(OSC)14係將特定頻率之動作訊號供給至控制器晶片11。EEPROM15係儲存控制程式等之非揮發性記憶體之一例。溫度感測器16係檢測半導體封裝體1內之溫度，通知至控制器晶片11。 控制器晶片11即使在被搭載於半導體封裝體1之半導體晶片之中，為了消耗大的電力，比起其他半導體晶片更容易成為高溫。當控制器晶片11之熱傳達至其他半導體晶片時，其他半導體晶片之性能下降。 在例如DRAM晶片13中，當溫度上升，更新週期之效率下降，資料變得容易消失。再者，再如NAND晶片12般之非揮發性半導體記憶體晶片中，當溫度上升時，資料之保持能力下降，被記憶的資料之可靠性下降。 接著，針對與第1實施型態所涉及之半導體封裝體1之構成予以說明。 圖3A及圖3B係半導體封裝體1之剖面圖，圖4為半導體封裝體1之上視圖。再者，為了方便說明，在圖3A、圖3B及圖4中，省略半導體封裝體1所具備的振盪器14、EEPROM15等之一部分的構成。再者，以下，也將半導體記憶體晶片稱為記憶體晶片。 半導體封裝體1具備基板21、控制器晶片11、至少一個以上之半導體記憶體晶片12、密封構件22、第1構件23及複數焊球25。 基板21在表面具備安裝膜24，在內部具備內部配線26。基板21具有第1面21a，和位於與第1面21a相反側的第2面21b。 控制器晶片11被設置在第1面21a上。控制器晶片11在基板21上藉由安裝膜24被固定。控制器晶片11具有電極墊28，與內部配線26電性連接。控制器晶片11係例如圖3A所示般，藉由金屬線202所致的打線接合，或如圖3B所示般，藉由倒裝晶片接合而被連接。 半導體記憶體晶片12在X方向與控制器晶片11隔著空間被設置在第1面21a上，在基板21上藉由安裝膜24被固定。半導體記憶體晶片12具有電極墊27。藉由例如連接金屬線201和電極墊27的打線接合，半導體記憶體晶片12與內部配線26電性連接。半導體記憶體晶片12經由內部配線26被電性連接於控制器晶片11。 密封構件22係在基板21上密封控制器晶片11和半導體記憶體晶片12的構件。 即使固定控制器晶片11之安裝膜24之熱傳導率高於密封構件22之熱傳導率亦可。在此情況，發揮將控制器晶片11之熱有效率地傳至基板21的作用。 第1構件23被設置在第1面21a上，覆蓋控制器晶片11之周圍之至少一部分。在此，所述的周圍係指控制器晶片11與基板21相接之面以外的面。並且，第1構件23在X方向中位於控制器晶片11和半導體記憶體晶片12之間。第1構件23之熱傳導率較密封構件22之熱傳導率低，難以將來自控制器晶片11之發熱傳到半導體記憶體晶片12。 基板21在第2面21b上具備焊球25，經由焊球25，能與電子機器之電路基板2電性連接。 藉由上述構造，控制器晶片11之熱難藉由第1構件23傳至密封構件22，同樣也難傳至以半導體記憶體晶片12為首的其他半導體晶片。再者，控制器晶片11之熱經由安裝膜24、基板21、焊球25被散熱至電路基板2之方向。因此，能夠抑制熱傳導對半導體記憶體晶片12般之半導體封裝體1內的其他半導體晶片的影響，能夠防止熱所致的功能下降。 [變形例] 即使本實施型態所涉及之半導體封裝體1如圖5般具備第2構件29亦可。第2構件29被設置成進一步覆蓋第1構件23之周圍的至少一部分。在此，所述的周圍係指第1構件23與基板21相接之面以外的面。並且，第2構件29在X方向中位於第1構件23和半導體記憶體晶片12之間。第2構件29之熱傳導率低於例如密封構件22之熱傳導率，並且即使低於第1構件23之熱傳導率亦可。 在第2構件29具有比第1構件23低的熱傳導率之情況，可以抑制無法完全以第1構件23被絕熱的控制器晶片11之熱傳至其他半導體晶片之情形。在此所指的絕熱係指比起經由密封構件22，更難以經由第1構件23或第2構件29，將控制器晶片11之熱傳導至以半導體記憶體晶片12為首的半導體晶片的情形。 即使藉由該些構造，控制器晶片11之熱藉由第1構件23、第2構件29難傳至密封構件22，同樣也難傳至以半導體記憶體晶片12為首的其他半導體晶片。再者，控制器晶片11之熱經由安裝膜24、基板21、焊球25被散熱至電路基板2之方向。因此，能夠抑制熱傳導對半導體記憶體晶片12般之半導體封裝體1內的其他半導體晶片的影響，能夠防止熱所致的功能下降。 密封構件22、第1構件23及第2構件29可以由例如酚樹脂、環氧樹脂、PET(聚對苯二甲酸乙二酯)、碳黑(直徑3～500nm左右之碳的微粒子)或氧化矽(二氧化矽)或該些混合物構成。藉由變更混合比，縮小熱傳導率高的材料(例如，碳黑或氧化矽等之金屬)的含有率，能夠降低熱傳導率。 在本實施型態中，即使疊層一個或複數片半導體記憶體晶片12亦可。 (第2實施形態) 接著，針對與第2實施型態所涉及之半導體封裝體1之構造予以說明。 圖6為本實施型態所涉及之半導體封裝體1之剖面圖，圖7及圖8為本實施型態所涉及之半導體封裝體1之上視圖。再者，為了方便說明，在圖6至圖8中，省略半導體封裝體1所具備的振盪器14、EEPROM15等之一部分的構成。針對第2實施型態之半導體封裝體1之各部，以相同符號表示與第1實施型態之半導體封裝體1之各部相同的部分。 半導體封裝體1具備基板21、控制器晶片11、複數半導體記憶體晶片12、密封構件22、第1構件23、安裝膜24及複數焊球25。 基板21在內部具備內部配線26。基板21具有第1面21a，和位於與第1面21a相反側的第2面21b。 如圖6至圖8所示般，被設置在第1面21a之半導體記憶體晶片12被分在兩處而疊層。將各者設為第1記體體晶片群12a、第2記憶體晶片群12b。該些記憶體晶片群係藉由例如安裝膜24被固定在第1面21a。再者，為了方便說明，在構成第1記憶體晶片群12a之複數半導體記憶體晶片12內，將在Z方向最接近於基板21之半導體記憶體晶片12設為記憶體晶片12aW，將被疊層於記憶體晶片12aW之半導體記憶體晶片12設為記憶體晶片12aV。並且，將被疊層於記憶體晶片12aV之半導體記憶體晶片12設為記憶體晶片12aU。在構成第2記憶體晶片群12b之複數半導體記憶體晶片12內，將在Z方向最接近於基板21之半導體記憶體晶片12設為記憶體晶片12bW，將被疊層於記憶體晶片12bW之半導體記憶體晶片12設為記憶體晶片12bV。並且，將被疊層於記憶體晶片12bV之半導體記憶體晶片12設為記憶體晶片12bU。 控制器晶片11被設置在第1面21a上，在X方向位於記憶體晶片12aW和12bW之間。控制器晶片11係藉由例如安裝膜24被固定在第1面21a上。控制器晶片11具有電極墊28，藉由例如打線接合或倒裝晶片接合與基板21內之內部配線26電性連接。 圖7為僅表示被疊層之複數半導體記憶體晶片12之中，在Z方向中最接近於基板21之記憶體晶片12aW、12bW的圖。在本實施型態中，控制器晶片11係在X方向被安裝於記憶體晶片12aW和記憶體晶片12bW之間的區域B。另外，在圖7中，區域B係以一點鏈線包圍的區域。 參照圖6，針對在Z方向中之各構成要素間的距離予以說明。在Z方向中之構成要素和構成要素之距離係指例如半導體封裝體1所含的各構成要素(例如，控制器晶片11、記憶體晶片12)之Z方向之中心點和中心點之最小距離。如圖6所示般，在與基板21垂直之Z方向中，記憶體晶片12aV、12bV和控制器晶片11之距離A分別大於記憶體晶片12aW、12bW和控制器晶片11之距離C。再者，在與基板21垂直之Z方向中，記憶體晶片12aU、12bU和控制器晶片11之距離H分別大於記憶體晶片12aV、12bV和控制器晶片11之距離A。 同樣，參照圖8，針對在X方向中之各構成要素間的距離予以說明。在X方向中之構成要素和構成要素之距離係指例如半導體封裝體1所含的各構成要素(例如，控制器晶片11、記憶體晶片12)之X方向之中心點和中心點之最小距離。在此，將記憶體晶片12aU之中心點設為u，將記憶體晶片12aV之中心點設為v，將記憶體晶片12aW之中心點設為w。同樣，將記憶體晶片12aU之中心點設為u’，將記憶體晶片12bV之中心點設為v’，將記憶體晶片12bW之中心點設為w’。記憶體晶片12aV和控制器晶片11之距離E小於記憶體晶片12aW和控制器晶片11之距離D。記憶體晶片12bV和控制器晶片11之距離G小於記憶體晶片12bW和控制器晶片11之距離F。再者，記憶體晶片12aU和控制器晶片11之距離I小於記憶體晶片12aV和控制器晶片11之距離E。記憶體晶片12bU和控制器晶片11之距離J小於記憶體晶片12bV和控制器晶片11之距離G。 換言之，在記憶體晶片群12a、12b之各者所含的至少n片之半導體記憶體晶片12之中，從最接近於基板21起算第i個半導體記憶體晶片12之上，疊層第i+1個的半導體記憶體晶片12。此時，第i+1個半導體記憶體晶片12以比起第i個半導體記憶體晶片12，在X方向中，離控制器晶片11的距離較小之狀態被疊層。在此所指的n為2以上之整數，i係指n未滿之整數。 再者，即使如圖8所示般，當從Z方向俯視觀看半導體封裝體1之時，構成記憶體晶片群12a、12b之至少一個半導體記憶體晶片12之至少一部分與在X方向及Y方向的包含控制器晶片11之區域B重疊亦可。 構成記憶體晶片群12a、12b之至少一個以上之半導體記憶體晶片12具有電極墊27。藉由例如連接金屬線201和電極墊27的打線接合，半導體記憶體晶片12彼此各被電性連接。構成記憶體晶片群12a、12b之至少一個以上之半導體記憶體晶片12經由電極墊27而與基板21內之內部配線26電性連接。控制器晶片11具有電極墊28，藉由例如打線接合或倒裝晶片接合與內部配線26電性連接。構成記憶體晶片群12a、12b之至少一個以上之半導體記憶體晶片12能經由內部配線26被電性連接於控制器晶片11。 密封構件22係在基板21上密封控制器晶片11和記憶體晶片群12a、12b的構件。 即使固定控制器晶片11之安裝膜24之熱傳導率高於密封構件22之熱傳導率亦可。在此情況，發揮將控制器晶片11之熱有效率地傳至基板21的作用。 第1構件23被設置在第1面21a上，覆蓋控制器晶片11之周圍之至少一部分。在此所述的周圍係指控制器晶片11與基板21相接之面以外的面。並且，第1構件23在X方向中位於控制器晶片11和半導體記憶體晶片12之間。第1構件23之熱傳導率較密封構件22之熱傳導率低，難以將來自控制器晶片11之發熱傳到半導體記憶體晶片12。 基板21在第2面21b上具備焊球25，經由焊球25，能與電子機器之電路基板2電性連接。 藉由上述構造，控制器晶片11之熱難藉由第1構件23傳至密封構件22，同樣也難傳至以半導體記憶體晶片12為首的其他半導體晶片。再者，控制器晶片11之熱經由安裝膜24、基板21、焊球25被散熱至電路基板2之方向。因此，採用被疊層成當從Z方向俯視觀看半導體封裝體1之時，至少一個半導體記憶體晶片12之至少一部分與在X方向及Y方向之包含控制器晶片11之區域B重疊之構造的記憶體晶片群12a、12b難受到熱的影響。因此，能夠抑制熱傳導對半導體記憶體晶片12般之半導體封裝體1內的其他半導體晶片的影響，能夠防止熱所致的功能下降。 [變形例] 如圖9所示般，即使在本實施型態中的半導體封裝體1於第1構件23和密封構件22之間也具備第2構件29亦可。 (第3實施形態) 接著，針對與第3實施型態所涉及之半導體封裝體1之構成予以說明。 圖10、圖11、圖14及圖15係本實施型態所涉及之半導體封裝體1之剖面圖，圖12、圖13及圖16為本實施型態所涉及之半導體封裝體1之上視圖。再者，為了方便說明，在圖10至圖16中，省略半導體封裝體1所具備的振盪器14、EEPROM15等之一部分的構成。 針對第3實施型態之半導體封裝體1之各部，以相同符號表示與第1實施型態之半導體封裝體1之各部相同的部分。如圖10至圖16所示般，第3實施型態所涉及之半導體封裝體1與第1實施型態不同之點係在半導體記憶體晶片12和控制器晶片11之間配置壁構件31，以取代覆蓋控制器晶片11之周圍之至少一部分的第1構件23。 壁構件31具有第1端部311、第2端部312、第3端部313及第4端部314。將與基板21之第1面21a相接之端部設為第1端部311，將與第1端部311相向之端部設為第2端部312。將與1面21a略垂直之端部之一方設為第3端部313，將與第3端部313相向之端部設為第4端部314。壁構件31係以防止來自控制器晶片11之發熱經由密封構件22傳至半導體封裝體1內之其他半導體晶片之情形為目的而設置的壁狀構件。 如圖10所示般，壁構件31若較在Z方向之控制器晶片11之厚度更往Z方向延伸即可。因此，即使第2端部312在Z方向藉由密封構件22被密封亦可。再者，即使如圖11所示般，第2端部312在第Z方向露出於密封構件22之表面亦可。 圖12及圖13係從Z方向俯視觀看本實施型態所涉及之半導體封裝體1之圖，為了方便說明，省略密封構件22。若壁構件31之沿著Y方向的寬度較沿著控制器晶片11之沿著Y方向的寬度更延伸即可。因此，即使如圖12所示般，在Y方向中，第3端部313及第4端部314藉由密封構件22被密封亦可。即使如圖13所示般，在Y方向中，第3端部313及第4端部314露出於密封構件22之表面亦可。即使第3端部313和第4端部314在Y方向中，其中一個露出至密封構件22之表面，其中另一個藉由密封構件22被密封亦可。 壁構件31之熱傳導率與密封構件22之熱傳導率不同。壁構件31可以由例如酚樹脂、環氧樹脂、PET(聚對苯二甲酸乙二酯)、碳黑(直徑3～500nm左右之碳的微粒子)或氧化矽(二氧化矽)或該些混合物構成。當熱傳導率高之材料(例如碳黑或氧化矽等之金屬)之含有率小之時，壁構件31之熱傳導率低於密封構件22之熱傳導率。由於壁構件31之熱傳導率低於密封構件22之熱傳導率，故來自控制器晶片11之發熱難以傳至以半導體記憶體晶片12為首的半導體封裝體1內之其他半導體晶片。再者，控制器晶片11之熱經由安裝膜24、基板21、焊球25被散熱至電路基板2之方向。 再者，即使壁構件31由例如Al-SiC等之合成金屬構成亦可。此時，壁構件31之熱傳導率高於密封密件22之熱傳導率。來自控制器晶片11之發熱傳至壁構件31之後，第1端部311以外的端部藉由密封構件22被密封之情況，朝基板21之方向散熱，在第1端部311以外之端部露出至密封構件22之表面之情況，朝基板21之方向及半導體封裝體1之外散熱。 如上述般，無論在壁構件31之熱傳導率高於或低於密封構件22之熱傳導率之情況，皆能夠抑制熱傳導對半導體記憶體晶片12般之半導體封裝體1內的其他半導體晶片的影響，能夠防止熱所致的功能下降。 再者，即使如圖14至圖16所示般，在本實施型態之半導體封裝體1中，與第1實施型態相同，在控制器晶片11之周圍具備第1構件23亦可。 並且，即使在本實施型態之半導體封裝體1中與第1實施型態相同，在X方向，於第1構件23和密封構件22之間具備第2構件29亦可。 以上，雖然說明本發明之幾個實施型態，但是該些實施型態透過舉例之方式來表呈現，並無限定發明之範圍的意圖。該些新增實施型態可以其他各種型態來實施，只要在不脫離發明之要旨的範圍下，可做各種省略、置換及變更。該些實施型態或其變形例當然也包含在發明範圍或要旨中，並且包含於申請專利範圍所記載之發明和其均等之範圍中。
1:半導體封裝體 2:電路基板 3:主控制器 4:訊號線 5:電源電路 6:電源線 11:控制器晶片 12:半導體記憶體晶片(NAND晶片) 13:DRAM晶片 14:振盪器(OSC) 15:EEPROM 16:溫度感測器 21:基板 22:密封構件 23:第1構件 24:安裝膜 25:焊球 26:內部配線 27:電極墊 28:電極墊 29:第2構件 201:金屬線 202:金屬線 31:壁構件 311:第1端部 312:第2端部 313:第3端部 314:第4端部
[圖1]係示意性地表示包含搭載第1實施型態所涉及之半導體封裝體之電路基板的電子機器的構成之一部分的圖。 [圖2]為表示第1實施型態所涉及之半導體封裝體之構成一例的方塊圖。 [圖3A]為第1實施型態所涉及之半導體封裝體之剖面圖。 [圖3B]為第1實施型態所涉及之半導體封裝體之剖面圖。 [圖4]為第1實施型態所涉及之半導體封裝體之上視圖。 [圖5]為第1實施型態之變形例所涉及之半導體封裝體之剖面圖。 [圖6]為第2實施型態所涉及之半導體封裝體之剖面圖。 [圖7]為表示除去第2實施型態所涉及之半導體封裝體之一部分構成的上視圖。 [圖8]為第2實施型態所涉及之半導體封裝體之上視圖。 [圖9]為第2實施型態之變形例所涉及之半導體封裝體之剖面圖。 [圖10]為第3實施型態所涉及之半導體封裝體之剖面圖。 [圖11]為第3實施型態所涉及之半導體封裝體之剖面圖。 [圖12]為第3實施型態所涉及之半導體封裝體之上視圖。 [圖13]為第3實施型態所涉及之半導體封裝體之上視圖。 [圖14]為第3實施型態所涉及之半導體封裝體之剖面圖。 [圖15]為第3實施型態所涉及之半導體封裝體之剖面圖。 [圖16]為第3實施型態所涉及之半導體封裝體之上視圖。
1:半導體封裝體
2:電路基板
11:控制器晶片
12:半導體記憶體晶片(NAND晶片)
21:基板
21a:第1面
21b:第2面
22:密封構件
23:第1構件
24:安裝膜
25:焊球
26:內部配線
27:電極墊
28:電極墊
201:金屬線
202:金屬線

Claims (19)

  1. 一種半導體封裝體，具備： 基板，其具有第1面； 至少一個記憶體晶片，其包含被設置在上述第1面上之第1記憶體晶片； 控制器晶片，其係在上述第1面上被設置成從上述第1記憶體晶片間隔開，能控制上述第1記憶體晶片； 密封構件，其係密封上述第1記憶體晶片和上述控制器晶片；及 第1構件，其係覆蓋上述控制器晶片之周圍之至少一部分，其熱傳導率低於上述密封構件。
  2. 如請求項1之半導體封裝體，其中 上述第1構件位於上述第1記憶體晶片和上述控制器晶片之間。
  3. 如請求項1或2之半導體封裝體，其中 進一步具備第2構件，其熱傳導率低於上述第1構件之熱傳導率，被配置在上述第1構件和上述密封構件之間。
  4. 如請求項1或2之半導體封裝體，其中 上述基板進一步具備安裝膜，其係將上述第1記憶體晶片和上述控制器晶片分別固定在上述第1面，其熱傳導率高於上述密封構件。
  5. 如請求項1或2之半導體封裝體，其中 上述第1記憶體晶片和上述控制器晶片與上述第1面相接。
  6. 如請求項1或2之半導體封裝體，其中 上述基板具有內部配線，和在與上述第1面相反側之第2面上的焊球， 上述控制器晶片具有電極墊， 上述控制器晶片經由上述內部配線和上述電極墊被電性連接， 上述內部配線經上述焊球能與外部之電路基板電性連接。
  7. 如請求項1或2之半導體封裝體，其中 上述記憶體晶片為複數， 上述複數記憶體晶片構成由被疊層在上述第1面上之複數上述記憶體晶片構成之第1記憶體晶片群，和被疊層在上述第1面上之複數上述記憶體晶片構成之第2記憶體晶片群， 上述控制器晶片位於上述第1記憶體晶片群，和上述第2記憶體晶片群之間。
  8. 如請求項7之半導體封裝體，其中 構成上述第1記憶體晶片群之上述複數記憶體晶片包含上述第1記憶體晶片和第3記憶體晶片， 在與上述基板垂直之第1方向中，上述第3記憶體晶片和上述控制器晶片之距離大於上述第1記憶體晶片和上述控制器晶片之距離， 在上述基板以水平從上述第1記憶體晶片群朝向上述控制器晶片之第2方向中，上述第3記憶體晶片和上述控制器晶片之距離小於上述第1記憶體晶片和上述控制器晶片之距離， 構成上述第2記憶體晶片群之上述複數記憶體晶片包含上述第2記憶體晶片和第4記憶體晶片， 在上述第1方向中，上述第4記憶體晶片和上述控制器晶片之距離大於上述第2記憶體晶片和上述控制器晶片之距離， 在上述基板以水平從上述第2記憶體晶片群朝向上述控制器晶片之第3方向中，上述第4記憶體晶片和上述控制器晶片之距離小於上述第2記憶體晶片和上述控制器晶片之距離。
  9. 如請求項8之半導體封裝體，其中 構成上述第1記憶體晶片群之上述複數記憶體晶片進一步包含上述第5記憶體晶片， 在上述第1方向中，上述第5記憶體晶片和上述控制器晶片之距離大於上述第3記憶體晶片和上述控制器晶片之距離， 在上述第2方向中，上述第5記憶體晶片和上述控制器晶片之距離小於上述第3記憶體晶片和上述控制器晶片之距離， 構成上述第2記憶體晶片群之上述複數記憶體晶片進一步包含上述第6記憶體晶片， 在上述第1方向中，上述第6記憶體晶片和上述控制器晶片之距離大於上述第4記憶體晶片和上述控制器晶片之距離， 在上述第3方向中，上述第6記憶體晶片和上述控制器晶片之距離小於上述第4記憶體晶片和上述控制器晶片之距離。
  10. 如請求項8之半導體封裝體，其中 在從上述第1方向觀看的俯視中，上述控制器晶片和屬於上述第1記憶體晶片群或上述第2記憶體晶片群中之任一個的至少一個記憶體晶片之至少一部分重複。
  11. 一種半導體封裝體，具備： 基板，其具有第1面； 記憶體晶片，其係與上述第1面相接而被設置； 控制器晶片，其係與上述第1面相接而被設置，能控制上述記憶體晶片； 密封構件，其係密封上述記憶體晶片和上述控制器晶片；及 壁構件，其係被設置在上述第1面，且被配置在上述記憶體晶片和上述控制器晶片之間，一端與上述第1面相接，其熱傳導率與上述密封構件不同。
  12. 如請求項11所記載之半導體封裝體，其中 在與上述基板垂直之第1方向中，上述壁構件之上述第1方向之長度大於上述控制器晶片之上述第1方向之長度，在上述基板以水平從上述控制器晶片朝向上述壁構件之第2方向正交的第3方向中，上述壁構件之上述第3方向之長度大於上述控制器晶片之上述第3方向之長度。
  13. 如請求項11或12之半導體封裝體，其中 上述壁構件之端部露出於上述密封構件之表面。
  14. 如請求項11或12之半導體封裝體，其中 上述密封構件密封上述壁構件。
  15. 如請求項11或12之半導體封裝體，其中 上述壁構件之熱傳導率低於上述密封構件之熱傳導率。
  16. 如請求項11或12之半導體封裝體，其中 上述壁構件之熱傳導率高於上述密封構件之熱傳導率。
  17. 如請求項11或12之半導體封裝體，其中 進一步具備第1構件，其係覆蓋上述控制器晶片之周圍之至少一部分，其熱傳導率低於上述密封構件。
  18. 如請求項11或12之半導體封裝體，其中 上述基板進一步具備安裝膜，其係將上述記憶體晶片和上述控制器晶片分別固定在上述第1面，其熱傳導率高於上述密封構件。
  19. 如請求項11或12之半導體封裝體，其中 上述基板具有內部配線，和在與上述第1面相反側之第2面上的焊球， 上述控制器晶片具有電極墊， 上述控制器晶片經由上述內部配線和上述電極墊被電性連接， 上述內部配線經上述焊球能與外部之電路基板電性連接。
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