TWI619227B - 用於高速低剖面記憶體封裝及插腳輸出設計的系統及方法 - Google Patents

用於高速低剖面記憶體封裝及插腳輸出設計的系統及方法 Download PDF

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TWI619227B
TWI619227B TW103117814A TW103117814A TWI619227B TW I619227 B TWI619227 B TW I619227B TW 103117814 A TW103117814 A TW 103117814A TW 103117814 A TW103117814 A TW 103117814A TW I619227 B TWI619227 B TW I619227B
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TW201436167A (zh
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安東尼 費
伊凡Ｒ 伯勒
楊志平
吳忠華
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蘋果公司
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Abstract

提供用於堆疊式半導體記憶體封裝之系統及方法。每一封裝可包括一積體電路(「IC」)封裝基板，該IC封裝基板能夠經由兩個通道將資料傳輸至堆疊在該封裝內之多個記憶體晶粒。每一通道可位於該IC封裝基板之一側上，且來自每一通道之信號可自該等記憶體晶粒之各別側投送至該等記憶體晶粒。

Description

用於高速低剖面記憶體封裝及插腳輸出設計的系統及方法
諸如快閃記憶體(例如，NAND快閃記憶體及NOR快閃記憶體)的各種類型之非揮發性記憶體(「NVM」)可用於大量儲存。舉例而言，消費型電子裝置(例如，攜帶型媒體播放器)使用快閃記憶體來儲存資料，包括音樂、視訊、影像及其他媒體或類型之資訊。消費型電子產業之目前趨勢涉及在較小裝置中利用更多NVM，從而產生對使資料儲存密度增加之創造性封裝解決方法的需要。
提供用於堆疊式半導體記憶體裝置之系統及方法。一堆疊式半導體記憶體封裝可包括一封裝基板及以一箭頭形堆疊配置之許多NVM晶粒。該NVM晶粒堆疊可用諸如(例如)一平台柵格陣列(「LGA」)之一表面黏著插槽安裝在該封裝基板上且以通信方式耦接至該封裝基板。該等NVM晶粒可以一箭頭形組態堆疊在該封裝內，其中一半的該等NVM晶粒在一第一方向上形成一階梯，且一半的該等NVM晶粒經旋轉180°且在一第二相反方向上繼續該堆疊。一記憶體裝置可經由藉由一印刷電路板(「PCB」)或印刷線路板(「PWB」)、該封裝基板及線接合提供之電連接而與該等NVM晶粒通信。
根據一些實施例，一新穎表面黏著插腳輸出設計可與上述堆疊 式半導體記憶體裝置一起使用。該插腳輸出設計可經組態以藉由(例如)以下操作來增強信號完整性：將載運高速信號之連接之差分對之間的距離減至最小、將線接合長度減至最小、避免高速信號在封裝內之交叉、在高速插腳之中心提供一接地(「GND」)插腳及分開高速插腳與低速插腳。根據另外實施例，高速插腳之置放可經最佳化以用於改良每一個別NVM封裝內或貫穿一整個NVM系統之信號完整性。該表面黏著插腳輸出設計可適合兩個通信通道，該兩個通信通道經組態以使得每一通道之對應插腳在旋轉180°後對稱地置放。
100‧‧‧系統
102‧‧‧主機
104‧‧‧非揮發性記憶體(NVM)封裝
106‧‧‧記憶體控制器
108‧‧‧揮發性記憶體
110‧‧‧主機介面
112a‧‧‧記憶體晶粒
112b‧‧‧記憶體晶粒
112n‧‧‧記憶體晶粒
114‧‧‧主機控制器
116‧‧‧通信通道
120‧‧‧處理器及/或微處理器
122‧‧‧揮發性記憶體
126‧‧‧共用內部匯流排
128a‧‧‧非揮發性記憶體(NVM)
128b‧‧‧非揮發性記憶體(NVM)
128n‧‧‧非揮發性記憶體(NVM)
134‧‧‧儲存組件
212a‧‧‧記憶體晶粒
212b‧‧‧記憶體晶粒
212c‧‧‧記憶體晶粒
212d‧‧‧記憶體晶粒
212e‧‧‧記憶體晶粒
212f‧‧‧記憶體晶粒
212g‧‧‧記憶體晶粒
212h‧‧‧記憶體晶粒
230‧‧‧平台柵格陣列(LGA)
232‧‧‧囊封劑
234‧‧‧基板
236‧‧‧電磁干擾(「EMI」)防護罩
238‧‧‧平台柵格陣列(LGA)之第一表面
240‧‧‧線接合線
260‧‧‧接合襯墊
262‧‧‧接合襯墊
304‧‧‧非揮發性記憶體(NVM)封裝
306‧‧‧記憶體控制器
312a‧‧‧記憶體晶粒
312b‧‧‧記憶體晶粒
312c‧‧‧記憶體晶粒
312d‧‧‧記憶體晶粒
312e‧‧‧記憶體晶粒
312f‧‧‧記憶體晶粒
312g‧‧‧記憶體晶粒
312h‧‧‧記憶體晶粒
316‧‧‧焊料凸塊
330‧‧‧平台柵格陣列(LGA)
332‧‧‧囊封劑
334‧‧‧基板
336‧‧‧電磁干擾(「EMI」)防護罩
338‧‧‧平台柵格陣列(LGA)之第一表面
340‧‧‧線接合線
350‧‧‧作用表面
352‧‧‧非作用表面
430‧‧‧平台柵格陣列(LGA)
450‧‧‧觸點
452‧‧‧觸點之第一子集
454‧‧‧觸點之第二子集
470‧‧‧旋轉對稱中心點
472‧‧‧中心軸線
530‧‧‧平台柵格陣列(LGA)
550‧‧‧觸點
552‧‧‧觸點之第一子集
554‧‧‧觸點之第二子集
570‧‧‧對稱軸線
600‧‧‧用於製造堆疊式半導體記憶體裝置之程序
601‧‧‧步驟
603‧‧‧步驟
605‧‧‧步驟
607‧‧‧步驟
609‧‧‧步驟
611‧‧‧步驟
在結合附圖考慮以下詳細描述後，本發明、本發明之性質及各種特徵之以上及其他態樣將變得更明顯，在附圖中，相同參考字元始終係指相同部件，且在附圖中：圖1為描繪根據各種實施例的包括主機及具有記憶體控制器之NVM封裝之說明性系統的圖；圖2為根據各種實施例的圖1之NVM封裝的截面圖；圖3為根據各種實施例之原始NVM封裝的截面圖；圖4為表面黏著封裝基板之仰視平面圖，其說明根據各種實施例之插腳輸出設計；圖5為表面黏著封裝基板之另一仰視平面圖，其說明根據各種實施例之插腳輸出設計；且圖6為根據各種實施例之用於製造堆疊式半導體記憶體裝置之程序的流程圖。
近年來，用於積體電路(「IC」)之表面黏著封裝已變得盛行，因為每一IC所需之互連的數目已增加超過傳統通孔式IC封裝(例如，雙列封裝(「DIP」)及插腳柵格陣列(「PGA」))之能力。表面黏著IC封 裝之實例包括球狀柵格陣列(「BGA」)及平台柵格陣列(「LGA」)。BGA或LGA可包括在封裝基板之一底面上配置於x-y平面中的一觸點陣列。該等觸點可焊接至一第二基板(諸如，PCB或PWB)之對應觸點。該第二基板可包括用於攜載來自IC封裝之信號及攜載信號至IC封裝的導電跡線。
本文中所揭示之例示性實施例可指IC封裝基板，為清楚起見，將IC封裝基板成為LGA。然而，熟習此項技術者可瞭解，在不脫離本發明之精神之情況下，任何合適類型之表面黏著封裝或通孔封裝可取代LGA。
詳言之，LGA之底面上之觸點可使用穿過封裝基板形成之導電介層孔佈線至頂面。LGA亦可包括封裝基板之頂面上的用於以通信方式耦接至安裝在LGA之上之一或多個IC的導電襯墊及/或跡線。在一些實施例中，線接合襯墊可形成於LGA之頂面上以用於以通信方式將該等觸點耦接至該(該等)IC。另外，一堆疊中之第一IC可以覆晶方式接合至封裝基板之頂面。在一些實施例中，IC封裝可為NVM封裝，且覆晶接合之IC可為用於NVM封裝之一記憶體控制器。
在一些實施例中，NVM封裝可包括安裝至一LGA之頂面的NVM晶粒之一堆疊。該堆疊可為箭頭形的，其中該等NVM晶粒之第一半部在一第一方向上形成一階梯，且該等NVM晶粒之第二半部繼續該堆疊且在相反方向上形成一階梯。此箭頭形的堆疊式晶粒佈局可在每一NVM晶粒之頂面上提供一暴露部分以用於收納線接合線。該等NVM晶粒之第一半部可自LGA的鄰近於該階梯之梯級之側而線接合至封裝基板，而該等NVM晶粒之第二半部可自(亦即，鄰近於第二階梯之梯級)之相反側而線接合至LGA。該第二梯級中之該等NVM晶粒可自第一半部中之該等NVM晶粒旋轉180°，以使得接合襯墊面向正確方向以收納線接合線。
形成於LGA之底面上之觸點可經配置以使得觸點之一第一集合(例如，一第一通道)可配置於封裝基板的最接近該第一階梯之梯級之側上，以將彼等觸點與頂面上之線接合襯墊之間的接線距離減至最小。觸點之該第一集合可專用於該等NVM晶粒之第一半部。類似地，觸點之一第二集合(例如，一第二通道)可配置於封裝基板的最接近該第二階梯之梯級之側上。觸點之該第二集合可專用於該等NVM晶粒之第二半部。將在下文關於圖4及圖5更詳細地論述各種觸點配置之進一步最佳化。
圖1為描繪系統100之圖，該系統包括主機102及NVM封裝104。主機102可與NVM封裝104通信，該NVM封裝可包括記憶體控制器106、主機介面110及具有對應NVM 128a至128n之記憶體晶粒112a至112n。主機102可為多種主機裝置及/或系統中之任一者，該等主機裝置及/或系統諸如攜帶型媒體播放器、蜂巢式電話、口袋大小之個人電腦、個人數位助理(「PDA」)、桌上型電腦、膝上型電腦及/或平板計算裝置。NVM封裝104可包括NVM 128a至128n(例如，在記憶體晶粒112a至112n中)且可為球狀柵格陣列封裝或其他合適類型之積體電路(「IC」)封裝。NVM封裝104可為主機102之部分及/或與主機102分離。舉例而言，主機102可為板級裝置，且NVM封裝104可為安裝在板級裝置上之記憶體子系統。在其他實施例中，NVM封裝104可用有線(例如，SATA)或無線(例如，BluetoothTM)介面耦接至主機102。
主機102可包括經組態以與NVM封裝104互動之主機控制器114。舉例而言，主機102可將各種存取請求(諸如，讀取操作、程式化操作及抹除操作)傳輸至NVM封裝104。主機控制器114可包括經組態以基於軟體指令及/或韌體指令之執行來執行操作的一或多個處理器及/或微處理器。另外及/或替代地，主機控制器114可包括經組態以執行各種操作的基於硬體之組件，諸如，特殊應用積體電路(「ASIC」)。主 機控制器114可根據在主機102與NVM封裝104之間共用之通信協定來格式化傳輸至NVM封裝104之資訊(例如，命令、資料)。
主機102可包括儲存組件134，該儲存組件可包括揮發性記憶體108。揮發性記憶體108可為多種揮發性記憶體類型(諸如，快取記憶體或RAM)中之任一者。主機102可使用揮發性記憶體108來執行記憶體操作及/或暫時地儲存自NMV封裝104讀取及/或寫入至NVM封裝之資料。舉例而言，揮發性記憶體108可暫時地儲存待發送至NVM封裝104或儲存自NVM封裝104接收之資料的記憶體操作之一佇列。
主機102可經由通信通道116與NVM封裝104通信。通信通道116可為固定的(例如，固定通信通道)、可拆卸的(例如，通用串列匯流排(USB)、串列進階技術(SATA))或無線的(例如，BluetoothTM)。與NVM封裝104之互動可包括提供存取請求及將資料(諸如，待程式化至記憶體晶粒112a至112n中之一或多者之資料)傳輸至NVM封裝104。通信通道116上之通信可在NVM封裝104之主機介面110處接收。主機介面110可為記憶體控制器106之部分及/或以通信方式連接至該記憶體控制器。在一些實施例中，例如，當記憶體控制器106係位於NVM封裝104外時，主機介面110亦可自NVM封裝104省略。
類似主機控制器114，記憶體控制器106可包括經組態以基於軟體指令及/或韌體指令之執行來執行操作的一或多個處理器及/或微處理器120。另外及/或替代地，記憶體控制器106可包括經組態以執行各種操作的基於硬體之組件，諸如ASIC。記憶體控制器106可執行多種操作，諸如執行由主機102起始之存取請求。
主機控制器114及記憶體控制器106可單獨地或組合地執行各種記憶體管理功能，諸如記憶體回收(garbage collection)及磨損調節。在記憶體控制器106經組態以執行至少一些記憶體管理功能之實施中，NVM封裝104可被稱為「被管NVM」(或對於NAND快閃記憶體，「被 管NAND」)。此可與「原始NVM」(或對於NAND快閃記憶體，「原始NAND」)形成對比，在原始NVM中，在NVM封裝104外的主機控制器114執行針對NVM封裝104之記憶體管理功能。
在一些實施例中，記憶體控制器106可與記憶體晶粒112a至112n併入至同一封裝中。在其他實施例中，記憶體控制器106可實體地位於單獨封裝中或與主機102位於同一封裝中。在一些實施例中，記憶體控制器106可省略，且通常由記憶體控制器106執行之所有記憶體管理功能(例如，記憶體回收及磨損調節)可由一主機控制器(例如，主機控制器114)來執行。
記憶體控制器106可包括揮發性記憶體122及NVM 124。揮發性記憶體122可為多種揮發性記憶體類型(諸如，快取記憶體或RAM)中之任一者。舉例而言，記憶體控制器106可使用揮發性記憶體122來執行存取請求及/或暫時地儲存自記憶體晶粒112a至112n中之NVM 128a至128n讀取及/或寫入至該等NVM之資料。另外，揮發性記憶體122可儲存韌體，且記憶體控制器106可使用該韌體來執行NVM封裝104上之操作(例如，讀取/程式化操作)。
記憶體控制器106可使用共用內部匯流排126來存取NVM 128a至128n，該等NVM可用於持續資料儲存。雖然在NVM封裝104中描繪了僅一個共用內部匯流排126，但NVM封裝可包括一個以上共用內部匯流排。每一內部匯流排可連接至多個(例如，2個、3個、4個、8個、32個等)記憶體晶粒，如關於記憶體晶粒112a至112n所描繪。記憶體晶粒112a至112n可以包括堆疊組態之多種組態實體地配置，且根據一些實施例，該等記憶體晶粒可為IC晶粒。根據一些實施例，以堆疊組態配置之記憶體晶粒112a至112n可用環氧樹脂導電跡線電耦接至記憶體控制器106。下文將關於圖3至圖5更詳細地論述此等實施例。
NVM 128a至128n可為多種NVM中之任一者，諸如，基於浮動閘 極或電荷捕獲技術之NAND快閃記憶體、NOR快閃記憶體、可抹除可程式化唯讀記憶體(「EPROM」)、電可抹除可程式化唯讀記憶體(「EEPROM」)、鐵電RAM(「FRAM」)、磁阻式RAM(「MRAM」)、相變記憶體(「PCM」)或其任何組合。
圖2為根據各種實施例之NVM封裝204的截面圖。NVM封裝204可包括記憶體晶粒212a至212h及LGA 230，如上文所揭示，NVM封裝可為任何合適封裝基板，諸如(例如)LGA、BGA或PGA。NVM封裝204及記憶體晶粒212a至212h可分別對應於圖1之NVM封裝104及記憶體晶粒112a至112h。NVM封裝204亦可包括囊封劑232及線接合線240。詳言之，NVM封裝204可為一「原始」NVM封裝，其不包括(例如)專用封裝內記憶體控制器，諸如記憶體控制器106。
上文提及之元件可安裝在基板234上，該基板可為諸如(例如)用於整個NVM系統(例如，圖1之系統100)或NVM系統之一部分之PCB或PWB的基板。基板234可包括促進系統之多個組件之間的連接性之導電引線。舉例而言，NVM封裝204之LGA 230可以通信方式耦接至基板234之觸點(未圖示)(例如，使用焊料)，且印刷導體(未圖示)可將記憶體晶粒212a至212h電耦接至一主機控制器(例如，圖1之主機控制器114)及/或其他系統組件。
為了防止在操作期間或在極端條件下對NVM封裝204之損害，LGA 230、囊封劑232及記憶體晶粒212a至212h可由具有類似熱膨脹係數之材料製成。舉例而言，記憶體晶粒212a至212h可為在Si晶圓上處理之積體電路，LGA 230可為由多層的織物(cloth)或纖維材料及一樹脂形成之層壓物，且囊封劑232可為塑膠、陶瓷或聚矽氧橡膠化合物。在其他實施例中，記憶體控制器206可在任何合適基板(例如，Ge、GaAs、InP)上處理，且囊封劑232可係為記憶體控制器206提供實體及環境保護之任何合適囊封劑材料。囊封劑232亦可經選擇以有 效地耗散來自記憶體晶粒212a至212h之熱。
NVM封裝204可完全或部分地囊封於電磁干擾(「EMI」)防護罩236中。EMI防護罩236可防止電磁輻射自NVM封裝204之組件發射。類似地，EMI防護罩236可防止藉由外部源發射之電磁及/或射頻干擾對NVM封裝204之組件的損害。一般而言，EMI防護罩236可充當法拉第籠(Faraday cage)，其可阻斷電場及/或電磁場之傳播。此外，EMI防護罩236可耦接至接地以便耗散電荷。如圖2所示，EMI防護罩236可為封閉NVM封裝204之一部分或全部之「罐」型EMI防護罩。根據一些實施例中，EMI防護罩236內之空間可為空(例如，填充以空氣)。在其他實施例中，EMI防護罩236內之空間可填充以合適介電材料。根據一些實施例，EMI防護罩236亦可使用標準塗佈技術(例如，物理氣相沈積(「PVD」)、化學氣相沈積(「CVD」)、旋塗等)而沈積於囊封劑232材料上方以作為保形傳導薄膜。
雖然本文中所描述之實施例參考特定半導體晶粒(例如，記憶體控制器及記憶體晶粒)，但熟習此項技術者將瞭解，半導體封裝(例如，NVM封裝204)可併有半導體晶粒之任何合適組合。舉例而言，封裝可包括連接至其他半導體晶粒(包括揮發性記憶體、非揮發性記憶體及/或一或多個類比電路晶粒)之一堆疊之一微處理器晶粒。
NVM封裝204可為堆疊式半導體晶粒組態之一實例，因為一或多個個別半導體晶片(例如，記憶體晶粒212a至212h)係以堆疊組件配置。在一些實施例中，記憶體晶粒212a至212h係使用任何合適黏著劑(例如，環氧樹脂)而附接至LGA 230之表面及彼此附接。堆疊式半導體晶粒組態可提供優於個別半導體晶片係側向地安裝在電路板上的電路板組態之許多優點。舉例而言，堆疊式組態中之晶粒具有較小「佔據面積」，此在需要小的總裝置尺寸之應用中可係有益的。事實上，因為封裝之佔據面積可非常接近於最大半導體晶片之尺寸，所以 NVM封裝204可稱為「晶片級封裝」。將記憶體晶粒堆疊亦使電子裝置之資料儲存密度增加，從而允許在相同實體空間中儲存更多資料。
雖然圖2中展示了八個記憶體晶粒，但熟習此項技術者將瞭解，依據空間、接線及/或結構限制，可將任何合適數目個記憶體晶粒併入至NVM封裝204中。
根據一些實施例，個別記憶體晶粒可使用線接合線240而以通信方式耦接至LGA 230。線接合程序可涉及將可撓性線自LGA 230之第一表面238上之接合襯墊260附接至形成於記憶體晶粒212a至212h上之接合襯墊262。該等線可由任何合適高導電性延性金屬(例如，Al、Au、Cu)製成。視所需外部連接之數目而定，可錯列LGA 230及/或記憶體晶粒212a至212h上之接合襯墊。錯列該等接合襯墊可使接合襯墊間距(接合襯墊之間的中心至中心距離)減小且允許比列式接合襯墊多的外部連接。錯列之接合襯墊可能需要LGA 230上之接合襯墊成階地以防止鄰近線之間的短接。
經由此線接合程序，記憶體晶粒212a至212h可以通信方式耦接至LGA 230及各種其他系統組件(例如，圖1之主機102)。線接合線240及LGA 230及基板234之電連接組合地可表示(例如)圖1之共用內部匯流排126。
為了形成圖2中所描繪之箭頭形結構，可將個別記憶體晶粒212a至212h堆疊且膠合在一起，其中相鄰記憶體晶粒相互稍微移位，從而在每一記憶體晶粒上產生暴露表面。記憶體晶粒212a至212h之暴露表面可包括用於耦接至線接合線240之接合襯墊262。如圖2中所描繪，一半的記憶體晶粒(亦即，記憶體晶粒212a至212d)可在第一方向上形成一階梯從而留下較接近NVM封裝204之第一邊緣之暴露表面，且一半的記憶體晶粒(亦即，記憶體晶粒212e至212h)可在第二方向上形成一階梯從而留下較接近NVM封裝204之與第一側對置之第二邊緣之暴 露表面。線接合線240可自NVM封裝204之第一側及第二側分別耦接至記憶體晶粒212a至212d及212e至212h。
圖3為根據各種實施例之NVM封裝304的截面圖。NVM封裝304可包括記憶體控制器306、記憶體晶粒312a至312h及LGA 330。NVM封裝304、記憶體控制器306、記憶體晶粒312a至312h可分別對應於(例如)圖1之NVM封裝104、記憶體控制器106及記憶體晶粒112a至112n。NVM封裝304亦可包括囊封劑332及線接合線340。以上元件可安裝在基板334上，該基板可為用於整個NVM系統(例如，圖1之系統100)或NVM系統之一部分之基板。因為NVM封裝304可包括記憶體控制器306，所以NVM封裝304可為「被管」NVM。
如圖3所示，記憶體控制器306可用任何合適黏著劑(例如，環氧樹脂)而接合至LGA 330，如上文所揭示，LGA可為諸如(例如)LGA、BGA或PGA的任何合適封裝基板。此外，記憶體控制器306可包括作用表面350及非作用表面352。在此等實施例中，記憶體控制器306之作用表面350可以覆晶方式接合至LGA 330之第一表面338。因此，記憶體控制器306可包括形成於作用表面350上之焊料凸塊316，該等焊料凸塊可用於將記憶體控制器306以覆晶方式接合至LGA 330之第一表面338。記憶體晶粒312a至312h可使用任何合適黏著劑(例如，環氧樹脂)安裝在記憶體控制器306之非作用表面352上。
一般而言，與其他接合方法(例如，線接合及TAB接合)相比，覆晶接合可使晶片至封裝互連長度減少，從而產生減少之電感且因此產生改良之高速信號完整性。焊料凸塊316可在晶圓處理期間添加至記憶體控制器晶粒。當記憶體控制器306與LGA 330經正確對準時，焊料凸塊316可回流從而在記憶體控制器306與LGA 330之第一表面338之間建立電連接。底部填充之黏著劑可添加於記憶體控制器306與LGA 330之間以使焊料凸塊316上之應力減少。
在圖中未示之其他實施例中，記憶體控制器306可以作用表面350避開LGA 330之第一表面338之方式耦接至LGA 330。在此等實施例中，記憶體控制器306可與記憶體晶粒312a至312h一起經由線接合線340而以通信方式耦接至LGA 330。因此，記憶體控制器306可包括暴露表面上的用於耦接至線接合線340之線接合襯墊。
圖4為根據一些實施例的LGA 430之下側的說明性平面圖。舉例而言，LGA 430可對應於圖2之LGA 230。觸點450之陣列可配置在LGA 430之底側上以用於在一NVM封裝(例如，NVM封裝204)與各種其他系統組件(例如，圖1之主機102)之間傳導信號。觸點450可包括適合與一NVM封裝中之一或多個晶粒通信之以下觸點：
‧Vcc：供應電壓(讀取)(×4)
‧VccQ：供應電壓(I/O)(×4)
‧Vpp：供應電壓(程式化/抹除)
‧Vref：參考電壓
‧GND：接地(×6)
‧PPM0-PPM1 IN：電力控制輸入通道0、1
‧PPM0-PPM1 OUT：電力控制輸出通道0、1
‧WE0#-WE1#：寫入啟用通道0、1
‧CLE0-CLE1：命令鎖存啟用通道0、1
‧ALE0-ALE1：位址鎖存啟用通道0、1
‧RE0-RE1：讀取啟用通道0、1
‧RE0#-RE1#：讀取啟用通道0、1
‧CE0#-CE7#：晶片啟用0-7
‧R/B0-R/B1：準備/忙通道0、1
‧DQS0-DQS1：資料佇列選通通道0、1
‧DQS0#-DQS1#：資料佇列選通通道0、1
‧IO(0-7)-0：資料I/O插腳0至7通道0
‧IO(0-7)-1：資料I/O插腳0至7通道1
可在x-y中以0至8延伸之列(y軸)座標及用於電力及接地插腳(該等插腳可配置在陣列之邊緣處)的OA至OF及用於信號插腳(該等插腳可相對於y軸大體上配置在陣列中心)的A至N延伸之行座標配置觸點450之陣列。熟習此項技術者將瞭解，插腳座標系統係任意的且可使用任何合適座標系統。
資料I/O插腳(例如，IO(0-7)-0及IO(0-7)-1)可用於將高速資料信號傳達至NVM封裝中之一或多個NVM晶粒(例如，圖1之記憶體晶粒112a至112n)。詳言之，資料I/O插腳之每一集合可表示控制器與NVM晶粒(例如，圖2之記憶體晶粒212a至212h中之一者)之間的8位元通信通道。舉例而言，針對上文關於圖2所揭示之原始NAND NVM封裝，控制器可為主機裝置之控制器(例如，圖1之主機控制器114)。另一方面，針對上文關於圖3所揭示之被管NAND NVM封裝，控制器可為NVM封裝之記憶體控制器(例如，圖3之記憶體控制器306)。
在高速應用中，將差分對之間的距離減至最小及使信號必須行進之總距離減少可幫助改良資料I/O插腳上之信號完整性。詳言之，可能需要差分對觸點之間的距離小於一預定臨限距離。因此，最佳插腳輸出設計可使攜載差分對信號之插腳之間的距離以及彼等信號行進之總距離減少。通常可用圖4中所顯示之插腳配置來滿足此等目的。
每一通道之資料I/O插腳可配置成圍繞GND插腳之環形。差分對信號在環形佈局中可經由相鄰資料I/O插腳攜載。舉例而言，以下插腳可攜載用於通道0之差分對信號：IO0-0及IO3-0；IO1-0及IO2-0；IO4-0及IO7-0；及IO5-0及IO6-0。相同配置(已作必要修正)可適用於用於通道1之資料I/O插腳。藉由減少每一差分對之插腳之間的接地偏移，將GND插腳併入於環形資料I/O插腳佈局內可進一步幫助改良信 號完整性。環形佈局亦可減少在NVM封裝內交叉高速信號載體之必要，從而減少載體之間的串擾且藉此改良信號完整性。
額外插腳可為環形資料I/O插腳佈局之部分，該等額外插腳包括(例如)RE0、RE1、RE0#、RE0#、DQS0#及DQS1#插腳。
資料I/O插腳之環形佈局可在y軸上相互偏移且配置於專用於非資料I/O活動之插腳列之間。舉例而言，GND、VCCQ、VCC、PPM0 IN及PPM1 IN插腳可沿著陣列之頂部及底部邊緣成列地配置，且環形資料I/O插腳佈局可配置於彼等列之間。可在環形佈局之間按對角列配置額外插腳(包括寫入啟用、晶片啟用、位址鎖存啟用、PMM OUT及命令鎖存啟用插腳)。
根據一些實施例，專用於每一通道之插腳可關於旋轉對稱中心點472對稱地置放。專用於每一通道之插腳可配置於穿過該旋轉對稱點繪製之中心軸線470之任一側上。因此，如圖4所示，資料I/O插腳IO(0-7)-0可對應於關於該旋轉對稱點反射之資料I/O插腳IO(0-7)-1。類似地，通道0之每一插腳在關於該對稱軸線反射時映射至通道1之對應插腳。
LGA 430可特別用於將信號投送至諸如(例如)圖2之NVM封裝204之堆疊式NVM封裝的NVM晶粒。因為一半的記憶體晶粒(亦即，記憶體晶粒212a至212d)可在第一方向上形成一階梯從而留下較接近NVM封裝204之第一邊緣之暴露表面，所以自專用於單一通道(例如，通道0)且配置於LGA 430之一部分上(例如，較接近NVM封裝204之第一邊緣)的觸點450之一子集投送之信號可以最小信號載體長度投送至記憶體晶粒212a至212d之接合襯墊。舉例而言，專用於通道0之觸點450之第一子集452可配置於LGA 430的最接近記憶體晶粒212a至212d之暴露表面之一部分上。專用於通道1之觸點450之第二子集454可配置於陣列之對置側上(例如，中心軸線470之對置側上)，且因此，最接近 記憶體晶粒212e至212h之暴露表面。因為記憶體晶粒212e至212h可自記憶體晶粒212a至212d旋轉180°且通道0可自通道1旋轉180°，所以每一通道可使用相同接線佈局(雖然相互旋轉180°)而佈線至記憶體晶粒之各別集合。
圖5為根據一些實施例的LGA 530之下側的說明性平面圖。舉例而言，LGA 530可對應於圖2之LGA 230。觸點550之陣列可配置在LGA 530之底側上以用於在一NVM封裝(例如，NVM封裝204)與各種其他系統組件(例如，圖1之主機102)之間傳導信號。觸點550可包括適合與一NVM封裝中之一或多個晶粒通信之以下觸點：
‧Vcc：供應電壓(讀取)(×4)
‧VccQ：供應電壓(I/O)(×4)
‧Vpp：供應電壓(程式化/抹除)
‧Vref：參考電壓
‧GND：接地(×6)
‧PPM0-PPM1 IN：電力控制輸入通道0、1
‧PPM0-PPM1 OUT：電力控制輸出通道0、1
‧WE0#-WE1#：寫入啟用通道0、1
‧CLE0-CLE1：命令鎖存啟用通道0、1
‧ALE0-ALE1：位址鎖存啟用通道0、1
‧RE0-RE1：讀取啟用通道0、1
‧RE0#-RE1#：讀取啟用通道0、1
‧CE0#-CE7#：晶片啟用0-7
‧R/B0-R/B1：準備/忙通道0、1
‧DQS0-DQS1：資料佇列選通通道0、1
‧DQS0#-DQS1#：資料佇列選通通道0、1
‧IO(0-7)-0：資料I/O插腳0至7通道0
‧IO(0-7)-1：資料I/O插腳0至7通道1
可在x-y中以0至8延伸之列(y軸)座標及用於電力及接地插腳的OA至OF及用於信號插腳的A至N延伸之行(x軸)座標配置觸點550之陣列。如圖5所示，電力及接地插腳係配置在陣列之邊緣處，且信號插腳係大體上配置在陣列之中心。熟習此項技術者將瞭解，插腳座標系統係任意的且可使用任何合適座標系統。
資料I/O插腳(IO(0-7)-0及IO(0-7)-1)可用於將高速資料信號傳達至NVM封裝中之一或多個NVM晶粒(例如，圖1之記憶體晶粒112a至112n)。詳言之，資料I/O插腳之每一集合可表示控制器與NVM晶粒(例如，圖2之記憶體晶粒212a至212h中之一者)之間的8位元通信通道。舉例而言，針對上文關於圖2所揭示之原始NANDNVM封裝，控制器可為主機裝置之控制器(例如，圖1之主機控制器114)。另一方面，針對上文關於圖3所揭示之被管NAND NVM封裝，控制器可為NVM封裝之記憶體控制器(例如，圖3之記憶體控制器306)。
圖5中所顯示之插腳配置可表示用於改良資料I/O插腳上之信號完整性之一替代實施例。
每一通道之資料I/O插腳可配置成圍繞GND插腳之C形。差分對信號在C形佈局中可經由相鄰資料I/O插腳攜載。舉例而言，以下插腳可攜載用於通道0之差分對信號：IO0-0及IO1-0；IO2-0及IO3-0；IO4-0及IO5-0；及IO6-0及IO7-0。相同配置(已作必要修正)適用於用於通道1之資料I/O插腳。藉由減少每一差分對之插腳之間的接地偏移，將GND插腳併入於C形資料I/O插腳佈局內可進一步幫助改良信號完整性。C形佈局亦可減少在NVM封裝內交叉高速信號載體之必要，從而減少載體之間的串擾且藉此改良信號完整性。
額外插腳可為C形資料I/O插腳佈局之部分，該等額外插腳包括 (例如)RE0、RE1、RE0#、RE1#、DQS0#及DQS1#插腳。
資料I/O插腳之C形佈局可在專用於非資料I/O活動之插腳列之間在y軸上居中。舉例而言，GND、VCCQ、VCC、PPM0 IN及PPM1 IN插腳可沿著陣列之頂部及底部邊緣按列配置，且C形資料I/O插腳佈局可在彼等列之間居中。可在邊緣列與C形佈局之間按列集合配置額外插腳(包括寫入啟用、晶片啟用、位址鎖存啟用、PMM OUT及命令鎖存啟用插腳)。
根據一些實施例，專用於每一通道之插腳可關於y軸定向之對稱中心軸線對稱地置放。專用於每一通道之插腳可配置在對稱軸線570之任一側，以使得第二LGA可沿著對稱軸線倒置旋轉。結果，第二LGA之插腳可與LGA 530之插腳一致。因此，如圖5所示，資料I/O插腳IO(0-7)-0可對應於關於該對稱軸線反射之資料I/O插腳IO(0-7)-1。類似地，通道0之每一插腳在關於該對稱軸線反射時映射至通道1之對應插腳。
LGA 530可供一堆疊式NVM封裝(諸如(例如)圖2之NVM封裝204)使用。如上所述，專用於通道0且配置在對稱軸線570之一側的觸點550之第一子集552可以最小信號載體距離佈線，從而以通信方式耦接第一子集552與(例如)記憶體晶粒212a至212d之暴露表面上之接合襯墊。類似地，專用於通道1且配置在對稱軸線570之另一側的觸點之第二子集554可以最小信號載體距離佈線，從而以通信方式耦接第二子集554與記憶體晶粒212e至212h之暴露表面上之接合襯墊。因為觸點550可能並非關於一點旋轉對稱，所以NVM封裝204內之接線可能必須針對每一通道更改以考慮自記憶體晶粒212e至212h旋轉180°之記憶體晶粒212a至212d。
圖6為根據一些實施例之用於製造堆疊式半導體記憶體裝置之程序600的流程圖。在步驟601，可提供一IC封裝基板(例如，圖2之LGA 230)。LGA之底面可包括用於以通信方式耦接LGA與一系統基板(例如，圖2之基板234)的一觸點陣列。舉例而言，可如上文關於圖4及圖5所描述地配置觸點之陣列。因此，第一通信通道可設置在LGA之底面之第一部分上，且第二通信通道可設置在LGA之底面之第二部分上。此外，LGA可包括用於將LGA之底面上之觸點佈線至LGA之頂面上之導電特徵(例如，接合襯墊)之任何合適介層孔及/或跡線。
接下來，在步驟603，可視情況將一記憶體控制器(例如，圖3之記憶體控制器306)實體耦接至LGA。在一些實施例中，記憶體控制器可以覆晶組態耦接至封裝基板。在此等實施例中，記憶體控制器之作用表面可包括允許記憶體控制器與LGA之間的直接連接之許多焊料凸塊。在其他實施例中，記憶體控制器可線接合至設置於LGA之第一表面上之接合襯墊。在另外其他實施例中，可完全省略記憶體控制器，以使得堆疊式半導體記憶體裝置為原始NVM裝置。
在步驟605，可用一合適黏著劑將NVM晶粒(例如，記憶體晶粒212a至212h)之一堆疊以一箭頭形組態耦接至LGA之頂面或記憶體控制器。在一些實施例中，可在每一記憶體晶粒之間引入環氧樹脂。可接著將該堆疊配置成箭頭形堆疊。最後，可固化環氧樹脂以使記憶體晶粒之該堆疊牢固。接著可使用任何合適方法將記憶體晶粒212a至212h之堆疊附接至LGA 230。根據一些實施例，記憶體晶粒212a至212h之堆疊可在該堆疊形成之同時以環氧樹脂黏接至LGA 230。
依據空間、接線及/或結構限制，可將任何數目個NVM晶粒包括於該堆疊中。每一NVM晶粒可用一合適黏著劑實體耦接至一相鄰晶粒，且該等晶粒可經配置，以使得該等NVM晶粒之第一半部在第一方向上形成一階梯且該等NVM晶粒之第二半部被旋轉180°且在第二方向上形成一階梯。所得箭頭形堆疊可在每一NVM晶粒上提供一暴露表面，接合襯墊可設置於該暴露表面上。用於沈積導電材料及自一 表面移除導電材料之任何合適技術可用來提供接合襯墊。
在步驟607，可將設置於該箭頭形堆疊之第一半部中之NVM晶粒之邊緣上的接合襯墊電耦接至LGA的與第一通信通道相關聯之觸點之一第一子集(例如，圖5之第一子集552)。在一些實施例中，如上文關於圖2所描述，線接合線可用於此用途。類似地，在步驟609，可將設置於該箭頭形堆疊之第二半部中之NVM晶粒之邊緣上的接合襯墊電耦接至LGA的與第二通信通道相關聯之觸點之一第二子集(例如，圖5之子集554)。
接下來，在步驟611，可視情況將一EMI防護罩(例如，圖3之EMI防護罩236)耦接至該堆疊式半導體記憶體封裝。該EMI防護罩可為可覆蓋該堆疊式半導體記憶體封裝之全部或部分的中空罐型EMI防護罩。在一些實施例中，該EMI防護罩與該記憶體裝置之組件之間的空間可填充以一介電材料。在彼等實施例中，一導電薄膜可沈積在該介電材料上從而形成該EMI防護罩。為了耗散電荷，可將該EMI防護罩接線至接地(例如，一附近電路板上之一接地插腳)。
將理解，圖6之程序600中所示之該等步驟僅為說明性的，且可修改或省略現有步驟，可添加額外步驟，且可更改特定步驟之次序。
雖然已描述了用於堆疊式半導體記憶體裝置之系統及方法，但應理解，在不脫離本發明之精神及範疇之情況下，可對該等系統及該等方法作出許多改變。一般熟習此項技術者所看到的對所主張標的之非實質改變(未知的或稍後發明的)在申請專利範圍之範疇內被明確視為等效的。因此，一般熟習此項技術者現在已知或稍後知道的明顯替換經界定為在所定義元件之範疇內。
為了說明而非限制之目的，呈現本發明之所描述實施例。
100‧‧‧系統
102‧‧‧主機
104‧‧‧非揮發性記憶體(NVM)封裝
106‧‧‧記憶體控制器
108‧‧‧揮發性記憶體
110‧‧‧主機介面
112a‧‧‧記憶體晶粒
112b‧‧‧記憶體晶粒
112n‧‧‧記憶體晶粒
114‧‧‧主機控制器
116‧‧‧通信通道
120‧‧‧處理器及/或微處理器
122‧‧‧揮發性記憶體
126‧‧‧共用內部匯流排
128a‧‧‧非揮發性記憶體(NVM)
128b‧‧‧非揮發性記憶體(NVM)
128n‧‧‧非揮發性記憶體(NVM)
134‧‧‧儲存組件

Claims (36)

  1. 一種堆疊式半導體封裝，其包含：一積體電路(「IC」)封裝基板，其包含形成於該IC封裝基板之一底面上的複數個導電觸點，其中該複數個導電觸點進一步包含複數個資料I/O觸點及複數個接地(「GND」)觸點；一箭頭形晶粒堆疊，其耦接至該IC封裝基板的與該底面對置之一頂面，該箭頭形晶粒堆疊包含：一堆疊式半導體晶粒之第一子集，其具有較接近該IC封裝基板之一第一邊緣之暴露表面；及一堆疊式半導體晶粒之第二子集，其具有較接近該IC封裝基板之一第二邊緣之暴露表面；其中該複數個導電觸點之一第一子集係以通信方式耦接至該堆疊式半導體晶粒之第一子集之該等暴露表面，且其中該複數個導電觸點之一第二子集係以通信方式耦接至該堆疊式半導體晶粒之第二子集之該等暴露表面，其中該複數個GND觸點僅兩個GND觸點係由該等資料I/O觸點圍繞，該等資料I/O觸點與該複數個導電觸點之該第一子集及該第二子集之各別一者相關聯。
  2. 如請求項1之堆疊式半導體封裝，其進一步包含延伸通過該IC封裝基板之複數個電性導電介層孔，其將該複數個導電觸點電耦接至配置於該IC封裝基板之該頂面之複數個電接合襯墊。
  3. 如請求項2之堆疊式半導體封裝，其中：對應至一第一通信通道之該複數個導電觸點之該第一子集係配置在該IC封裝基板之該底面之一第一側；且對應至一第二通信通道之該複數個導電觸點之該第二子集係配置在該IC封裝基板之該底面之一第二側。
  4. 如請求項1之堆疊式半導體封裝，其中該箭頭形晶粒堆疊包含非揮發性記憶體晶粒。
  5. 如請求項1之堆疊式半導體封裝，其進一步包含耦接在該箭頭形晶粒堆疊及該IC封裝基板之該頂面之一記憶體控制器晶粒。
  6. 如請求項5之堆疊式半導體封裝，其中該記憶體控制器晶粒係覆晶式接合至該IC封裝基板之該頂面。
  7. 如請求項5之堆疊式半導體封裝，其中該記憶體控制器晶粒係線接合至形成在該IC封裝基板之該頂面上之電接合襯墊。
  8. 如請求項1之堆疊式半導體封裝，其中：該堆疊式半導體晶粒之第一子集在一第一方向形成一階梯；該堆疊式半導體晶粒之第二子集在與該第一方向對置的一第二方向形成一階梯；該堆疊式半導體晶粒之第二子集係堆疊在該堆疊式半導體晶粒之第一子集的頂部；且該堆疊式半導體晶粒之第二子集之每一半導體晶粒自該堆疊式半導體晶粒之第一子集之每一晶粒旋轉180°。
  9. 如請求項1之堆疊式半導體封裝，其中該IC封裝基板包含一平台柵格陣列(「LGA」)、一球狀柵格陣列(「BGA」)及一插腳柵格陣列(「PGA」)之一者。
  10. 一種用於製造一堆疊式半導體封裝之方法，該方法包含：提供一積體電路(「IC」)封裝基板，該積體電路封裝基板包含形成於該IC封裝基板之一底面上的複數個導電觸點，其中該複數個導電觸點進一步包含複數個資料I/O觸點及複數個接地(「GND」)觸點；在一箭頭形堆疊中實體地耦接一記憶體晶粒之堆疊至該積體電路封裝基板之一頂面； 將在該箭頭形堆疊之一第一半中提供在該等記憶體晶粒之暴露表面上的接合襯墊電耦合至與一第一通信通道相關聯之該IC封裝基板之接點；及將在該箭頭形堆疊之一第二半中提供在該等記憶體晶粒之暴露表面上的接合襯墊電耦合至與一第二通信通道相關聯之該IC封裝基板之接點，其中該複數個GND觸點僅兩個GND觸點係由該等資料I/O觸點圍繞，該等資料I/O觸點與該複數個導電觸點之該第一子集及該第二子集之各別一者相關聯。
  11. 如請求項10之方法，其進一步包含：形成通過該IC封裝基板之複數個電性導電介層孔(via)，該複數個電性導電介層孔自該IC封裝基板之該頂面延伸至該IC封裝基板之一底面。
  12. 如請求項11之方法，其進一步包含形成在該IC封裝基板之該底面上之一電觸點陣列，該電觸點陣列以通信方式使用該複數個電性導電介層孔以耦接至該等接合襯墊。
  13. 如請求項12之方法，其中形成在該IC封裝基板之該底面之一第一側上的該電觸點陣列之一第一子集係對應於該第一通信通道，且其中形成在該IC封裝基板之該底面之一第二側上的該電觸點陣列之一第二子集係對應於該第二通信通道。
  14. 如請求項10之方法，其進一步包含將一IC晶粒耦接在該IC封裝基板之該頂面及該記憶體晶粒之堆疊間。
  15. 如請求項14之方法，其中該耦接該IC晶粒包含將該IC晶粒覆晶式接合至該IC封裝基板之該頂面。
  16. 如請求項14之方法，其中該耦接該IC晶粒包含將該IC晶粒線接合至形成在該IC封裝基板之該頂面上之接合襯墊。
  17. 如請求項10之方法，其進一步包含將一電磁干擾(「EMI」)防護 罩耦接至該IC封裝基板。
  18. 如請求項17之方法，其進一步包含以介電材料填充在該EMI防護罩及該IC封裝基板之間的空間。
  19. 一種積體電路(「IC」)封裝基板，其包含包括一觸點陣列之一底面，該觸點陣列包含複數個資料I/O觸點，其中：該複數個資料I/O觸點之一第一子集形成配置在該底面之一第一部分之一第一C形(C-shaped)佈局；該複數個資料I/O觸點之一第二子集形成配置在該底面之一第二部分之一第二C形佈局；且該第一部分及該第二部分關於一中央軸係反射地對稱。
  20. 如請求項19之IC封裝基板，該觸點陣列進一步包含複數個接地(「GND」)觸點，其中該複數個GND觸點之至少一GND觸點係由該複數個資料I/O觸點之該第一子集及該第二子集的每一者的資料I/O觸點圍繞。
  21. 如請求項19之IC封裝基板，該觸點陣列進一步包含複數個資料佇列選通(「DQS」)觸點，其中該複數個DQS觸點之至少一DQS觸點係由該複數個資料I/O觸點之該第一子集及該第二子集的每一者的資料I/O觸點圍繞。
  22. 如請求項19之IC封裝基板，其中該複數個資料I/O觸點之該第一子集包含一第一通信通道，且該複數個資料I/O觸點之該第二子集包含一第二通信通道。
  23. 如請求項22之IC封裝基板，該觸點陣列進一步包含複數個晶片啟用(「CE」)觸點，其中該複數個CE觸點之一第一子集與該複數個CE觸點之一第二子集關於對稱軸係反射地對稱。
  24. 如請求項23之IC封裝基板，其中該等CE觸點之該第一子集對通過該第一通信通道之一發送信號及一接收信號之至少一者啟用 一第一子集之記憶體晶粒，且其中該等CE觸點之該第二子集對通過該第二通信通道之一發送信號及一接收信號之至少一者啟用一第二子集之記憶體晶粒。
  25. 如請求項19之IC封裝基板，該觸點陣列進一步包含沿著該底面之頂部及底部邊緣按列配置之複數個非資料I/O觸點，其中該第一C形佈局及該第二C形佈局配置於該等列之間。
  26. 如請求項25之IC封裝基板，其中該複數個非資料I/O觸點係在該等列中之唯一觸點。
  27. 一種積體電路(「IC」)封裝基板，其包含包括一觸點陣列之一底面，該觸點陣列包含複數個資料I/O觸點，其中：該複數個資料I/O觸點之一第一子集形成配置在該底面之一第一側之一第一C形(C-shaped)佈局；該複數個資料I/O觸點之一第二子集形成配置在該底面之一第二側之一第二C形佈局；且該第一部分及該第二部分關於一中央軸係反射地對稱，其中該觸點陣列進一步包含複數個接地(「GND」)觸點，其中僅該複數個GND觸點之兩個GND觸點係由該複數個資料I/O觸點之該第一子集及該第二子集的資料I/O觸點圍繞。
  28. 如請求項27之IC封裝基板，其中資料I/O觸點之該第一子集包含複數個差分對資料觸點、複數個讀取啟用觸點、複數個資料佇列選通(「DQS」)觸點及該僅兩個GND觸點之一者，及其中資料I/O觸點之該第二子集包含複數個差分對資料觸點、複數個讀取啟用觸點、複數個資料佇列選通(「DQS」)觸點及該僅兩個GND觸點之一者。
  29. 如請求項28之IC封裝基板，其中在該第一C形佈局中，該GND觸點相鄰該等讀取啟用觸點之各者與該DQS觸點之各者，及在該第 二C形佈局中，該GND觸點相鄰該等讀取啟用觸點之各者與該DQS觸點之各者。
  30. 如請求項27之IC封裝基板，該觸點陣列進一步包含複數個寫入啟用(「WE」)觸點，該複數個WE觸點經配置在該第一環形佈局及該第二環形佈局之間之兩個平行對角軸。
  31. 如請求項30之IC封裝基板，其中該等WE觸點之一第一子集經配置於相鄰該第一C形佈局之該兩個平行對角軸之一第一者中，且其中該等WE觸點之一第二子集經配置於相鄰該第二C形佈局之該兩個平行對角軸之一第二者中。
  32. 如請求項31之IC封裝基板，其中該等WE觸點之該第一子集經關於位於該中央軸之對稱點旋轉180°後映射至對應之該複數個WE觸點之該第二子集之WE觸點。
  33. 一種半導體封裝，其包含：一積體電路(「IC」)封裝基板，其包含形成於該IC封裝基板之一底面上的複數個導電觸點，其中該複數個導電觸點進一步包含複數個資料I/O觸點及複數個接地(「GND」)觸點；其中該複數個GND觸點僅兩個GND觸點係由該等資料I/O觸點圍繞，該等資料I/O觸點與該複數個導電觸點之子集之一第一C形佈局及一第二C形佈局之一對應者相關聯。
  34. 如請求項33之半導體封裝，其中該僅兩個GND觸點之一第一者與該第一C形佈局相關聯，且該僅兩個GND觸點之一第二者與該第二C形佈局相關聯。
  35. 如請求項33之半導體封裝，其中對應至一第一通信通道之該第一C形佈局係配置在該IC封裝基板之該底面之一第一側；且對應至一第二通信通道之該第二C形佈局係配置在該IC封裝基 板之該底面之一第二側。
  36. 如請求項33之半導體封裝，其中該IC封裝基板包含一平台柵格陣列(「LGA」)、一球狀柵格陣列(「BGA」)及一插腳柵格陣列(「PGA」)之一者。
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