JP6839395B2 - 半導体演算装置 - Google Patents
半導体演算装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 52
- 230000000149 penetrating effect Effects 0.000 claims description 28
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- 239000011229 interlayer Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 14
- 238000013500 data storage Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 238000013528 artificial neural network Methods 0.000 description 7
- 230000035515 penetration Effects 0.000 description 7
- 230000010354 integration Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000013135 deep learning Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- 238000013527 convolutional neural network Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1(A)及び(B)は、本発明に係る半導体演算装置の第1の実施形態の概略の平面図及び断面図を示す。同図(A)、(B)において、本実施形態の半導体演算装置10は、各々異なる第1、第2、第3の素子層に実装される演算器111〜113の各々が縦方向の寸法Lv、横方向の寸法Lhの方形領域内に重なり配置され、かつ、2以上の演算器111〜113がそれぞれ第1、第2、第3の同一層内で二次元アレイ状に配置された素子層を有する。以上は、素子層数が3の場合であるが、更に、素子層数をAと拡張して演算器の対角線方向に沿った演算器の断面図を示せば、図1(B)に121〜12Aで模式的に示すように素子層はA層(ただし、Aは2以上の自然数)積層されている。なお、図示の便宜上、図1(A)は3つの素子層121〜123が積層された状態(A=3の場合)の平面図を模式的に示している。また、図1(A)は図示の便宜上、一例として同一素子層に9つの演算器が二次元アレイ状に配置された平面図を模式的に示しており、演算器111は素子層121に二次元アレイ状に配置された9つの演算器、演算器112は素子層122に二次元アレイ状に配置された9つの演算器、演算器113は素子層123に二次元アレイ状に配置された9つの演算器を示している。
次に、本発明に係る半導体演算装置の第2の実施形態として、例えば深層学習における畳み込み演算に用いる例について説明する。
111〜113、50、502、5021〜502N 演算器
12、121〜12A 素子層
13、131〜13A、201、202 層間配線
14 演算器の対角線
30、301、302 ロジックセル
31 素子層貫通用配線領域
33a 高電圧側電源用配線層
33b 低電圧側電源用配線層
34a、34b ゲート電極
35 第1の不純物拡散層
36 第2の不純物拡散層
37 出力配線層
38 素子層貫通配線
39 第2層配線層
40 第1層配線層
41 素子分離領域
42 ゲート絶縁膜
111 第1の演算器
112 第2の演算器
121 第1の素子層
122 第2の素子層
203 同一の素子層の演算器間を結ぶ配線
311、312、401、402 素子層貫通用配線領域
403 素子層111及び112の重なる位置にある素子層貫通用配線領域
500 畳み込み演算装置
501 入力セレクタ
503 ネットワーク
504 出力セレクタ
5121〜5123 重み係数格納用キャッシュメモリ
5131〜5133 バッファメモリ
5141〜5143 セレクタ
5151〜5153 乗算器
516 入力層データ格納用レジスタファイル
5171〜5173 加算器
5181 第1層計算用レジスタ
5182 第2層計算用レジスタ
5191 第1層計算結果格納用レジスタ
5192 第2層計算結果格納用レジスタ
520 出力セレクタ
Claims (6)
- 演算器が縦方向の寸法Lv、横方向の寸法Lhの方形領域内に配置され、かつ、2以上の前記演算器が同一層内で二次元アレイ状に配置された素子層が複数積層されており、
前記複数の素子層の積層方向に相隣る素子層において、それぞれ配置位置が重なる前記演算器同士が、互いに前記演算器の一つの対角線方向に相対的にずれて配置されるように前記複数の素子層を積層するとともに、前記相隣る素子層においてそれぞれ配置位置が重なる前記演算器同士を配線により接続し、層間の前記配線を通信路として用いることを特徴とする半導体演算装置。 - 前記複数の素子層は、少なくとも(m/4)層(ただし、mはメニーコアプロセッサにおいて、近接する演算器と1タイムスロットで同時通信可能な演算器の数)積層されており、積層方向に相隣る素子層それぞれに配置された前記演算器は、互いに素子層表面において縦方向にLv/(m/4)、横方向にLh/(m/4)の各寸法だけ相対的にずれて配置されていることを特徴とする請求項1記載の半導体演算装置。
- 前記複数の素子層のうち、それぞれ3以上の異なる素子層の配置位置が重なる各演算器の、配線領域位置が重なる配線領域同士を直線状に貫通して接続する貫通配線を有し、前記貫通配線を通信路として使用することを特徴とする請求項1又は2記載の半導体演算装置。
- 前記演算器を構成するロジックセルの中に、前記複数の素子層の中間配線層の配線ピッチのn倍(ただし、nは1以上の自然数)の幅の素子層貫通用配線領域が、前記横方向に帯状に形成されていることを特徴とする請求項1乃至3のうちいずれか一項記載の半導体演算装置。
- 前記素子層貫通用配線領域は、前記複数の素子層の互いに同じ位置に前記横方向に帯状に形成されていることを特徴とする請求項4記載の半導体演算装置。
- 前記素子層貫通用配線領域は、前記ロジックセルの電源用配線領域に隣接して平行に形成されていることを特徴とする請求項4又は5記載の半導体演算装置。
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JP2016107757 | 2016-05-30 | ||
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PCT/JP2017/019176 WO2017208901A1 (ja) | 2016-05-30 | 2017-05-23 | 半導体演算装置 |
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US8399973B2 (en) * | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
US8258619B2 (en) * | 2009-11-12 | 2012-09-04 | International Business Machines Corporation | Integrated circuit die stacks with translationally compatible vias |
US9087846B2 (en) * | 2013-03-13 | 2015-07-21 | Apple Inc. | Systems and methods for high-speed, low-profile memory packages and pinout designs |
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