TWI722300B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI722300B
TWI722300B TW107124452A TW107124452A TWI722300B TW I722300 B TWI722300 B TW I722300B TW 107124452 A TW107124452 A TW 107124452A TW 107124452 A TW107124452 A TW 107124452A TW I722300 B TWI722300 B TW I722300B
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substrate
semiconductor
layer
ground
holes
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TW107124452A
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TW201916315A (zh
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足利寛
木村直樹
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種不易產生ESD擊穿之半導體裝置。 根據實施形態，半導體裝置具備第1基板、半導體晶片、及絕緣層。第1基板具備複數個通孔。半導體晶片覆晶安裝於第1基板之第1面。絕緣層覆蓋第1基板之第1面與半導體晶片。通孔具備：複數個第1通孔，其等電性連接於半導體晶片；及至少1個第2通孔，其未電性連接於半導體晶片。絕緣層覆蓋第1通孔，不覆蓋第2通孔。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
作為大容量記憶裝置，近年來，代替HDD(Hard Disk Drive，硬盤驅動器)而開發了SSD(Solid State Drive，固態驅動器)。SSD包括NAND(Not AND，與非)型快閃記憶體等非揮發性半導體記憶體及其控制器等。控制器包括半導體晶片及晶片基板，半導體晶片係利用打線接合而安裝於晶片基板。晶片基板與快閃記憶體一起安裝於SSD基板。
近年來，代替打線接合而開發了覆晶安裝技術，於控制器中，半導體晶片亦使用覆晶技術安裝於晶片基板。所謂覆晶安裝，係指於半導體晶片之表面排列被稱為凸塊之微小之金屬突起(焊料等)狀之端子，以凸塊與晶片基板接觸之方式將半導體晶片載置於晶片基板，使凸塊熔融而使半導體晶片接合於晶片基板。由利用打線接合安裝設置之樹脂材料形成之密封部(亦稱為包覆成形)有時於覆晶安裝中省略。覆晶安裝不僅限定於SSD之控制器用之半導體晶片，亦用於廣泛之領域。
先前之覆晶安裝之半導體裝置容易產生由靜電所致之ESD(Electro-Static Discharge，靜電放電)擊穿。再者，ESD擊穿不限定於SSD之控制器，於利用覆晶安裝之整個半導體裝置中都會產生。
本發明之實施形態提供一種不易產生ESD擊穿之半導體裝置。
根據實施形態，半導體裝置具備第1基板、半導體晶片、及絕緣層。第1基板具備複數個通孔。半導體晶片覆晶安裝於第1基板之第1面。絕緣層覆蓋第1基板之第1面與半導體晶片。通孔具備：複數個第1通孔，其等電性連接於半導體晶片；及至少1個第2通孔，其未電性連接於半導體晶片。絕緣層覆蓋第1通孔，不覆蓋第2通孔。
[相關申請]
本申請享有以日本專利申請案2017-179056號(申請日：2017年9月19日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之所有內容。
以下，參照圖式對實施形態進行說明。再者，揭示只不過為一例，並不由以下之實施形態中所記載之內容來限定發明。對幾個要素標註複數個名稱，該等名稱之例只不過為例示，並不否定對該等要素標註其他名稱。又，關於未標註複數個名稱之要素，亦可標註其他名稱而表達。業者容易想到之變化當然包含於揭示之範圍中。為了使說明更明確，於圖式中，亦存在將各部分之尺寸、厚度、平面尺寸，形狀等相對於實際之實施態樣變更而模式性地表示之情況。又，有時於圖式相互間亦包含相互之尺寸之關係或比率不同之部分。於複數個圖式中，亦存在對所對應之要素標註相同之參照數字，而省略詳細之說明之情況。 [第1實施形態]
利用覆晶安裝之半導體裝置之例有各種，此處，作為一例對SSD進行說明。圖1係表示實施形態之SSD之構成之一例之方塊電路圖。如圖1所示，SSD10具備控制器20、作為非揮發性半導體記憶體之快閃記憶體32-1、32-2(亦有時稱為32)、DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)54、電源電路58、主機介面(主機I/F)52等。
作為主機裝置之外部設備50連接於主機I/F52。外部設備50進行對快閃記憶體32之資料之寫入及讀出。外部設備50例如有個人電腦或CPU(Central Processing Unit，中央處理單元)核心等。作為與外部設備50之介面，例如亦可使用PCI Express(註冊商標)、SAS(Serial Attached SCSI)(註冊商標)、SATA(Serial Advanced Technology Attachment)(註冊商標)、NVMe(Non Volatile Memory Express)(註冊商標)、USB(Universal Serial Bus)(註冊商標)等標準。
主機I/F52連接於控制器20。於控制器20亦連接有快閃記憶體32、DRAM54、電源電路58。快閃記憶體32之數量並不限定為2個，亦可設置多數。DRAM54為揮發性記憶體之一例，使用於快閃記憶體之管理資訊之保管或資料之快取等。亦可代替DRAM54而使用SRAM(Static Random Access Memory，靜態隨機存取記憶體)等其他揮發性記憶體。電源電路58例如為DC-DC(Direct Current- Direct Current，直流-直流)轉換器，從自外部設備50供給之電源產生SSD10所需要之各種電壓。雖未圖示，但控制器20具備DRAM I/F、NAND I/F，且經由DRAM I/F連接於DRAM54，經由NAND I/F連接於快閃記憶體32-1、32-2。
圖2(a)係表示SSD10之外觀之一例之俯視圖，圖2(b)係表示控制器20之外觀之一例之立體圖。圖3係表示控制器20之附近之剖面構造之一例之剖視圖。圖4(a)係表示控制器20之構造之一例之俯視圖，圖4(b)係自SSD10之基板側觀察控制器20之基板之俯視圖，圖4(c)係自控制器20側觀察控制器20之基板之俯視圖。
如圖3所示，大致矩形形狀之第1基板(SSD基板、印刷配線板：PWB(Printed Wiring Board)、裸板、原始基板)12為具有第1面12a(第1表面、安裝面、第1基板面、上表面)、及與第1面12a相反側之背面12b(下表面、底面)之扁平之板狀零件。
第1基板12為將環氧樹脂等合成樹脂重疊而形成之多層構造，例如為8層構造。於各層之表面，形成有各種各樣形狀之配線圖案。例如，形成有進行信號之收發之信號層、接地層、電源層等。於圖3之情形時，為了簡化圖示而表示了3層構造(第1層12g、第2層12h、第3層12i)。接地層42介置於第1層12g與第2層12h之間。
各層之配線圖案之種類能夠適當變更，例如，不同種類之配線圖案亦可存在於相同層，亦可為不存在配線圖案之層。
第1基板12亦可為單面基板(1層基板)或兩面基板(2層基板)。於第1基板12為單面基板之情形時，於第1面12a形成有接地圖案或信號圖案、電源圖案等。於第1基板12為兩面基板之情形時，於第1面12a與背面12b將接地圖案或信號圖案、電源圖案等適當分配形成。
於第1基板12之例如側面12d，具備用以與外部設備，例如個人電腦或CPU核心等連接之連接器14。
形成於第1基板12之內層之接地層42或省略了圖示之信號層及電源層電性連接於連接器14之特定之端子接腳14b，且與外部設備連接。再者，連接器14例如於自中央位置偏離之位置形成有狹縫14c，與設置於外部設備之突起(未圖示)等嵌合。藉此，可防止SSD10正面背面相反地安裝於外部設備。
於第1基板12之第1面12a之表面形成有接地線(未圖示)，該接地線亦可電性連接於連接器14之特定之端子接腳14b，且與外部設備連接。亦可將接地層42之一部分與該接地線使用第1基板12之內部配線等電性連接。
接地層42或接地線經由端子接腳14b而電性連接於外部設備且接地。再者，亦可構成為傳遞(熱輸送)至接地層42或接地線之熱經由端子接腳14b而傳遞(熱輸送)至外部設備之殼體側，進行於半導體裝置10中產生之熱之散熱。
一般而言，於多層配線中，形成有作為將下層之配線與上層之配線電性連接之連接區域之通孔(Via)。通孔係對層間絕緣膜進行蝕刻而將導孔(via hole)開口，將該導孔利用金屬材料嵌埋而形成。於第1基板12之第1層12g，形成有複數個將第1面12a與形成於第2層12h上之接地層42電性地(亦熱地)連接之第1通孔40。再者，於圖3中雖省略了圖示，但亦形成有用以進行與信號層或電源層電性連接之通孔，經由連接器14之端子接腳14b而與外部設備電性連接。
第1基板12之第1面12a具備半導體封裝16。亦如圖2(b)、圖4(a)所示，半導體封裝16具有第2基板18(封裝基板、安裝基板、BGA(Ball Grid Array，球柵陣列)基板)、半導體晶片20(第1電子零件、Si晶片、晶粒、控制器)、及絕緣層22(絕緣體、絕緣片材)。
第2基板18經由焊料球16a而設置於第1面12a上。第2基板18具有與第1面12a面對之第2面18a，及與該第2面18a相反側之第3面18b，進而具備使第2面18a與第3面18b貫通之第2通孔38。圖4(b)係第2基板18之第2面18a之俯視圖，圖4(c)係第2基板18之第3面18b之俯視圖。
於圖3中，第2通孔38與第1通孔40形成於對應之位置，但並不限定於該對應位置關係。形成於半導體封裝16之第2基板18之第2通孔38之一部分如上所述，用於在第2基板18之第2面18a與第3面18b之間進行電性之連接，另一部分亦用於將於半導體晶片20之驅動時所產生之熱向第1基板12側熱輸送。
雖省略了圖示，但第2基板18為與第1基板12相同地將合成樹脂重疊而形成之多層構造。於第2基板18之各層之表面，形成有各種形狀之配線圖案。例如形成有進行信號之收發之信號層、接地層、電源層等。
半導體晶片20例如為覆晶安裝型之半導體，且具有配置於第2基板18之第3面18b上且與第3面18b面對之第4面20a，及與該第4面20a為相反側之第5面20b。於半導體晶片20之第4面20a形成有微小之金屬突起(焊料等)狀之端子(稱為凸塊)21，以凸塊21與第3面18b接觸之方式將半導體晶片20載置於第2基板18之上並將凸塊21熔融，藉此將半導體晶片20接合於第2基板18。半導體晶片20進行與半導體封裝16一起安裝於第1基板12之第1面12a上之其他電子零件之控制，例如記憶體晶片32(第2電子零件、NAND型快閃記憶體晶片)、DRAM晶片54。通常設置複數個記憶體晶片32，圖2(a)表示安裝例如2個記憶體晶片32-1、32-2之例。於第1基板12之第1面12a上亦安裝電源電路模組58。
半導體晶片20例如進行對記憶體晶片32之資料寫入及讀出，於與外部設備(個人電腦、CPU核心等)之間進行資料之發送接收。
雖未圖示，但半導體晶片20亦可包括多層之半導體晶片，層間之連接亦可使用打線接合。最下層之半導體晶片藉由覆晶安裝而接合於第2基板18之第3面18b。
絕緣層22以覆蓋(抵接)第2基板18之第3面18b之表面(一部分例外)及半導體晶片20之第5面20b之方式設置。因此，半導體晶片20成為於第2基板18上自周圍絕緣之狀態。絕緣層22可使用片狀者，亦可將絕緣性樹脂利用塗佈等加以塗佈而形成。
於圖3中，雖省略了圖示，但由於凸塊21之存在而產生之第2基板18之第3面18b與半導體晶片20之第4面20a之間的間隙，亦可藉由底部填充劑予以填埋。底部填充劑係以例如熱硬化性之樹脂，利用毛細管現象進入至第3面18b與第4面20a之間隙，而成為對於衝擊或彎折等來自外部之應力之緩衝材，有助於提高凸塊21之連接可靠性。
半導體封裝16為將焊料球16a柵格狀排列於第2基板18之第2面18a之BGA(Ball Grid Array)，藉由將焊料球16a熔融，而與形成於第1基板12之第1面12a上之焊墊(電極：未圖示)電性連接。焊料球16a不需要配置於第2基板18之第2面18a之整個面，亦可局部地配置。
於圖3中，雖省略了圖示，但由於焊料球16a之存在而產生之第1基板12之第1面12a與第2基板18之第2面18a之間的間隙亦可藉由底部填充劑予以填埋。底部填充劑係以例如熱硬化性之樹脂，利用毛細管現象進入至第1面12a與第2面18a之間隙，而成為對於衝擊或彎折等來自外部之應力之緩衝材，有助於提高焊料球16a之連接可靠性。
亦如圖2(b)、圖4(a)所示，將大致正方形之平面形狀之半導體晶片20載置於同樣為大致正方形之平面形狀之第2基板18之上表面(第3面18b)。於圖2(b)、圖4(a)中，絕緣層22省略圖示。於第2基板18之下表面(第2面18a)排列有多數之焊料球16a。焊料球16a之各者經由第2通孔38而導通至第2基板18之上表面(第3面18b)，且經由未圖示之第2基板18之上表面(第3面18b)之配線而連接於半導體晶片20之內部電路。
一般而言，已知有於半導體封裝中，處於基板(此處，為第2基板18)之角部之1個或複數個接腳(此處，為通孔38)由於在高溫-低溫之溫度循環測試中基板與晶粒(此處，為半導體晶片20)之翹曲之差異之影響，而與處於中央部之接腳相比產生焊料裂紋之機率略高。因此，分別處於第2基板18之4個角部之例如1個第2通孔38a、38b、38c、38d不電性連接於半導體晶片20，經由焊料球16a而連接於第1基板12之接地層42。此種接腳已知有NC(non­connection)接腳或NU(not usage)接腳。於與第2通孔38a、38b、38c、38d對應之第2基板18之第3面18b未形成絕緣層22。於形成絕緣層22時，與第2通孔38a、38b、38c、38d對應之第2基板18之第3面18b藉由蝕刻形成開口部。藉由於該開口部形成導電體，於與第2通孔38a、38b、38c、38d對應之第2基板18之第3面18b設置導電性之露出部39a、39b、39c、39d(亦有時總稱為39)。露出部39a、39b、39c、39d電性連接於第2通孔38a、38b、38c、38d。覆蓋第2基板18之第3面18b之表面及半導體晶片20之第5面20b之絕緣層22覆蓋處於角部以外之第2通孔38之上端，但不覆蓋連接於處於角部之第2通孔38a、38b、38c、38d之露出部39a、39b、39c、39d。藉此，連接於第1基板12之接地層42之第2通孔38a、38b、38c、38d會露出於半導體封裝16之表面。露出部39之形狀並不限定為圓形，亦可為較第2通孔38a、38b、38c、38d大之矩形，於為圓形之情形時，既可為與第2通孔38a、38b、38c、38d相同之直徑，亦可為較第2通孔38a、38b、38c、38d大之直徑。於圖3中，露出部39與絕緣層22之上表面成為相同之高度，但例如亦可為露出部39較高，兩者之高度不同。
於圖4(c)所示之第2基板18之第3面18b中，白圓為經由第3面18b之配線而連接於半導體晶片20之內部電路之第2通孔38，黑圓為連接於接地層42而並非半導體晶片20之第2通孔38a、38b、38c、38d。此處，各角部之3個通孔連接於接地層42。亦可使連接於接地層42之通孔全部露出於半導體封裝16之表面，亦可僅使其中之幾個露出。於任一情形時，露出部39亦可針對各通孔而設置，亦可相對於各角部設置1個露出部39。
如圖2(a)所示，於將於第1基板12上安裝有半導體封裝16之SSD10搭載於外部設備之狀態下，若外部設備產生靜電，則靜電自半導體封裝16之上表面(形成有絕緣層22之面)施加至半導體封裝16。存在由該靜電而產生之電荷流入至絕緣層22之可能性。然而，於絕緣層22中流通之電荷自露出於絕緣層22之表面之導電性之露出部39經由第2通孔38a、38b、38c、38d而流入至SSD10之接地層42。若不存在露出於半導體封裝16之表面之第2通孔38a、38b、38c、38d，則存在如下可能性：由施加至半導體封裝16之靜電而產生且於絕緣層22中流通之電荷經由第2基板18之第3面18b之配線而流入至半導體晶片20之內部電路，使內部電路擊穿(ESD擊穿)。 [ESD]
ESD(Electro-Static Discharge)係藉由於半導體裝置內流通放電電流而產生。半導體裝置有時由於伴隨局部之發熱或電場集中產生之ESD而被擊穿。ESD有幾個產生因素。有相對於該等ESD之產生因素之試驗模型，目前應用之試驗方法大致劃分，有人體模型(Human Body Model：HBM)、設備模型(Machine Model：MM)、元件帶電模型(Charged Device Model：CDM)之3種。
藉由組裝步驟之自動化，半導體裝置於自動組裝中接收摩擦或靜電感應、接觸於金屬類之機會增加。因此，存在如下傾向：隨著步驟之自動化，利用帶電之元件接觸於金屬類而產生之CDM進行之ESD增加。
SSD要求高速化，因此，謀求控制器20之動作之高速化。於控制器20中，為了高速地進行處理，使電容器之容量儘可能地減少。藉此，控制器20成為低阻抗而實現高速動作。另一方面，快閃記憶體32若使電容器之容量變小則能夠實現高速化，但有無法正確地讀取電容器之資訊之可能性。因此，控制器20與快閃記憶體32相比，電容器之容量較小。即，控制器20與快閃記憶體32相比，電容器容量較低，故而成為不易將與高電壓脈衝一起流入之電流之高頻成分去除，ESD耐性較低之構造。因此，控制器20與快閃記憶體32相比，要求ESD耐性。
控制器20由絕緣層22覆蓋。絕緣體由靜電帶電物體而靜電感應，容易帶電。
如實施形態般，藉由將露出於絕緣層22之表面之導電性之露出部39a、39b、39c、39d經由第2通孔38a、38b、38c、38d而連接於SSD10之接地層42，容易將電荷向空氣自然放電(耐CDM)。又，可防止由來自從外部之接觸(或空氣)之ESD電湧所致之電荷流入至控制器20之內部電路(耐HBM、耐MM)。
作為控制器20以外之安裝零件之快閃記憶體32、DRAM54等半導體晶片利用打線接合安裝於封裝基板之情況較多，但該等亦與控制器相同地亦可利用第1實施形態之覆晶技術來安裝。 [第1實施形態之總結]
如此，根據第1實施形態，於絕緣層22中流通之電荷經由露出部39a、39b、39c、39d、第2通孔38a、38b、38c、38d而流入至SSD10之接地層42，不流入至半導體晶片20之內部電路，故而可防止ESD擊穿。先前，為了提高半導體晶片20之絕緣性且保護半導體晶片20免受ESD擊穿影響，而於絕緣層22之上進一步形成有由樹脂材料形成之密封部(亦稱為包覆成形)，於實施形態中，即便絕緣層22之絕緣耐性較低且由靜電產生之電荷於絕緣層22中流通，亦經由露出部39a、39b、39c、39d、第2通孔38a、38b、38c、38d而流入至SSD10之接地層42，故而亦可省略密封部。密封部之省略帶來SSD之成本降低。 [第2實施形態]
圖5係表示第2實施形態之SSD10A之外觀之一例之俯視圖，圖6係表示第2實施形態之控制器附近之剖面構造之一例之剖視圖。
第2實施形態之SSD10A相對於第1實施形態之SSD10之不同點僅在於貼附銘版標籤62。通常，於SSD貼附有描述模型名或序列號之銘版標籤。於第2實施形態中，該銘版標籤62由導電性之材料構成，例如，如圖5所示，以覆蓋DRAM晶片54、半導體封裝16、記憶體晶片32-1、32-2之方式貼附。因此，如圖6所示，銘版標籤62覆蓋構成控制器之半導體封裝16之絕緣層22，且覆蓋自絕緣層22露出之露出部39。因此，銘版標籤62與露出部39電性連接。
根據第2實施形態，發揮與第1實施形態相同之效果，並且亦發揮以下之效果。由於銘版標籤62為導電性，故而於對半導體封裝16施加靜電之情形時，由靜電而產生之電荷於銘版標籤62中流通，容易經由露出部39a、39b、39c、39d、第2通孔38a、38b、38c、38d而流通於SSD10之接地層42。因此，由施加於半導體封裝16之靜電而產生之電荷更不易流通於半導體晶片20之內部電路，可進一步防止ESD擊穿。銘版標籤62之尺寸越大，則經由露出部39a、39b、39c、39d、第2通孔38a、38b、38c、38d而流入至SSD10之接地層42之電荷之量越多，越可防止ESD擊穿。
再者，將SSD中通常使用之銘版標籤設為導電性銘版標籤62，但於不使用銘板標籤之情形時，亦可僅貼附覆蓋DRAM晶片54、半導體封裝16、記憶體晶片32-1、32-2等之導電片。 [第3實施形態]
圖7表示第3實施形態之SSD之接地連接之一例。根據第1、第2實施形態，於絕緣層22中流通之電荷經由露出部39a、39b、39c、39d、第2通孔38a、38b、38c、38d而流動於SSD10之接地層42。於SSD10之接地層42亦連接有控制器20以外之安裝晶片之接地端子。因此，若於控制器20中因靜電而產生之電荷流動於接地層42，則連接於接地層42之其他安裝晶片之接地亦瞬間成為高電位，有將其他安裝晶片擊穿之可能性。同樣地，因其他安裝晶片之電位變動而接地層42瞬間成為高電位，控制器20之第2通孔38a、38b、38c、38d成為高電位，有控制器20被ESD擊穿之可能性。該可能性取決於接地層42中之來自控制器20之接地之接點、與接地層42中來自其他安裝晶片之接地之接點之配線距離，配線距離越近則該可能性越高。其非兩接點間之間隔，而是將兩接點相連之配線長度。
於第3實施形態中，對控制器20之接地端子72與其他晶片、例如快閃記憶體32-1之接地端子76向接地層42之連接進行說明。如圖7所示，若使控制器20之接地端子72與快閃記憶體32-1之接地端子76經由第2通孔38、第1通孔40而直接與接地層42連接，則接地層42中之控制器20之接地接點(端子72之正下方)與快閃記憶體32-1之接地接點(端子76之正下方)之配線距離成為d1＋d2以上。配線距離d1＋d2為配線可形成為格柵狀之情形時之最短距離，若使配線於中途迂迴則距離變長。另一方面，若經由接地層42以外之層之配線而使端子72、76與接地層42連接，則可使該接地層42中之控制器20之接地接點與快閃記憶體32-1之接地接點之配線距離變長。例如，若以使控制器20之接地端子72於接地層42以外之層自快閃記憶體32-1之接地端子76離開之方式拉伸配線，利用接點74連接於接地層42，且以使快閃記憶體32-1之接地端子76亦於接地層42以外之層自控制器20之接地端子72離開之方式拉伸配線，利用接點78連接於接地層42，則接點74與接點78之配線距離成為D1＋D2以上。
如此，於2個晶片之接地端子之距離較近之情形時，以接地層上之接點之距離較端子間之距離長之方式利用接地層以外之層之配線拉伸配線而使2個接地端子之接地接點間之配線距離變長，藉此，於一個晶片中產生之高電位傳播至另一個晶片，防止另一個晶片被擊穿。
實施形態對應用於SSD之控制器20之例進行了說明，但並不限定於此，亦可應用於利用覆晶安裝之任何半導體裝置。
再者，本發明並不僅限定於上述實施形態，於實施階段中可於不脫離其主旨之範圍內將構成要素變化而具體化。又，利用上述實施形態中揭示之複數個構成要素之適當組合能夠形成各種發明。例如，亦可自實施形態所示之所有構成要素刪除幾個構成要素。再者，亦可適當組合不同實施形態中之構成要素。
10‧‧‧SSD12‧‧‧第1基板12a‧‧‧第1面12b‧‧‧背面12d‧‧‧側面12g‧‧‧第1層12h‧‧‧第2層12i‧‧‧第3層14‧‧‧連接器14b‧‧‧端子接腳14c‧‧‧狹縫16‧‧‧半導體封裝16a‧‧‧焊料球18‧‧‧第2基板18a‧‧‧第2面18b‧‧‧第3面20‧‧‧半導體晶片20a‧‧‧第4面20b‧‧‧第5面21‧‧‧凸塊22‧‧‧絕緣層32-1、32-2‧‧‧快閃記憶體38‧‧‧第2通孔38a、38b、38c、38d‧‧‧第2通孔39‧‧‧露出部39a、39b、39c、39d‧‧‧露出部40‧‧‧第1通孔50‧‧‧外部設備52‧‧‧主機I/F54‧‧‧DRAM58‧‧‧電源電路62‧‧‧銘版標籤72‧‧‧接地端子74‧‧‧接點76‧‧‧接地端子78‧‧‧接點
圖1係表示第1實施形態之SSD之構成之一例之方塊電路圖。 圖2(a)及(b)表示SSD與控制器之外觀之一例。 圖3表示控制器附近之剖面構造之一例。 圖4(a)～(c)表示控制器基板之構造之一例。 圖5係表示第2實施形態之SSD之外觀之一例之俯視圖。 圖6表示控制器附近之剖面構造之一例。 圖7表示第3實施形態之SSD之接地連接之一例。
12‧‧‧第1基板
12a‧‧‧第1面
12b‧‧‧背面
12d‧‧‧側面
12g‧‧‧第1層
12h‧‧‧第2層
12i‧‧‧第3層
14‧‧‧連接器
16‧‧‧半導體封裝
16a‧‧‧焊料球
18‧‧‧第2基板
18a‧‧‧第2面
18b‧‧‧第3面
20‧‧‧半導體晶片
20a‧‧‧第4面
20b‧‧‧第5面
21‧‧‧凸塊
22‧‧‧絕緣層
38‧‧‧第2通孔
38a、38b‧‧‧第2通孔
39a、39b‧‧‧露出部
40‧‧‧第1通孔

Claims (5)

  1. 一種半導體裝置，其具備：第1基板，其包含接地層及複數個第1通孔(via)；及第1半導體零件以及第2半導體零件，上述第1半導體零件安裝於上述第1基板，上述第2半導體零件安裝於上述第1基板；且上述第1半導體零件具備：第2基板，其具備複數個第2通孔；半導體晶片，其覆晶安裝於上述第2基板；及絕緣層，其覆蓋上述第2基板與上述半導體晶片；上述第2基板之上述複數個第2通孔具備：至少1個第3通孔，其電性連接於上述半導體晶片；及至少1個第4通孔，其未電性連接於上述半導體晶片；上述第2基板包含：與至少1個上述第4通孔電性連接的導電性之露出部；上述露出部係露出於上述絕緣層之表面；上述第1半導體零件之接地端子經由上述第1基板之配線而與上述接地層於第1點連接；上述第2半導體零件之接地端子經由上述第1基板之配線而與上述接地層於第2點連接；上述第1點與上述第2點之間之配線距離係：長於上述接地層之上述第1半導體零件之接地端子正下方之第3點與上述接地層之上述第2半導體零件之接地端子正下方之第4點之間的配線距離。
  2. 如請求項1之半導體裝置，其中上述第2基板為矩形形狀，至少1個上述第4通孔位於上述第2基板之至少1個角部。
  3. 如請求項2之半導體裝置，其中至少1個上述第4通孔經由上述第1基板之上述第1通孔而連接於上述接地層。
  4. 如請求項3之半導體裝置，其進而具備：導電片，其覆蓋上述第1半導體零件與上述第2半導體零件。
  5. 如請求項4之半導體裝置，其中上述導電片具備記載與上述半導體裝置相關之資訊之標籤。
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