CN111799230A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN111799230A
CN111799230A CN202010089008.5A CN202010089008A CN111799230A CN 111799230 A CN111799230 A CN 111799230A CN 202010089008 A CN202010089008 A CN 202010089008A CN 111799230 A CN111799230 A CN 111799230A
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China
Prior art keywords
layer
package
sidewall
insulating layer
substrate
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Pending
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CN202010089008.5A
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English (en)
Inventor
闵丙国
姜允熙
宋旼友
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN111799230A publication Critical patent/CN111799230A/zh
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Abstract

一种半导体封装件，包含：第一半导体芯片，具有上表面、与上表面相对的下表面以及在上表面与下表面之间的侧壁；封端绝缘层，覆盖第一半导体芯片的上表面和侧壁；以及屏蔽层，在封端绝缘层上，其中封端绝缘层的下部部分包含接触屏蔽层的下表面的侧向突出封端突出部。

Description

半导体封装件
相关申请案的交叉引用
2019年4月1日在韩国知识产权局提交且标题为：“半导体封装件(SemiconductorPackage)”的韩国专利申请案第10-2019-0037898号以其全文引用的方式并入本文中。
技术领域
本公开的实例实施例涉及一种半导体封装件。
背景技术
半导体封装件可以使集成电路装置适用于电子装置的形式来实施。举例来说，半导体封装件可具有其中半导体芯片安装在印刷电路板(printed circuit board，PCB)上且结合线和/或凸块将半导体芯片与PCB电连接的结构。
发明内容
实施例可通过提供一种半导体封装件来实现，所述半导体封装件包含第一半导体芯片，具有上表面、与上表面相对的下表面以及在上表面与下表面之间的侧壁；封端绝缘层，覆盖第一半导体芯片的上表面及侧壁；以及屏蔽层，在封端绝缘层上，其中封端绝缘层的下部部分包含接触屏蔽层的下表面的侧向突出封端突出部。
实施例可通过提供一种半导体封装件来实现，所述半导体封装件包含：第一半导体芯片，具有上表面、与上表面相对的下表面以及在上表面与下表面之间的侧壁；以及封端绝缘层，覆盖第一半导体芯片的上表面和侧壁，其中封端绝缘层具有第一封端侧壁和第二封端侧壁，所述第二封端侧壁在第一封端侧壁下方以使得第二封端侧壁邻近于第一半导体芯片的下表面，且第二封端侧壁的表面粗糙度大于第一封端侧壁的表面粗糙度。
实施例可通过提供一种半导体封装件来实现，所述半导体封装件包含：第一半导体芯片，具有上表面、与上表面相对的下表面以及在上表面与下表面之间的侧壁；封端绝缘层，在第一半导体芯片的上表面和侧壁上；以及屏蔽层，在封端绝缘层上，其中封端绝缘层的下部外侧壁与屏蔽层的下部外侧壁垂直对准。
附图说明
通过参考附图来详细描述示范性实施例，特征将对于本领域的技术人员显而易见，在附图中：
图1示出根据实例实施例的半导体封装件的立体图。
图2A示出沿图1的线I-I'截取的剖面视图。
图2B示出根据实例实施例的半导体封装件的剖面视图。
图3A、图3B以及图3C示出图2A的部分‘P1’的放大视图。
图4示出图3A的部分‘P2’的放大视图。
图5A、图5B以及图5C示出制造根据实例实施例的具有图2A的剖面的半导体封装件的方法中的阶段的剖面视图。
图6示出根据实例实施例的半导体封装件的剖面视图。
图7示出根据实例实施例的半导体封装件的剖面视图。
图8示出根据实例实施例的半导体封装件的剖面视图。
图9示出根据实例实施例的半导体封装件的剖面视图。
图10示出根据实例实施例的半导体封装件的剖面视图。
图11示出图10的部分‘P1’的放大视图。
图12示出根据实例实施例的半导体封装件的剖面视图。
图13示出根据实例实施例的半导体封装件的剖面视图。
附图标号说明
10：下部半导体芯片；
12：芯片导电图案；
12p：边缘芯片导电图案；
14：芯片保护层；
15：内部连接结构；
15a：导电柱；
15b：焊料层；
16：外部连接端子；
17：底部填充层；
18：模制层；
20：封端绝缘层；
20a：含聚合物层；
20b：绝缘颗粒；
20p：侧向突出封端突出部；
20s1：第一封端侧壁；
20s2：第二封端侧壁；
30：屏蔽层；
30a：第一屏蔽层；
30ap：侧向突出第一屏蔽突出部；
30b：第二屏蔽层；
30p：侧向突出屏蔽突出部；
30s1：第一屏蔽侧壁；
30s2：第二屏蔽侧壁；
30sp：中间屏蔽突出部；
40：再分布层；
41：再分布图案；
42：封装基底；
43：球焊盘；
50：载体基底；
51：容纳部分；
52：封装连接结构；
54：上部封装基底；
56：上部半导体芯片；
58：上部模制层；
60：热界面材料层；
70：连接基底；
71：连接布线结构；
72：腔室；
73：连接绝缘层；
80：上部再分布层；
81：上部再分布图案；
83：通孔；
100、100a、101、102、103、104、105、106、107：半导体封装件；
100p：初步半导体封装件；
I-I'：线；
LPK：下部半导体封装件；
P1、P2：部分；
R1：凹部区域；
UPK：上部半导体封装件；
V1：第一气隙区域；
V2：第二气隙区域。
具体实施方式
图1示出根据实例实施例的半导体封装件的立体图。图2A示出沿图1的线I-I'截取的剖面视图。图2B示出根据实例实施例的半导体封装件的剖面视图。图3A、图3B以及图3C示出图2A的部分‘P1’的放大视图。图4示出图3A的部分‘P2’的放大视图。
参考图1和图2A，根据实例实施例的半导体封装件100可包含半导体芯片10。半导体芯片10可包含例如系统大规模集成(large scale integration，ISI)；逻辑电路；图像传感器，例如CMOS图像传感器(CMOS image sensor，CIS)；存储装置，例如闪存、DRAM、SRAM、EEPROM、PRAM、MRAM、ReRAM、高带宽存储器(high bandwidth memory，HBM)或混合存储立方体(hybrid memory cubic，HMC)；或微机电系统(microelectromechanical system，MEMS)。如本文中所使用，术语“或”不是排它性术语，例如“A或B”可包含A、B或A和B。
参考图2A，芯片保护层14可覆盖半导体芯片10的表面(例如下表面)。芯片保护层14可由绝缘材料形成，例如氮化硅或聚酰亚胺。彼此间隔开的芯片导电图案12可在半导体芯片10的下表面与芯片保护层14之间。芯片导电图案12可包含例如铝、铜、金、锡或氮化钛。芯片导电图案12中的每一个可由单个层或多个层形成。外部连接端子16可分别穿过芯片保护层14以连接到芯片导电图案12。外部连接端子16可各自包含例如导电凸块、导电柱、焊料层或焊球。
参考图1和图2A，封端绝缘层20可覆盖半导体芯片10的表面(例如与下表面相对的上表面)和侧壁(例如四个侧壁)。举例来说，封端绝缘层20可覆盖半导体芯片10的五个表面。屏蔽层30可在封端绝缘层20上。屏蔽层30可覆盖封端绝缘层20的上表面和一个或多个侧壁。半导体封装件100可以是一种扇入型晶片级封装。
参考图3A和图4，封端绝缘层20可包含覆盖(或接触，例如直接接触)屏蔽层30的下表面的侧向突出封端突出部20p。封端绝缘层20的下表面可与芯片保护层14的下表面共面。封端绝缘层20可具有在侧向突出封端突出部20p上方的第一封端侧壁20s1和在第一封端侧壁20s1下方的第二封端侧壁20s2。第二封端侧壁20s2可对应于或可以是侧向突出封端突出部20p的侧壁。第二封端侧壁20s2的表面粗糙度可大于第一封端侧壁20s1的表面粗糙度。屏蔽层30的下部部分可由侧向突出封端突出部20p封闭或覆盖，且当半导体封装件100安装在板基底上时，可阻挡屏蔽层30与邻近导电图案之间的非所要接触。
封端绝缘层20可具有例如约1微米到约20微米的厚度。封端绝缘层20可包含例如氧化铝层或氧化硅层的无机层，或例如环氧树脂或聚氨酯的含聚合物层，且可具有单层或多层结构。当封端绝缘层20由例如氧化铝层或氧化硅层的无机层形成时，封端绝缘层20可通过沉积工艺来形成，例如溅射工艺、物理气相沉积(physical vapor deposition，PVD)、化学气相沉积(chemical vapor deposition，CVD)工艺或原子层沉积(atomic layerdeposition，ALD)工艺。举例来说，当封端绝缘层20通过ALD工艺形成时，无论位置如何，封端绝缘层20可共形地形成为具有均匀厚度。另外，当封端绝缘层20由含聚合物层形成时，封端绝缘层20可通过喷涂干燥工艺形成。
在实施方案中，参考图4，封端绝缘层20可包含含聚合物层20a以及分散于含聚合物层20a中的绝缘颗粒20b。含聚合物层20a可包含例如环氧树脂或聚氨酯，且绝缘颗粒20b可包含无机材料，例如氧化硅或氧化铝。绝缘颗粒20b可彼此接触地分布于含聚合物层20a中。绝缘颗粒20b可彼此接触地分布，且可提高散热效果。
氧化硅层或氧化铝层可具有绝缘特性和相对优良的热导率。举例来说，当封端绝缘层20由氧化硅或氧化铝形成或绝缘颗粒20b由氧化硅或氧化铝形成时，可提高散热效果。
在实施方案中，再次参考图3A，屏蔽层30可具有例如约1微米到约10微米的厚度。屏蔽层30可包含单层或多层结构，且可包含金属，例如不锈钢(stainless steel，SUS)、铜或镍。屏蔽层30可通过沉积工艺形成，例如溅射工艺、PVD工艺、CVD工艺或ALD工艺。屏蔽层30可具有邻近于半导体芯片10的侧壁或与所述侧壁大致对准的第一屏蔽侧壁30s1，以及邻近于芯片保护层14的侧壁或与所述侧壁大致对准且在第一屏蔽侧壁30s1下方的第二屏蔽侧壁30s2。第二屏蔽侧壁30s2的表面粗糙度可大于第一屏蔽侧壁30s1的表面粗糙度。第二屏蔽侧壁30s2可与第二封端侧壁20s2垂直对准。
在实施方案中，参考图3B，屏蔽层30的下部部分可侧向突出。举例来说，屏蔽层30可包含侧向突出屏蔽突出部30p。屏蔽层30的第二屏蔽侧壁30s2可对应于或可以是侧向突出屏蔽突出部30p的侧壁。
在实施方案中，参考图3C，屏蔽层30可包含第一屏蔽层30a和第二屏蔽层30b的双层。第一屏蔽层30a可包含与第二屏蔽层30b的金属不同的金属。第一屏蔽层30a可包含侧向突出第一屏蔽突出部30ap。在实施方案中，屏蔽层30可具有三层或大于三层的结构。双层或多层结构的屏蔽层30可有助于提高电磁干扰(electromagnetic interference，EMI)屏蔽效果。
在实施方案中，参考图2B，半导体封装件100a可包含在半导体芯片10的下表面的边缘(例如外侧)上的边缘芯片导电图案12p。边缘芯片导电图案12p的侧壁可与半导体芯片10的侧壁和芯片保护层14的侧壁垂直对准。边缘芯片导电图案12p可通过封端绝缘层20来与屏蔽层30绝缘。除了边缘芯片导电图案12p以外，半导体封装件100a的其它组件可与参考图3A到图3C以及图4所描述的相同或类似。
参考图2A和图2B，半导体封装件100和半导体封装件100a可具有由封端绝缘层20保护的上表面和侧壁。半导体封装件100和半导体封装件100a可通过屏蔽层30具有EMI屏蔽功能。屏蔽层30可通过封端绝缘层20与边缘芯片导电图案12p间隔开，且可增加芯片导电图案12和芯片导电图案12p的设计自由度。在实施方案中，封端绝缘层20可包含例如氧化铝层和/或氧化硅层，且可提高散热效果。封端绝缘层20可包含接触屏蔽层30的下表面的侧向突出封端突出部20p，且当半导体封装件100和半导体封装件100a安装在板基底上时，可防止半导体封装件100和半导体封装件100a与邻近导电图案短接(shorting)。举例来说，可防止不良安装，且可提供具有改善的可靠性和耐久性的半导体封装件。
图5A、图5B以及图5C示出制造根据实例实施例的具有图2A的剖面的半导体封装件的方法中的阶段的剖面视图。
参考图5A，可制造初步半导体封装件100p。初步半导体封装件100p可具有不包含或不具有图2A的半导体封装件100中的封端绝缘层20和屏蔽层30的结构。初步半导体封装件100p可通过扇入型晶片级封装的制造方法形成。可制备载体基底50。载体基底50可包含容纳部分51。在实施方案中，如图5A中所示出，可包含一个容纳部分51。在实施方案中，可在载体基底50中布置多个容纳部分51。初步半导体封装件100p可定位于载体基底50上。在那时，附接到半导体芯片10的下表面的外部连接端子16可插入到容纳部分51中，且芯片保护层14的边缘可接触载体基底50。
参考图5B，封端绝缘层20可形成为覆盖半导体芯片10的上表面和侧壁。封端绝缘层20可在载体基底50的上表面上连续形成。封端绝缘层20可通过执行例如溅射工艺、PVD工艺、CVD工艺或ALD工艺的沉积工艺由无机层来形成。在实施方案中，封端绝缘层20可通过喷涂干燥工艺由含聚合物层来形成。屏蔽层30可在封端绝缘层20上形成。屏蔽层30可通过执行例如溅射工艺、PVD工艺、CVD工艺或ALD工艺的沉积工艺由例如SUS、铜或镍的金属层来形成。屏蔽层30可在载体基底50的上表面以及半导体芯片10的上表面和侧壁上(例如在封端绝缘层20上)形成。
参考图5C，可从载体基底50提起半导体芯片10。举例来说，半导体芯片10上的封端绝缘层20和屏蔽层30可与载体基底50上的封端绝缘层20和屏蔽层30分离。邻近于半导体芯片10的下表面的封端绝缘层20和屏蔽层30可与图3B中所示的封端绝缘层和屏蔽层类似地侧向突出。在实施方案中，可将突出部(图3B的侧向突出封端突出部20p和图3B的侧向突出屏蔽突出部30p)抛光，从而移除突出部的至少部分。举例来说，可如图3A中所示来移除侧向突出屏蔽突出部30p，且可减小侧向突出封端突出部20p的大小。在实施方案中，如图3A或图3B中所示，可相对增大封端绝缘层20的第二封端侧壁20s2的表面粗糙度和屏蔽层30的第二屏蔽侧壁30s2的表面粗糙度。取决于侧向突出屏蔽突出部30p和/或侧向突出封端突出部20p的抛光/移除量，所得结构可变成图3A或图3B中所示的结构。在实施方案中，在从载体基底50提起半导体芯片10之前，可使用激光或钻孔机来切掉封端绝缘层20和屏蔽层30。可通过这类工艺来制造图2A的半导体封装件100。
图6示出根据实例实施例的半导体封装件的剖面视图。
参考图6，半导体封装件101可以是扇出型晶片级封装的实例。举例来说，半导体封装件101可具有先芯片(chip-first)或先模制(mold-first)的扇出型晶片级封装结构。半导体封装件101可更包含电连接到半导体芯片10的再分布层40。再分布图案41可在再分布层40中。再分布图案41中的一些可穿过芯片保护层14以接触半导体芯片10的芯片导电图案12。再分布图案41可将半导体芯片10的芯片导电图案12与外部连接端子16电连接。
再分布图案41可包含金属，例如铜或铝。再分布层40可从半导体芯片10的侧壁且在所述侧壁下方朝外突出。模制层18可覆盖再分布层40和半导体芯片10。模制层18的下表面(例如面向再分布层的表面)可与芯片保护层14的下表面共面。模制层18可包含绝缘树脂，例如环氧模塑料(epoxy molding compound，EMC)。模制层18可更包含填充剂。填充剂可分散于绝缘树脂中。填充剂可包含例如氧化硅。
模制层18的上表面和侧壁以及再分布层40的侧壁可由封端绝缘层20覆盖。封端绝缘层20的上表面和侧壁可由屏蔽层30覆盖。封端绝缘层20的下部部分可侧向突出，且可接触屏蔽层30的下表面。封端绝缘层20和屏蔽层30的详细结构可与参考图3A到图3C以及图4所描述的相同或类似。在实施方案中，在半导体封装件101中，一个半导体芯片10可在再分布层40上。在实施方案中，两个或大于两个半导体芯片10可并排于再分布层40上。
半导体封装件101可如下制造。半导体芯片10可在额外载体基底上，且随后可形成模制层18以覆盖半导体芯片10。在半导体芯片10和模制层18与额外载体基底分离之后，可在半导体芯片10的下表面和模制层18的下表面上形成再分布层40以制造初步半导体封装件。初步半导体封装件可定位于载体基底50上，替代图5A的初步半导体封装件100p。其后，可执行如参考图5B和图5C所描述的后续工艺以形成封端绝缘层20和屏蔽层30。
图7示出根据实例实施例的半导体封装件的剖面视图。
参考图7，半导体封装件102可包含封装基底42。半导体芯片10可通过倒装芯片结合方法使用内部连接结构15安装在封装基底42上。封装基底42可以是具有单层或多层布线结构的印刷电路板(PCB)基底。内部连接结构15可包含例如导电凸块、导电柱、焊料层或焊球。导电凸块和导电柱可包含例如铜。焊料层和焊球可包含例如锡或铅。球焊盘43可在封装基底42的下表面上。外部连接端子16可结合到球焊盘43。封装基底42可从半导体芯片10的侧壁且在所述侧壁下方朝外突出。模制层18可覆盖半导体芯片10的侧壁和封装基底42的上表面。模制层18的上表面可与半导体芯片10的上表面共面。模制层18可延伸以填充半导体芯片10与封装基底42之间的空间。
封端绝缘层20可接触半导体芯片10的上表面、模制层18的上表面和侧壁以及封装基底42的侧壁。封端绝缘层20的上表面和侧壁可由屏蔽层30覆盖。封端绝缘层20的下部部分可侧向突出以接触屏蔽层30的下表面。封端绝缘层20和屏蔽层30的详细结构可与参考图3A到图3C以及图4所描述的相同或类似。在实施方案中，在半导体封装件102中，一个半导体芯片10可在封装基底42上。在实施方案中，两个或大于两个半导体芯片10可并排安置或垂直堆叠在封装基底42上。
半导体封装件102可如下制造。在制造除了图7的结构中的封端绝缘层20和屏蔽层30以外或不包含所述封端绝缘层和所述屏蔽层的结构的初步半导体封装件之后，初步半导体封装件可定位于载体基底50上，替代图5A的初步半导体封装件100p。其后，可执行如参考图5B和图5C所描述的后续工艺。
图8示出根据实例实施例的半导体封装件的剖面视图。
参考图8，半导体封装件103可以是层叠封装结构的实例。半导体封装件103可包含下部半导体封装件LPK和安装在下部半导体封装件LPK上的上部半导体封装件UPK。
下部半导体封装件LPK可包含下部封装基底42以及安装在下部封装基底42上的下部半导体芯片10。下部封装基底42可以是具有单层或多层布线结构的PCB基底。下部半导体芯片10可通过倒装芯片结合方法使用内部连接结构15安装在下部封装基底42上。外部连接端子16可粘附到下部封装基底42。内部连接结构15和外部连接端子16可各自包含例如导电凸块、导电柱、焊料层或焊球。下部模制层18可覆盖下部封装基底42的上表面和下部半导体芯片10。下部模制层18的上表面可与下部半导体芯片10的上表面共面。
上部半导体封装件UPK可包含上部封装基底54以及安装在上部封装基底54上的上部半导体芯片56。上部半导体芯片56可堆叠在上部封装基底54上，且可通过焊线结合方法连接到上部封装基底54。上部半导体芯片56和上部封装基底54可由上部模制层58覆盖。下部模制层18和上部模制层58可各自包含绝缘树脂，例如环氧模塑料(EMC)。下部模制层18和上部模制层58可更包含填充剂。填充剂可分散于绝缘树脂中。填充剂可包含例如氧化硅。
上部半导体封装件UPK可通过封装连接结构52电连接到下部半导体封装件LPK。封装连接结构52可将下部封装基底42与上部封装基底54电连接。下部模制层18可包含开口，封装连接结构52插入到所述开口中。封装连接结构52可包含例如导电凸块、导电柱、焊料层或焊料凸块。
上部封装基底54可与下部半导体芯片10和下部模制层18间隔开。热界面材料层60可在上部封装基底54与下部半导体芯片10之间。热界面材料层60可包含例如散热膏或热环氧树脂。在实施方案中，散热膏或热环氧树脂可包含金属固体颗粒。
上部半导体封装件UPK和下部半导体封装件LPK可由封端绝缘层20覆盖。封端绝缘层20可接触上部模制层58的上表面和侧壁、上部封装基底54的侧壁、下部模制层18的侧壁以及下部封装基底42的侧壁。封端绝缘层20可在下部模制层18与上部封装基底54之间延伸。封端绝缘层20可延伸以接触封装连接结构52的侧壁和热界面材料层60。
封端绝缘层20的上表面和侧壁可由屏蔽层30覆盖。封端绝缘层20的下部部分可侧向突出以接触屏蔽层30的下表面。封端绝缘层20和屏蔽层30的详细结构可与参考图3A到图3C以及图4所描述的相同或类似。
半导体封装件103可如下制造。在制造具有除了图8的结构中的封端绝缘层20和屏蔽层30以外的结构的初步半导体封装件之后，初步半导体封装件可定位于载体基底50上，替代图5A的初步半导体封装件100p。其后，可执行如参考图5B和图5C所描述的后续工艺。封端绝缘层20可通过ALD工艺共形地形成。在那时，用于形成封端绝缘层20的源气可在上部半导体封装件UPK与下部半导体封装件LPK之间扩散，以使得封端绝缘层20可填充上部半导体封装件UPK与下部半导体封装件LPK之间的空间。
图9示出根据实例实施例的半导体封装件的剖面视图。
参考图9，半导体封装件104可以是层叠封装结构的实例。半导体封装件104可包含下部半导体封装件LPK以及安装在下部半导体封装件LPK上的上部半导体封装件UPK。
下部半导体封装件LPK可包含再分布层40以及安装于再分布层40上的半导体芯片10。包含腔室72的连接基底70可在再分布层40上。在实施方案中，腔室72可在连接基底70中的中心部分中，且连接基底70在平面视图中可具有矩形环形状。连接基底70可包含连接布线结构71和连接绝缘层73。连接布线结构71可包含穿过连接绝缘层73的导通孔塞、导电布线线路以及导电垫。连接绝缘层73可各自包含热固性树脂，例如环氧树脂；热塑性树脂，例如聚酰亚胺；或具有增强材料(例如玻璃纤维(玻璃布或玻璃织物))或无机填充剂浸渍于热固性树脂和热塑性树脂中的树脂，如预浸料、味之素(ajinomoto)积层膜(build-up film，BF)、双马来酰亚胺三嗪(bismaleimide triazine，BT)或可光成像介电(photo imageabledielectric，PLD)树脂。
连接布线结构71可电连接到再分布层40中的再分布图案41。下部半导体芯片10可插入到腔室72中。下部半导体芯片10可与腔室72的内侧壁间隔开。下部模制层18可填充下部半导体芯片10与腔室72的内侧壁之间的空间。下部模制层18可接触再分布层40的上表面。下部模制层18可延伸以覆盖下部半导体芯片10的上表面。下部模制层18还可延伸以覆盖连接基底70的上表面。下部模制层18的侧壁可与连接基底70的侧壁和再分布层40的侧壁垂直对准。
上部半导体封装件UPK可包含上部封装基底54以及安装在上部封装基底54上的上部半导体芯片56。上部半导体芯片56可通过倒装芯片结合方法安装在上部封装基底54上。上部模制层58可覆盖上部封装基底54的上表面和上部半导体芯片56的侧壁。上部模制层58可填充上部半导体芯片56与上部封装基底54之间的空间。上部模制层58的上表面可与上部半导体芯片56的上表面共面。
上部半导体封装件UPK可与下部半导体封装件LPK间隔开。上部半导体封装件UPK可通过封装连接结构52电连接到下部半导体封装件LPK。封装连接结构52可将连接基底70与上部封装基底54电连接。下部模制层18可包含开口，封装连接结构52插入到所述开口中。封装连接结构52可各自包含例如导电凸块、导电柱、焊料层或焊球。
上部半导体封装件UPK和下部半导体封装件LPK可由封端绝缘层20覆盖。封端绝缘层20可接触上部模制层58的上表面和侧壁、上部半导体芯片56的上表面、上部封装基底54的侧壁、下部模制层18的侧壁、连接基底70的侧壁以及再分布层40的侧壁。
封端绝缘层20可在下部模制层18与上部封装基底54之间延伸。封端绝缘层20可延伸以接触封装连接结构52的侧壁。无论位置如何，封端绝缘层20可具有恒定厚度。在封端绝缘层20中可存在第一气隙区域V1和第二气隙区域V2。第一气隙区域V1可存在于连接基底70与上部封装基底54之间或邻近封装连接结构52之间。第二气隙区域V2可存在于下部半导体芯片10与上部封装基底54之间。凹部区域R1可在上部半导体封装件UPK的边缘与下部半导体封装件LPK的边缘之间的封端绝缘层20中。
屏蔽层30可覆盖封端绝缘层20的上表面和侧壁。屏蔽层30可包含填充凹部区域R1的中间屏蔽突出部30sp。封端绝缘层20的下部部分可侧向突出以接触屏蔽层30的下表面。封端绝缘层20和屏蔽层30的详细结构可与参考图3A到图3B以及图4所描述的相同或类似。
半导体封装件104可如下制造。在制造具有除了图9的结构中的封端绝缘层20和屏蔽层30以外的结构的初步半导体封装件之后，初步半导体封装件可定位于载体基底50上，替代图5A的初步半导体封装件100p。其后，可执行如参考图5B和图5C所描述的后续工艺。封端绝缘层20可通过ALD工艺共形地形成。在那时，用于形成封端绝缘层20的源气可在上部半导体封装件UPK与下部半导体封装件LPK之间扩散，以使得封端绝缘层20可插入在上部半导体封装件UPK与下部半导体封装件LPK之间。另外，在那时，可形成第一气隙区域V1和第二气隙区域V2。
图10示出根据实例实施例的半导体封装件的剖面视图。图11示出图10的部分‘P1’的放大视图。
参考图10和图11，在半导体封装件105中，可省略图2A的屏蔽层30。半导体芯片10的上表面和侧壁可仅由封端绝缘层20覆盖。举例来说，图2A的侧向突出封端突出部20p可以不存在于封端绝缘层20的下部部分处。封端绝缘层20可包含第一封端侧壁20s1以及在第一封端侧壁20s1下方的第二封端侧壁20s2。第二封端侧壁20s2的表面粗糙度可大于第一封端侧壁20s1的表面粗糙度。不包含屏蔽层30的半导体封装件的此结构可应用于图6到图9的半导体封装件101、半导体封装件102、半导体封装件103以及半导体封装件104。举例来说，图6到图9的半导体封装件101、半导体封装件102、半导体封装件103以及半导体封装件104可以不包含屏蔽层30。在这种情况下，封端绝缘层20可以不包含图2A的侧向突出封端突出部20p，且封端绝缘层20的下部结构可与参考图11所描述的相同或类似。
除了省略图5C的屏蔽层30的形成以外，半导体封装件105可通过执行与参考图5A到图5C所描述相同的工艺来制造。
图12示出根据实例实施例的半导体封装件的剖面视图。
参考图12，半导体封装件106可具有后芯片(chip-last)或先再分布(RDL-first)的扇出型晶片级封装结构。举例来说，半导体芯片10可在再分布层40上。半导体芯片10的上表面和侧壁可依序由封端绝缘层20和屏蔽层30覆盖。封端绝缘层20和屏蔽层30可与参考图1到图4所描述的相同或类似。
多层再分布图案41可在再分布层40中。再分布图案41中的一些可将外部连接端子16与接触芯片导电图案12的内部连接结构15电连接。内部连接结构15中的每一个可包含导电柱15a以及在导电柱15a下方的焊料层15b。导电柱15a可包含例如铜。焊料层15b可包含例如锡和/或铅。因为内部连接结构15之间的间隔较窄，所以其中内部连接结构15包含导电柱15a和焊料层15b的结构可在防止电短路方面有利。再分布层40可从半导体芯片10的侧壁且在所述侧壁下方朝外延伸。
半导体芯片10与再分布层40之间的空间可用底部填充层17填充。底部填充层17可接触封端绝缘层20，且可与屏蔽层30间隔开。屏蔽层30和再分布层40可由模制层18覆盖。模制层18可接触封端绝缘层20的下部侧壁(例如封端突出部的侧壁)。相对于再分布层40的上表面，模制层18的下表面可低于半导体芯片10的下表面和芯片保护层14的下表面。模制层18可接触底部填充层17。半导体封装件106的其它组件可与参考图6所描述的相同或类似。
半导体封装件106可如下制造。半导体芯片10可设置为通过参考图5A、图5B以及图5C所描述的工艺由封端绝缘层20和屏蔽层30来覆盖。再分布层40可在额外载体基底上形成，且半导体芯片10可安装于再分布层40上。其后，可形成底部填充层17和模制层18。
图13示出根据实例实施例的半导体封装件的剖面视图。
参考图13，半导体封装件107可以是叠层封装结构的实例。半导体封装件107可包含下部半导体封装件LPK以及安装在下部半导体封装件LPK上的上部半导体封装件UPK。
下部半导体封装件LPK可具有与图12的半导体封装件106类似的结构。举例来说，下部半导体封装件LPK可包含安装在下部再分布层40上的下部半导体芯片10。下部再分布层40可包含下部再分布图案41。下部半导体芯片10的上表面和侧壁可由封端绝缘层20和屏蔽层30覆盖。屏蔽层30和下部再分布层40可由下部模制层18覆盖。上部再分布层80可在下部模制层18上。上部再分布层80可包含上部再分布图案81。通孔83可穿过下部模制层18以将上部再分布层80与下部再分布层40电连接。
上部半导体封装件UPK可包含上部封装基底54以及安装在上部封装基底54上的上部半导体芯片56。上部半导体芯片56可通过焊线结合方法连接到上部封装基底54。上部半导体芯片56和上部封装基底54可由上部模制层58覆盖。上部半导体封装件UPK可通过封装连接结构52电连接到下部半导体封装件LPK。举例来说，封装连接结构52可将上部再分布层80与上部封装基底54电连接。上部模制层58和下部模制层18可以不由封端绝缘层20和屏蔽层30覆盖，且可暴露。半导体封装件107的其它组件可与参考图8和图12所描述的相同或类似。
借助于总结和综述，随着电子行业的发展，已进行各种研究来改善半导体封装件的可靠性和耐久性。
一个或多个实施例可提供一种半导体封装件，所述半导体封装件有助于防止与邻近半导体封装件短接(shorting)，且因此可防止不良安装，从而提供具有改善的可靠性和耐久性的半导体封装件。
尽管可能没有绘示一些剖面视图的对应平面视图和/或立体图，但本文中所示出的装置结构的剖面视图提供对于沿两个不同方向(如将在平面视图中示出)和/或在三个不同方向上(如将在立体图中示出)延伸的多个装置结构的支持。两个不同方向可以或可以不彼此正交。三个不同方向可包含可与两个不同方向正交的第三方向。多个装置结构可集成在同一电子装置中。举例来说，当装置结构(例如存储单元结构或晶体管结构)以剖面视图示出时，电子装置可包含多个装置结构(例如存储单元结构或晶体管结构)，如将由电子装置的平面视图所示出。多个装置结构可以阵列和/或二维图案来布置。
已在本文中公开实例实施例，且尽管采用特定术语，但所述术语仅在一般性和描述性意义上使用并解释，且并不出于限制的目的。在一些情况下，如对本领域的一般技术人员将显而易见，截至本申请案提交时，除非另外特别指示，否则结合特定实施例描述的特征、特性和/或元件可单独使用或与结合其它实施例描述的特征、特性和/或元件组合使用。因此，本领域的技术人员应理解，可在不脱离如以下权利要求中所阐述的本发明的精神和范围的情况下作出形式和细节的各种变化。

Claims (25)

1.一种半导体封装件，包括：
第一半导体芯片，具有上表面、与所述上表面相对的下表面以及在所述上表面与所述下表面之间的侧壁；
封端绝缘层，覆盖所述第一半导体芯片的所述上表面和所述侧壁；以及
屏蔽层，在所述封端绝缘层上，
其中，所述封端绝缘层的下部部分包含接触所述屏蔽层的下表面的侧向突出封端突出部。
2.根据权利要求1所述的半导体封装件，其中所述封端绝缘层的所述下部部分的外侧壁与所述屏蔽层的外侧壁对准。
3.根据权利要求1所述的半导体封装件，其中：
所述封端绝缘层具有由所述屏蔽层覆盖的第一封端侧壁以及在所述侧向突出封端突出部处的第二封端侧壁，且
所述第二封端侧壁的表面粗糙度大于所述第一封端侧壁的表面粗糙度。
4.根据权利要求1所述的半导体封装件，其中：
所述屏蔽层具有与所述封端突出部间隔开的第一屏蔽侧壁以及邻近于所述封端突出部的第二屏蔽侧壁，且
所述第二屏蔽侧壁的表面粗糙度大于所述第一屏蔽侧壁的表面粗糙度。
5.根据权利要求1所述的半导体封装件，其中所述屏蔽层的下部部分在所述侧向突出封端突出部上侧向突出。
6.根据权利要求1所述的半导体封装件，其中：
所述屏蔽层包含：
第一屏蔽层，邻近于所述封端绝缘层，以及
第二屏蔽层，在所述第一屏蔽层上且与所述封端绝缘层间隔开，且
所述第一屏蔽层包含与所述第二屏蔽层中所包含的金属不同的金属。
7.根据权利要求6所述的半导体封装件，其中所述第一屏蔽层的下部部分在所述侧向突出封端突出部上侧向突出，且接触所述第二屏蔽层的下表面。
8.根据权利要求1所述的半导体封装件，更包括：
基底，在所述第一半导体芯片的所述下表面上，且相对于所述第一半导体芯片的所述侧壁朝外突出；以及
模制层，在所述基底的上表面上且在所述第一半导体芯片的所述侧壁上，
其中：
所述封端绝缘层接触所述基底的侧壁和所述模制层，且
所述基底为再分布层或封装基底。
9.根据权利要求1所述的半导体封装件，更包括：
上部封装基底，在所述第一半导体芯片上；
第二半导体芯片，在所述上部封装基底上；以及
模制层，在所述第二半导体芯片和所述上部封装基底上，
其中所述封端绝缘层接触所述上部封装基底的侧壁和所述模制层。
10.根据权利要求9所述的半导体封装件，其中所述封端绝缘层在所述上部封装基底与所述第一半导体芯片之间延伸。
11.根据权利要求9所述的半导体封装件，更包括：
下部封装基底，在所述第一半导体芯片的所述下表面上；以及
封装连接结构，将所述上部封装基底与所述下部封装基底电连接，
其中所述封端绝缘层接触所述封装连接结构的侧壁。
12.根据权利要求9所述的半导体封装件，更包括：
再分布层，在所述第一半导体芯片的所述下表面上；
连接基底，在所述再分布层上；以及
封装连接结构，延伸穿过所述连接基底，且将所述上部封装基底与所述连接基底电连接，
其中所述封端绝缘层延伸以接触所述封装连接结构的侧壁。
13.根据权利要求1所述的半导体封装件，更包括：
基底，在所述第一半导体芯片的所述下表面上，且相对于所述第一半导体芯片的所述侧壁朝外突出；以及
模制层，覆盖所述基底的上表面和所述屏蔽层的侧壁，
其中所述基底是再分布层或封装基底。
14.根据权利要求13所述的半导体封装件，其中所述模制层接触所述封端绝缘层的所述侧向突出封端突出部。
15.根据权利要求13所述的半导体封装件，更包括：
上部再分布图案，在所述模制层上且电连接到所述基底；以及
上部半导体封装件，在所述上部再分布图案上且电连接到所述上部再分布图案。
16.一种半导体封装件，包括：
第一半导体芯片，具有上表面、与所述上表面相对的下表面以及在所述上表面与所述下表面之间的侧壁；以及
封端绝缘层，覆盖所述第一半导体芯片的所述上表面和所述侧壁，
其中：
所述封端绝缘层具有第一封端侧壁和第二封端侧壁，所述第二封端侧壁在所述第一封端侧壁下方以使得所述第二封端侧壁邻近于所述第一半导体芯片的所述下表面，且
所述第二封端侧壁的表面粗糙度大于所述第一封端侧壁的表面粗糙度。
17.根据权利要求16所述的半导体封装件，更包括所述封端绝缘层上的屏蔽层，
其中所述封端绝缘层的下部部分侧向突出且接触所述屏蔽层的下表面。
18.根据权利要求16所述的半导体封装件，更包括：
上部封装基底，在所述第一半导体芯片上；
第二半导体芯片，在所述上部封装基底上；以及
模制层，覆盖所述第二半导体芯片和所述上部封装基底，
其中所述封端绝缘层接触所述上部封装基底的侧壁和所述模制层。
19.根据权利要求18所述的半导体封装件，其中所述封端绝缘层在所述上部封装基底与所述第一半导体芯片之间延伸。
20.根据权利要求18所述的半导体封装件，更包括：
下部封装基底，在所述第一半导体芯片的所述下表面上；以及
封装连接结构，将所述上部封装基底与所述下部封装基底电连接，
其中所述封端绝缘层接触所述封装连接结构的侧壁。
21.一种半导体封装件，包括：
第一半导体芯片，具有上表面、与所述上表面相对的下表面以及在所述上表面与所述下表面之间的侧壁；
封端绝缘层，在所述第一半导体芯片的所述上表面和所述侧壁上；以及
屏蔽层，在所述封端绝缘层上，
其中所述封端绝缘层的下部外侧壁与所述屏蔽层的下部外侧壁垂直对准。
22.根据权利要求21所述的半导体封装件，更包括边缘芯片导电图案，所述边缘芯片导电图案在所述第一半导体芯片的所述下表面的边缘上且与所述屏蔽层间隔开，
其中所述封端绝缘层在所述屏蔽层与所述边缘芯片导电图案之间。
23.根据权利要求21所述的半导体封装件，其中所述封端绝缘层的下部部分侧向突出，且接触所述屏蔽层的下表面。
24.根据权利要求21所述的半导体封装件，其中：
所述封端绝缘层包含在其所述下部外侧壁上的上部外侧壁，且
所述封端绝缘层的所述下部外侧壁的表面粗糙度大于所述封端绝缘层的所述上部外侧壁的表面粗糙度。
25.根据权利要求21所述的半导体封装件，其中：
所述屏蔽层包含在其所述下部外侧壁上的上部外侧壁，且
所述屏蔽层的所述下部外侧壁的表面粗糙度大于所述屏蔽层的所述上部外侧壁的表面粗糙度。
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