TW202038406A - 半導體封裝件 - Google Patents

半導體封裝件 Download PDF

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Publication number
TW202038406A
TW202038406A TW108147558A TW108147558A TW202038406A TW 202038406 A TW202038406 A TW 202038406A TW 108147558 A TW108147558 A TW 108147558A TW 108147558 A TW108147558 A TW 108147558A TW 202038406 A TW202038406 A TW 202038406A
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Taiwan
Prior art keywords
layer
insulating layer
semiconductor package
side wall
semiconductor
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TW108147558A
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English (en)
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TWI809234B (zh
Inventor
閔丙國
姜允熙
宋旼友
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南韓商三星電子股份有限公司
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Publication of TW202038406A publication Critical patent/TW202038406A/zh
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Abstract

一種半導體封裝件，包含：第一半導體晶片，具有上表面、與上表面相對的下表面以及在上表面與下表面之間的側壁；封端絕緣層，覆蓋第一半導體晶片的上表面和側壁；以及屏蔽層，在封端絕緣層上，其中封端絕緣層的下部部分包含接觸屏蔽層的下表面的側向突出封端突出部。

Description

半導體封裝件
本揭露的實例實施例是關於一種半導體封裝件。
半導體封裝件可以使積體電路裝置適用於電子裝置的形式來實施。舉例來說，半導體封裝件可具有其中半導體晶片安裝在印刷電路板（printed circuit board，PCB）上且結合線和/或凸塊將半導體晶片與PCB電連接的結構。
實施例可通過提供一種半導體封裝件來實現，所述半導體封裝件包含第一半導體晶片，具有上表面、與上表面相對的下表面以及在上表面與下表面之間的側壁；封端絕緣層，覆蓋第一半導體晶片的上表面及側壁；以及屏蔽層，在封端絕緣層上，其中封端絕緣層的下部部分包含接觸屏蔽層的下表面的側向突出封端突出部。
實施例可通過提供一種半導體封裝件來實現，所述半導體封裝件包含：第一半導體晶片，具有上表面、與上表面相對的下表面以及在上表面與下表面之間的側壁；以及封端絕緣層，覆蓋第一半導體晶片的上表面和側壁，其中封端絕緣層具有第一封端側壁和第二封端側壁，所述第二封端側壁在第一封端側壁下方以使得第二封端側壁鄰近於第一半導體晶片的下表面，且第二封端側壁的表面粗糙度大於第一封端側壁的表面粗糙度。
實施例可通過提供一種半導體封裝件來實現，所述半導體封裝件包含：第一半導體晶片，具有上表面、與上表面相對的下表面以及在上表面與下表面之間的側壁；封端絕緣層，在第一半導體晶片的上表面和側壁上；以及屏蔽層，在封端絕緣層上，其中封端絕緣層的下部外側壁與屏蔽層的下部外側壁垂直對準。
圖1示出根據實例實施例的半導體封裝件的立體圖。圖2A示出沿圖1的線I-I'截取的剖面視圖。圖2B示出根據實例實施例的半導體封裝件的剖面視圖。圖3A、圖3B以及圖3C示出圖2A的部分‘P1’的放大視圖。圖4示出圖3A的部分‘P2’的放大視圖。
參考圖1和圖2A，根據實例實施例的半導體封裝件100可包含半導體晶片10。半導體晶片10可包含例如系統大規模積體（large scale integration，ISI）；邏輯電路；影像感測器，例如CMOS影像感測器（CMOS image sensor，CIS）；記憶體裝置，例如閃存、DRAM、SRAM、EEPROM、PRAM、MRAM、ReRAM、高帶寬記憶體（high bandwidth memory，HBM）或混合記憶體立方體（hybrid memory cubic，HMC）；或微機電系統（microelectromechanical system，MEMS）。如本文中所使用，術語“或”不是排它性術語，例如“A或B”可包含A、B或A和B。
參考圖2A，晶片保護層14可覆蓋半導體晶片10的（例如下）表面。晶片保護層14可由絕緣材料形成，例如氮化矽或聚醯亞胺。彼此間隔開的晶片導電圖案12可在半導體晶片10的下表面與晶片保護層14之間。晶片導電圖案12可包含例如鋁、銅、金、錫或氮化鈦。晶片導電圖案12中的每一個可由單個層或多個層形成。外部連接端子16可分別穿過晶片保護層14以連接到晶片導電圖案12。外部連接端子16可各自包含例如導電凸塊、導電柱、焊料層或焊球。
參考圖1和圖2A，封端絕緣層20可覆蓋半導體晶片10的表面（例如與下表面相對的上表面）和側壁（例如四個側壁）。舉例來說，封端絕緣層20可覆蓋半導體晶片10的五個表面。屏蔽層30可在封端絕緣層20上。屏蔽層30可覆蓋封端絕緣層20的上表面和一個或多個側壁。半導體封裝件100可以是一種扇入型晶圓級封裝。
參考圖3A和圖4，封端絕緣層20可包含覆蓋（或接觸，例如直接接觸）屏蔽層30的下表面的側向突出封端突出部20p。封端絕緣層20的下表面可與晶片保護層14的下表面共面。封端絕緣層20可具有在側向突出封端突出部20p上方的第一封端側壁20s1和在第一封端側壁20s1下方的第二封端側壁20s2。第二封端側壁20s2可對應於或可以是側向突出封端突出部20p的側壁。第二封端側壁20s2的表面粗糙度可大於第一封端側壁20s1的表面粗糙度。屏蔽層30的下部部分可由側向突出封端突出部20p封閉或覆蓋，且當半導體封裝件100安裝在板基底上時，可阻擋屏蔽層30與鄰近導電圖案之間的非所要接觸。
封端絕緣層20可具有例如約1微米到約20微米的厚度。封端絕緣層20可包含例如氧化鋁層或氧化矽層的無機層，或例如環氧樹脂或聚胺酯的含聚合物層，且可具有單層或多層結構。當封端絕緣層20由例如氧化鋁層或氧化矽層的無機層形成時，封端絕緣層20可通過沉積製程來形成，例如濺射製程、物理氣相沉積（physical vapor deposition，PVD）、化學氣相沉積（chemical vapor deposition，CVD）製程或原子層沉積（atomic layer deposition，ALD）製程。舉例來說，當封端絕緣層20通過ALD製程形成時，無論位置如何，封端絕緣層20可共形地形成為具有均勻厚度。另外，當封端絕緣層20由含聚合物層形成時，封端絕緣層20可通過噴塗乾燥製程形成。
在實施方案中，參考圖4，封端絕緣層20可包含含聚合物層20a以及分散於含聚合物層20a中的絕緣顆粒20b。含聚合物層20a可包含例如環氧樹脂或聚胺酯，且絕緣顆粒20b可包含無機材料，例如氧化矽或氧化鋁。絕緣顆粒20b可彼此接觸地分佈於含聚合物層20a中。絕緣顆粒20b可彼此接觸地分佈，且可提高散熱效果。
氧化矽層或氧化鋁層可具有絕緣特性和相對優良的熱導率。舉例來說，當封端絕緣層20由氧化矽或氧化鋁形成或絕緣顆粒20b由氧化矽或氧化鋁形成時，可提高散熱效果。
在實施方案中，再次參考圖3A，屏蔽層30可具有例如約1微米到約10微米的厚度。屏蔽層30可包含單層或多層結構，且可包含金屬，例如不銹鋼（stainless steel，SUS）、銅或鎳。屏蔽層30可通過沉積製程形成，例如濺射製程、PVD製程、CVD製程或ALD製程。屏蔽層30可具有鄰近於半導體晶片10的側壁或與所述側壁大致對準的第一屏蔽側壁30s1，以及鄰近於晶片保護層14的側壁或與所述側壁大致對準且在第一屏蔽側壁30s1下方的第二屏蔽側壁30s2。第二屏蔽側壁30s2的表面粗糙度可大於第一屏蔽側壁30s1的表面粗糙度。第二屏蔽側壁30s2可與第二封端側壁20s2垂直對準。
在實施方案中，參考圖3B，屏蔽層30的下部部分可側向突出。舉例來說，屏蔽層30可包含側向突出屏蔽突出部30p。屏蔽層30的第二屏蔽側壁30s2可對應於或可以是側向突出屏蔽突出部30p的側壁。
在實施方案中，參考圖3C，屏蔽層30可包含第一屏蔽層30a和第二屏蔽層30b的雙層。第一屏蔽層30a可包含與第二屏蔽層30b的金屬不同的金屬。第一屏蔽層30a可包含側向突出第一屏蔽突出部30ap。在實施方案中，屏蔽層30可具有三層或大於三層的結構。雙層或多層結構的屏蔽層30可有助於提高電磁干擾（electromagnetic interference，EMI）屏蔽效果。
在實施方案中，參考圖2B，半導體封裝件100a可包含在半導體晶片10的下表面的邊緣（例如外側）上的邊緣晶片導電圖案12p。邊緣晶片導電圖案12p的側壁可與半導體晶片10的側壁和晶片保護層14的側壁垂直對準。邊緣晶片導電圖案12p可通過封端絕緣層20來與屏蔽層30絕緣。除了邊緣晶片導電圖案12p以外，半導體封裝件100a的其它組件可與參考圖3A到圖3C以及圖4所描述的相同或類似。
參考圖2A和圖2B，半導體封裝件100和半導體封裝件100a可具有由封端絕緣層20保護的上表面和側壁。半導體封裝件100和半導體封裝件100a可通過屏蔽層30具有EMI屏蔽功能。屏蔽層30可通過封端絕緣層20與邊緣晶片導電圖案12p間隔開，且可增加晶片導電圖案12和晶片導電圖案12p的設計自由度。在實施方案中，封端絕緣層20可包含例如氧化鋁層和/或氧化矽層，且可提高散熱效果。封端絕緣層20可包含接觸屏蔽層30的下表面的側向突出封端突出部20p，且當半導體封裝件100和半導體封裝件100a安裝在板基底上時，可防止半導體封裝件100和半導體封裝件100a與鄰近導電圖案短接（shorting）。舉例來說，可防止不良安裝，且可提供具有改善的可靠性和耐久性的半導體封裝件。
圖5A、圖5B以及圖5C示出製造根據實例實施例的具有圖2A的剖面的半導體封裝件的方法中的階段的剖面視圖。
參考圖5A，可製造初步半導體封裝件100p。初步半導體封裝件100p可具有不包含或不具有圖2A的半導體封裝件100中的封端絕緣層20和屏蔽層30的結構。初步半導體封裝件100p可通過扇入型晶圓級封裝的製造方法形成。可製備載體基底50。載體基底50可包含容納部分51。在實施方案中，如圖5A中所示出，可包含一個容納部分51。在實施方案中，可在載體基底50中佈置多個容納部分51。初步半導體封裝件100p可定位於載體基底50上。在那時，附接到半導體晶片10的下表面的外部連接端子16可插入到容納部分51中，且晶片保護層14的邊緣可接觸載體基底50。
參考圖5B，封端絕緣層20可形成為覆蓋半導體晶片10的上表面和側壁。封端絕緣層20可在載體基底50的上表面上連續形成。封端絕緣層20可通過執行例如濺射製程、PVD製程、CVD製程或ALD製程的沉積製程由無機層來形成。在實施方案中，封端絕緣層20可通過噴塗乾燥製程由含聚合物層來形成。屏蔽層30可在封端絕緣層20上形成。屏蔽層30可通過執行例如濺射製程、PVD製程、CVD製程或ALD製程的沉積製程由例如SUS、銅或鎳的金屬層來形成。屏蔽層30可在載體基底50的上表面以及半導體晶片10的上表面和側壁上（例如在封端絕緣層20上）形成。
參考圖5C，可從載體基底50提起半導體晶片10。舉例來說，半導體晶片10上的封端絕緣層20和屏蔽層30可與載體基底50上的封端絕緣層20和屏蔽層30分離。鄰近於半導體晶片10的下表面的封端絕緣層20和屏蔽層30可與圖3B中所示的封端絕緣層和屏蔽層類似地側向突出。在實施方案中，可將突出部（圖3B的側向突出封端突出部20p和圖3B的側向突出屏蔽突出部30p）拋光，從而移除突出部的至少部分。舉例來說，可如圖3A中所示來移除側向突出屏蔽突出部30p，且可減小側向突出封端突出部20p的大小。在實施方案中，如圖3A或圖3B中所示，可相對增大封端絕緣層20的第二封端側壁20s2的表面粗糙度和屏蔽層30的第二屏蔽側壁30s2的表面粗糙度。取決於側向突出屏蔽突出部30p和/或側向突出封端突出部20p的拋光/移除量，所得結構可變成圖3A或圖3B中所示的結構。在實施方案中，在從載體基底50提起半導體晶片10之前，可使用雷射或鑽孔機來切掉封端絕緣層20和屏蔽層30。可通過這類製程來製造圖2A的半導體封裝件100。
圖6示出根據實例實施例的半導體封裝件的剖面視圖。
參考圖6，半導體封裝件101可以是扇出型晶圓級封裝的實例。舉例來說，半導體封裝件101可具有先晶片（chip-first）或先模製（mold-first）的扇出型晶圓級封裝結構。半導體封裝件101可更包含電連接到半導體晶片10的再分佈層40。再分佈圖案41可在再分佈層40中。再分佈圖案41中的一些可穿過晶片保護層14以接觸半導體晶片10的晶片導電圖案12。再分佈圖案41可將半導體晶片10的晶片導電圖案12與外部連接端子16電連接。
再分佈圖案41可包含金屬，例如銅或鋁。再分佈層40可從半導體晶片10的側壁且在所述側壁下方朝外突出。模製層18可覆蓋再分佈層40和半導體晶片10。模製層18的下表面（例如面向再分佈層的表面）可與晶片保護層14的下表面共面。模製層18可包含絕緣樹脂，例如環氧模製化合物（epoxy molding compound，EMC）。模製層18可更包含填充劑。填充劑可分散於絕緣樹脂中。填充劑可包含例如氧化矽。
模製層18的上表面和側壁以及再分佈層40的側壁可由封端絕緣層20覆蓋。封端絕緣層20的上表面和側壁可由屏蔽層30覆蓋。封端絕緣層20的下部部分可側向突出，且可接觸屏蔽層30的下表面。封端絕緣層20和屏蔽層30的詳細結構可與參考圖3A到圖3C以及圖4所描述的相同或類似。在實施方案中，在半導體封裝件101中，一個半導體晶片10可在再分佈層40上。在實施方案中，兩個或大於兩個半導體晶片10可並排於再分佈層40上。
半導體封裝件101可如下製造。半導體晶片10可在額外載體基底上，且隨後可形成模製層18以覆蓋半導體晶片10。在半導體晶片10和模製層18與額外載體基底分離之後，可在半導體晶片10的下表面和模製層18的下表面上形成再分佈層40以製造初步半導體封裝件。初步半導體封裝件可定位於載體基底50上，替代圖5A的初步半導體封裝件100p。其後，可執行如參考圖5B和圖5C所描述的後續製程以形成封端絕緣層20和屏蔽層30。
圖7示出根據實例實施例的半導體封裝件的剖面視圖。
參考圖7，半導體封裝件102可包含封裝基底42。半導體晶片10可通過倒裝晶片結合方法使用內部連接結構15安裝在封裝基底42上。封裝基底42可以是具有單層或多層佈線結構的印刷電路板（PCB）基底。內部連接結構15可包含例如導電凸塊、導電柱、焊料層或焊球。導電凸塊和導電柱可包含例如銅。焊料層和焊球可包含例如錫或鉛。球焊盤43可在封裝基底42的下表面上。外部連接端子16可結合到球焊盤43。封裝基底42可從半導體晶片10的側壁且在所述側壁下方朝外突出。模製層18可覆蓋半導體晶片10的側壁和封裝基底42的上表面。模製層18的上表面可與半導體晶片10的上表面共面。模製層18可延伸以填充半導體晶片10與封裝基底42之間的空間。
封端絕緣層20可接觸半導體晶片10的上表面、模製層18的上表面和側壁以及封裝基底42的側壁。封端絕緣層20的上表面和側壁可由屏蔽層30覆蓋。封端絕緣層20的下部部分可側向突出以接觸屏蔽層30的下表面。封端絕緣層20和屏蔽層30的詳細結構可與參考圖3A到圖3C以及圖4所描述的相同或類似。在實施方案中，在半導體封裝件102中，一個半導體晶片10可在封裝基底42上。在實施方案中，兩個或大於兩個半導體晶片10可並排安置或垂直堆疊在封裝基底42上。
半導體封裝件102可如下製造。在製造除了圖7的結構中的封端絕緣層20和屏蔽層30以外或不包含所述封端絕緣層和所述屏蔽層的結構的初步半導體封裝件之後，初步半導體封裝件可定位於載體基底50上，替代圖5A的初步半導體封裝件100p。其後，可執行如參考圖5B和圖5C所描述的後續製程。
圖8示出根據實例實施例的半導體封裝件的剖面視圖。
參考圖8，半導體封裝件103可以是層疊封裝結構的實例。半導體封裝件103可包含下部半導體封裝件LPK和安裝在下部半導體封裝件LPK上的上部半導體封裝件UPK。
下部半導體封裝件LPK可包含下部封裝基底42以及安裝在下部封裝基底42上的下部半導體晶片10。下部封裝基底42可以是具有單層或多層佈線結構的PCB基底。下部半導體晶片10可通過倒裝晶片結合方法使用內部連接結構15安裝在下部封裝基底42上。外部連接端子16可粘附到下部封裝基底42。內部連接結構15和外部連接端子16可各自包含例如導電凸塊、導電柱、焊料層或焊球。下部模製層18可覆蓋下部封裝基底42的上表面和下部半導體晶片10。下部模製層18的上表面可與下部半導體晶片10的上表面共面。
上部半導體封裝件UPK可包含上部封裝基底54以及安裝在上部封裝基底54上的上部半導體晶片56。上部半導體晶片56可堆疊在上部封裝基底54上，且可通過焊線結合方法連接到上部封裝基底54。上部半導體晶片56和上部封裝基底54可由上部模製層58覆蓋。下部模製層18和上部模製層58可各自包含絕緣樹脂，例如環氧模製化合物（EMC）。下部模製層18和上部模製層58可更包含填充劑。填充劑可分散於絕緣樹脂中。填充劑可包含例如氧化矽。
上部半導體封裝件UPK可通過封裝連接結構52電連接到下部半導體封裝件LPK。封裝連接結構52可將下部封裝基底42與上部封裝基底54電連接。下部模製層18可包含開口，封裝連接結構52插入到所述開口中。封裝連接結構52可包含例如導電凸塊、導電柱、焊料層或焊料凸塊。
上部封裝基底54可與下部半導體晶片10和下部模製層18間隔開。熱界面材料層60可在上部封裝基底54與下部半導體晶片10之間。熱界面材料層60可包含例如散熱膏或熱環氧樹脂。在實施方案中，散熱膏或熱環氧樹脂可包含金屬固體顆粒。
上部半導體封裝件UPK和下部半導體封裝件LPK可由封端絕緣層20覆蓋。封端絕緣層20可接觸上部模製層58的上表面和側壁、上部封裝基底54的側壁、下部模製層18的側壁以及下部封裝基底42的側壁。封端絕緣層20可在下部模製層18與上部封裝基底54之間延伸。封端絕緣層20可延伸以接觸封裝連接結構52的側壁和熱界面材料層60。
封端絕緣層20的上表面和側壁可由屏蔽層30覆蓋。封端絕緣層20的下部部分可側向突出以接觸屏蔽層30的下表面。封端絕緣層20和屏蔽層30的詳細結構可與參考圖3A到圖3C以及圖4所描述的相同或類似。
半導體封裝件103可如下製造。在製造具有除了圖8的結構中的封端絕緣層20和屏蔽層30以外的結構的初步半導體封裝件之後，初步半導體封裝件可定位於載體基底50上，替代圖5A的初步半導體封裝件100p。其後，可執行如參考圖5B和圖5C所描述的後續製程。封端絕緣層20可通過ALD製程共形地形成。在那時，用於形成封端絕緣層20的源氣可在上部半導體封裝件UPK與下部半導體封裝件LPK之間擴散，以使得封端絕緣層20可填充上部半導體封裝件UPK與下部半導體封裝件LPK之間的空間。
圖9示出根據實例實施例的半導體封裝件的剖面視圖。
參考圖9，半導體封裝件104可以是層疊封裝結構的實例。半導體封裝件104可包含下部半導體封裝件LPK以及安裝在下部半導體封裝件LPK上的上部半導體封裝件UPK。
下部半導體封裝件LPK可包含再分佈層40以及安裝於再分佈層40上的半導體晶片10。包含腔室72的連接基底70可在再分佈層40上。在實施方案中，腔室72可在連接基底70中的中心部分中，且連接基底70在平面視圖中可具有矩形環形狀。連接基底70可包含連接佈線結構71和連接絕緣層73。連接佈線結構71可包含穿過連接絕緣層73的導通孔塞、導電佈線線路以及導電墊。連接絕緣層73可各自包含熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；或具有增強材料（例如玻璃纖維（玻璃布或玻璃織物））或無機填充劑浸漬於熱固性樹脂和熱塑性樹脂中的樹脂，如預浸料、味之素（ajinomoto）積層膜（build-up film，BF）、雙馬來醯亞胺三嗪（bismaleimide triazine，BT）或可光成像介電（photo imageable dielectric，PLD）樹脂。
連接佈線結構71可電連接到再分佈層40中的再分佈圖案41。下部半導體晶片10可插入到腔室72中。下部半導體晶片10可與腔室72的內側壁間隔開。下部模製層18可填充下部半導體晶片10與腔室72的內側壁之間的空間。下部模製層18可接觸再分佈層40的上表面。下部模製層18可延伸以覆蓋下部半導體晶片10的上表面。下部模製層18還可延伸以覆蓋連接基底70的上表面。下部模製層18的側壁可與連接基底70的側壁和再分佈層40的側壁垂直對準。
上部半導體封裝件UPK可包含上部封裝基底54以及安裝在上部封裝基底54上的上部半導體晶片56。上部半導體晶片56可通過倒裝晶片結合方法安裝在上部封裝基底54上。上部模製層58可覆蓋上部封裝基底54的上表面和上部半導體晶片56的側壁。上部模製層58可填充上部半導體晶片56與上部封裝基底54之間的空間。上部模製層58的上表面可與上部半導體晶片56的上表面共面。
上部半導體封裝件UPK可與下部半導體封裝件LPK間隔開。上部半導體封裝件UPK可通過封裝連接結構52電連接到下部半導體封裝件LPK。封裝連接結構52可將連接基底70與上部封裝基底54電連接。下部模製層18可包含開口，封裝連接結構52插入到所述開口中。封裝連接結構52可各自包含例如導電凸塊、導電柱、焊料層或焊球。
上部半導體封裝件UPK和下部半導體封裝件LPK可由封端絕緣層20覆蓋。封端絕緣層20可接觸上部模製層58的上表面和側壁、上部半導體晶片56的上表面、上部封裝基底54的側壁、下部模製層18的側壁、連接基底70的側壁以及再分佈層40的側壁。
封端絕緣層20可在下部模製層18與上部封裝基底54之間延伸。封端絕緣層20可延伸以接觸封裝連接結構52的側壁。無論位置如何，封端絕緣層20可具有恒定厚度。在封端絕緣層20中可存在第一氣隙區域V1和第二氣隙區域V2。第一氣隙區域V1可存在於連接基底70與上部封裝基底54之間或鄰近封裝連接結構52之間。第二氣隙區域V2可存在於下部半導體晶片10與上部封裝基底54之間。凹部區域R1可在上部半導體封裝件UPK的邊緣與下部半導體封裝件LPK的邊緣之間的封端絕緣層20中。
屏蔽層30可覆蓋封端絕緣層20的上表面和側壁。屏蔽層30可包含填充凹部區域R1的中間屏蔽突出部30sp。封端絕緣層20的下部部分可側向突出以接觸屏蔽層30的下表面。封端絕緣層20和屏蔽層30的詳細結構可與參考圖3A到圖3B以及圖4所描述的相同或類似。
半導體封裝件104可如下製造。在製造具有除了圖9的結構中的封端絕緣層20和屏蔽層30以外的結構的初步半導體封裝件之後，初步半導體封裝件可定位於載體基底50上，替代圖5A的初步半導體封裝件100p。其後，可執行如參考圖5B和圖5C所描述的後續製程。封端絕緣層20可通過ALD製程共形地形成。在那時，用於形成封端絕緣層20的源氣可在上部半導體封裝件UPK與下部半導體封裝件LPK之間擴散，以使得封端絕緣層20可插入在上部半導體封裝件UPK與下部半導體封裝件LPK之間。另外，在那時，可形成第一氣隙區域V1和第二氣隙區域V2。
圖10示出根據實例實施例的半導體封裝件的剖面視圖。圖11示出圖10的部分‘P1’的放大視圖。
參考圖10和圖11，在半導體封裝件105中，可省略圖2A的屏蔽層30。半導體晶片10的上表面和側壁可僅由封端絕緣層20覆蓋。舉例來說，圖2A的側向突出封端突出部20p可以不存在於封端絕緣層20的下部部分處。封端絕緣層20可包含第一封端側壁20s1以及在第一封端側壁20s1下方的第二封端側壁20s2。第二封端側壁20s2的表面粗糙度可大於第一封端側壁20s1的表面粗糙度。不包含屏蔽層30的半導體封裝件的此結構可應用於圖6到圖9的半導體封裝件101、半導體封裝件102、半導體封裝件103以及半導體封裝件104。舉例來說，圖6到圖9的半導體封裝件101、半導體封裝件102、半導體封裝件103以及半導體封裝件104可以不包含屏蔽層30。在這種情況下，封端絕緣層20可以不包含圖2A的側向突出封端突出部20p，且封端絕緣層20的下部結構可與參考圖11所描述的相同或類似。
除了省略圖5C的屏蔽層30的形成以外，半導體封裝件105可通過執行與參考圖5A到圖5C所描述相同的製程來製造。
圖12示出根據實例實施例的半導體封裝件的剖面視圖。
參考圖12，半導體封裝件106可具有後晶片（chip-last）或先再分佈（RDL-first）的扇出型晶圓級封裝結構。舉例來說，半導體晶片10可在再分佈層40上。半導體晶片10的上表面和側壁可依序由封端絕緣層20和屏蔽層30覆蓋。封端絕緣層20和屏蔽層30可與參考圖1到圖4所描述的相同或類似。
多層再分佈圖案41可在再分佈層40中。再分佈圖案41中的一些可將外部連接端子16與接觸晶片導電圖案12的內部連接結構15電連接。內部連接結構15中的每一個可包含導電柱15a以及在導電柱15a下方的焊料層15b。導電柱15a可包含例如銅。焊料層15b可包含例如錫和/或鉛。因為內部連接結構15之間的間隔較窄，所以其中內部連接結構15包含導電柱15a和焊料層15b的結構可在防止電短路方面有利。再分佈層40可從半導體晶片10的側壁且在所述側壁下方朝外延伸。
半導體晶片10與再分佈層40之間的空間可用底部填充層17填充。底部填充層17可接觸封端絕緣層20，且可與屏蔽層30間隔開。屏蔽層30和再分佈層40可由模製層18覆蓋。模製層18可接觸封端絕緣層20的下部側壁（例如封端突出部的側壁）。相對於再分佈層40的上表面，模製層18的下表面可低於半導體晶片10的下表面和晶片保護層14的下表面。模製層18可接觸底部填充層17。半導體封裝件106的其它組件可與參考圖6所描述的相同或類似。
半導體封裝件106可如下製造。半導體晶片10可設置為通過參考圖5A、圖5B以及圖5C所描述的製程由封端絕緣層20和屏蔽層30來覆蓋。再分佈層40可在額外載體基底上形成，且半導體晶片10可安裝於再分佈層40上。其後，可形成底部填充層17和模製層18。
圖13示出根據實例實施例的半導體封裝件的剖面視圖。
參考圖13，半導體封裝件107可以是疊層封裝結構的實例。半導體封裝件107可包含下部半導體封裝件LPK以及安裝在下部半導體封裝件LPK上的上部半導體封裝件UPK。
下部半導體封裝件LPK可具有與圖12的半導體封裝件106類似的結構。舉例來說，下部半導體封裝件LPK可包含安裝在下部再分佈層40上的下部半導體晶片10。下部再分佈層40可包含下部再分佈圖案41。下部半導體晶片10的上表面和側壁可由封端絕緣層20和屏蔽層30覆蓋。屏蔽層30和下部再分佈層40可由下部模製層18覆蓋。上部再分佈層80可在下部模製層18上。上部再分佈層80可包含上部再分佈圖案81。通孔83可穿過下部模製層18以將上部再分佈層80與下部再分佈層40電連接。
上部半導體封裝件UPK可包含上部封裝基底54以及安裝在上部封裝基底54上的上部半導體晶片56。上部半導體晶片56可通過焊線結合方法連接到上部封裝基底54。上部半導體晶片56和上部封裝基底54可由上部模製層58覆蓋。上部半導體封裝件UPK可通過封裝連接結構52電連接到下部半導體封裝件LPK。舉例來說，封裝連接結構52可將上部再分佈層80與上部封裝基底54電連接。上部模製層58和下部模製層18可以不由封端絕緣層20和屏蔽層30覆蓋，且可暴露。半導體封裝件107的其它組件可與參考圖8和圖12所描述的相同或類似。
借助於總結和綜述，隨著電子行業的發展，已進行各種研究來改善半導體封裝件的可靠性和耐久性。
一個或多個實施例可提供一種半導體封裝件，所述半導體封裝件有助於防止與鄰近半導體封裝件短接（shorting），且因此可防止不良安裝，從而提供具有改善的可靠性和耐久性的半導體封裝件。
儘管可能沒有繪示一些剖面視圖的對應平面視圖和/或立體圖，但本文中所示出的裝置結構的剖面視圖提供對於沿兩個不同方向（如將在平面視圖中示出）和/或在三個不同方向上（如將在立體圖中示出）延伸的多個裝置結構的支持。兩個不同方向可以或可以不彼此正交。三個不同方向可包含可與兩個不同方向正交的第三方向。多個裝置結構可積體在同一電子裝置中。舉例來說，當裝置結構（例如記憶體單元結構或電晶體結構）以剖面視圖示出時，電子裝置可包含多個裝置結構（例如記憶體單元結構或電晶體結構），如將由電子裝置的平面視圖所示出。多個裝置結構可以陣列和/或二維圖案來佈置。
已在本文中揭露實例實施例，且儘管採用特定術語，但所述術語僅在一般性和描述性意義上使用並解釋，且並不出於限制的目的。在一些情況下，如對本領域的一般技術人員將顯而易見，截至本申請案提交時，除非另外特別指示，否則結合特定實施例描述的特徵、特性和/或元件可單獨使用或與結合其它實施例描述的特徵、特性和/或元件組合使用。因此，本領域的技術人員應理解，可在不脫離如以下申請專利範圍中所闡述的本發明的精神和範圍的情況下作出形式和細節的各種變化。
10:下部半導體晶片 12:晶片導電圖案 12p:邊緣晶片導電圖案 14:晶片保護層 15:內部連接結構 15a:導電柱 15b:焊料層 16:外部連接端子 17:底部填充層 18:模製層 20:封端絕緣層 20a:含聚合物層 20b:絕緣顆粒 20p:側向突出封端突出部 20s1:第一封端側壁 20s2:第二封端側壁 30:屏蔽層 30a:第一屏蔽層 30ap:側向突出第一屏蔽突出部 30b:第二屏蔽層 30p:側向突出屏蔽突出部 30s1:第一屏蔽側壁 30s2:第二屏蔽側壁 30sp:中間屏蔽突出部 40:再分佈層 41:再分佈圖案 42:封裝基底 43:球焊盤 50:載體基底 51:容納部分 52:封裝連接結構 54:上部封裝基底 56:上部半導體晶片 58:上部模製層 60:熱界面材料層 70:連接基底 71:連接佈線結構 72:腔室 73:連接絕緣層 80:上部再分佈層 81:上部再分佈圖案 83:通孔 100、100a、101、102、103、104、105、106、107:半導體封裝件 100p:初步半導體封裝件 I-I':線 LPK:下部半導體封裝件 P1、P2:部分 R1:凹部區域 UPK:上部半導體封裝件 V1:第一氣隙區域 V2:第二氣隙區域
通過參考附圖來詳細描述示範性實施例，特徵將對於本領域的技術人員顯而易見，在附圖中： 圖1示出根據實例實施例的半導體封裝件的立體圖。 圖2A示出沿圖1的線I-I'截取的剖面視圖。 圖2B示出根據實例實施例的半導體封裝件的剖面視圖。 圖3A、圖3B以及圖3C示出圖2A的部分‘P1’的放大視圖。 圖4示出圖3A的部分‘P2’的放大視圖。 圖5A、圖5B以及圖5C示出製造根據實例實施例的具有圖2A的剖面的半導體封裝件的方法中的階段的剖面視圖。 圖6示出根據實例實施例的半導體封裝件的剖面視圖。 圖7示出根據實例實施例的半導體封裝件的剖面視圖。 圖8示出根據實例實施例的半導體封裝件的剖面視圖。 圖9示出根據實例實施例的半導體封裝件的剖面視圖。 圖10示出根據實例實施例的半導體封裝件的剖面視圖。 圖11示出圖10的部分‘P1’的放大視圖。 圖12示出根據實例實施例的半導體封裝件的剖面視圖。 圖13示出根據實例實施例的半導體封裝件的剖面視圖。
10:下部半導體晶片
12:晶片導電圖案
14:晶片保護層
16:外部連接端子
20:封端絕緣層
30:屏蔽層
100:半導體封裝件
P1:部分

Claims (25)

  1. 一種半導體封裝件，包括： 第一半導體晶片，具有上表面、與所述上表面相對的下表面以及在所述上表面與所述下表面之間的側壁； 封端絕緣層，覆蓋所述第一半導體晶片的所述上表面和所述側壁；以及 屏蔽層，在所述封端絕緣層上， 其中，所述封端絕緣層的下部部分包含接觸所述屏蔽層的下表面的側向突出封端突出部。
  2. 如申請專利範圍第1項所述的半導體封裝件，其中所述封端絕緣層的所述下部部分的外側壁與所述屏蔽層的外側壁對準。
  3. 如申請專利範圍第1項所述的半導體封裝件，其中： 所述封端絕緣層具有由所述屏蔽層覆蓋的第一封端側壁以及在所述側向突出封端突出部處的第二封端側壁，且 所述第二封端側壁的表面粗糙度大於所述第一封端側壁的表面粗糙度。
  4. 如申請專利範圍第1項所述的半導體封裝件，其中： 所述屏蔽層具有與所述封端突出部間隔開的第一屏蔽側壁以及鄰近於所述封端突出部的第二屏蔽側壁，且 所述第二屏蔽側壁的表面粗糙度大於所述第一屏蔽側壁的表面粗糙度。
  5. 如申請專利範圍第1項所述的半導體封裝件，其中所述屏蔽層的下部部分在所述側向突出封端突出部上側向突出。
  6. 如申請專利範圍第1項所述的半導體封裝件，其中： 所述屏蔽層包含： 第一屏蔽層，鄰近於所述封端絕緣層，以及 第二屏蔽層，在所述第一屏蔽層上且與所述封端絕緣層間隔開，且 所述第一屏蔽層包含與所述第二屏蔽層中所包含的金屬不同的金屬。
  7. 如申請專利範圍第6項所述的半導體封裝件，其中所述第一屏蔽層的下部部分在所述側向突出封端突出部上側向突出，且接觸所述第二屏蔽層的下表面。
  8. 如申請專利範圍第1項所述的半導體封裝件，更包括： 基底，在所述第一半導體晶片的所述下表面上，且相對於所述第一半導體晶片的所述側壁朝外突出；以及 模製層，在所述基底的上表面上且在所述第一半導體晶片的所述側壁上， 其中： 所述封端絕緣層接觸所述基底的側壁和所述模製層，且 所述基底為再分佈層或封裝基底。
  9. 如申請專利範圍第1項所述的半導體封裝件，更包括： 上部封裝基底，在所述第一半導體晶片上； 第二半導體晶片，在所述上部封裝基底上；以及 模製層，在所述第二半導體晶片和所述上部封裝基底上， 其中所述封端絕緣層接觸所述上部封裝基底的側壁和所述模製層。
  10. 如申請專利範圍第9項所述的半導體封裝件，其中所述封端絕緣層在所述上部封裝基底與所述第一半導體晶片之間延伸。
  11. 如申請專利範圍第9項所述的半導體封裝件，更包括： 下部封裝基底，在所述第一半導體晶片的所述下表面上；以及 封裝連接結構，將所述上部封裝基底與所述下部封裝基底電連接， 其中所述封端絕緣層接觸所述封裝連接結構的側壁。
  12. 如申請專利範圍第9項所述的半導體封裝件，更包括： 再分佈層，在所述第一半導體晶片的所述下表面上； 連接基底，在所述再分佈層上；以及 封裝連接結構，延伸穿過所述連接基底，且將所述上部封裝基底與所述連接基底電連接， 其中所述封端絕緣層延伸以接觸所述封裝連接結構的側壁。
  13. 如申請專利範圍第1項所述的半導體封裝件，更包括 基底，在所述第一半導體晶片的所述下表面上，且相對於所述第一半導體晶片的所述側壁朝外突出；以及 模製層，覆蓋所述基底的上表面和所述屏蔽層的側壁， 其中所述基底是再分佈層或封裝基底。
  14. 如申請專利範圍第13項所述的半導體封裝件，其中所述模製層接觸所述封端絕緣層的所述側向突出封端突出部。
  15. 如申請專利範圍第13項所述的半導體封裝件，更包括： 上部再分佈圖案，在所述模製層上且電連接到所述基底；以及 上部半導體封裝件，在所述上部再分佈圖案上且電連接到所述上部再分佈圖案。
  16. 一種半導體封裝件，包括： 第一半導體晶片，具有上表面、與所述上表面相對的下表面以及在所述上表面與所述下表面之間的側壁；以及 封端絕緣層，覆蓋所述第一半導體晶片的所述上表面和所述側壁， 其中： 所述封端絕緣層具有第一封端側壁和第二封端側壁，所述第二封端側壁在所述第一封端側壁下方以使得所述第二封端側壁鄰近於所述第一半導體晶片的所述下表面，且 所述第二封端側壁的表面粗糙度大於所述第一封端側壁的表面粗糙度。
  17. 如申請專利範圍第16項所述的半導體封裝件，更包括所述封端絕緣層上的屏蔽層， 其中所述封端絕緣層的下部部分側向突出且接觸所述屏蔽層的下表面。
  18. 如申請專利範圍第16項所述的半導體封裝件，更包括： 上部封裝基底，在所述第一半導體晶片上； 第二半導體晶片，在所述上部封裝基底上；以及 模製層，覆蓋所述第二半導體晶片和所述上部封裝基底， 其中所述封端絕緣層接觸所述上部封裝基底的側壁和所述模製層。
  19. 如申請專利範圍第18項所述的半導體封裝件，其中所述封端絕緣層在所述上部封裝基底與所述第一半導體晶片之間延伸。
  20. 如申請專利範圍第18項所述的半導體封裝件，更包括： 下部封裝基底，在所述第一半導體晶片的所述下表面上；以及 封裝連接結構，將所述上部封裝基底與所述下部封裝基底電連接， 其中所述封端絕緣層接觸所述封裝連接結構的側壁。
  21. 一種半導體封裝件，包括： 第一半導體晶片，具有上表面、與所述上表面相對的下表面以及在所述上表面與所述下表面之間的側壁； 封端絕緣層，在所述第一半導體晶片的所述上表面和所述側壁上；以及 屏蔽層，在所述封端絕緣層上， 其中所述封端絕緣層的下部外側壁與所述屏蔽層的下部外側壁垂直對準。
  22. 如申請專利範圍第21項所述的半導體封裝件，更包括邊緣晶片導電圖案，所述邊緣晶片導電圖案在所述第一半導體晶片的所述下表面的邊緣上且與所述屏蔽層間隔開， 其中所述封端絕緣層在所述屏蔽層與所述邊緣晶片導電圖案之間。
  23. 如申請專利範圍第21項所述的半導體封裝件，其中所述封端絕緣層的下部部分側向突出，且接觸所述屏蔽層的下表面。
  24. 如申請專利範圍第21項所述的半導體封裝件，其中： 所述封端絕緣層包含在其所述下部外側壁上的上部外側壁，且 所述封端絕緣層的所述下部外側壁的表面粗糙度大於所述封端絕緣層的所述上部外側壁的表面粗糙度。
  25. 如申請專利範圍第21項所述的半導體封裝件，其中： 所述屏蔽層包含在其所述下部外側壁上的上部外側壁，且 所述屏蔽層的所述下部外側壁的表面粗糙度大於所述屏蔽層的所述上部外側壁的表面粗糙度。
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