CN108122862A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN108122862A
CN108122862A CN201710531531.7A CN201710531531A CN108122862A CN 108122862 A CN108122862 A CN 108122862A CN 201710531531 A CN201710531531 A CN 201710531531A CN 108122862 A CN108122862 A CN 108122862A
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electronic device
transfer box
semiconductor device
layer
moulding layer
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CN201710531531.7A
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CN108122862B (zh
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陈天赐
王圣民
王奕程
许文政
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置封装包括电子装置、传导框和第一模制层。所述传导框安置在所述电子装置上并且电连接到所述电子装置，并且所述传导框包括多个引线。所述第一模制层覆盖所述电子装置和所述传导框的一部分，并且安置在所述引线中的至少邻近的两者之间。

Description

半导体装置封装及其制造方法
技术领域
本发明涉及半导体装置封装及其制造方法，且更确切地说涉及包括电连接到传导框的电子装置的半导体装置封装及其制造方法。
背景技术
半导体装置封装可以包括可以产生电磁干扰(EMI)的在相对较高频率处操作的电子装置，例如，射频集成电路(RFIC)。当布局密度增大时且当半导体装置封装小型化时，EMI尤其会存在问题。此外，半导体装置封装的散热是另一个有关的问题。
发明内容
在一些实施例中，半导体装置封装包括电子装置、传导框和第一模制层。传导框安置在电子装置上且电连接到电子装置，并且传导框包括多个引线。第一模制层覆盖电子装置和传导框的一部分，并且安置在引线中的至少邻近的两者之间。
在一些实施例中，半导体装置封装包括电子装置、传导框和第一模制层。电子装置具有第一表面、与第一表面相对的第二表面以及多个横向侧面。传导框包括面向电子装置的第一表面的顶盖部分和围绕电子装置的横向侧面的横向部分。横向部分限定至少一个凹口，并且传导框电连接到电子装置。第一模制层囊封电子装置的横向侧面和第二表面的一部分、传导框的横向部分以及顶盖部分的一部分，并且填充到至少一个凹口中。
在一些实施例中，制造半导体装置封装的方法包括：提供包括多个引线的传导框；在传导框上安置电子装置，其中传导框覆盖电子装置的第一表面且围绕电子装置的横向侧面，并且电连接到电子装置；以及在电子装置和传导框上形成模制层，其中模制层形成于引线的至少邻近的两者之间。
附图说明
当结合附图阅读时，从以下具体实施方式最好地理解本发明的一些实施例的方面。应注意，各种结构可能未按比例绘制，且各种结构的尺寸可出于论述的清楚起见而任意增大或减小。
图1是根据本发明的一些实施例的半导体装置封装的仰视图；
图2是根据本发明的一些实施例的半导体装置封装的俯视图；
图3是根据本发明的一些实施例的半导体装置封装的侧视图；
图4是根据本发明的一些实施例的半导体装置封装的截面视图；
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H、图5I、图5J、图5K和图5L说明根据本发明的一些实施例的半导体装置封装的制造方法的实例；以及
图6是根据本发明的一些实施例的半导体装置封装的截面视图。
具体实施方式
以下揭露内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例来阐释本发明的某些方面。当然，这些组件和布置仅为实例并且并不意图为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或上的形成可以包括第一特征和第二特征直接接触地形成的实施例，且还可包括额外特征可在第一特征与第二特征之间形成使得第一特征与第二特征可不直接接触的实施例。另外，本发明可在各种实例中重复参考标号和/或字母。此重复是出于简单和清楚的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
除非另外说明，否则例如“上方”、“下方”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“高于”、“低于”、“上部”、“在……上”、“在……下”等等的空间描述是相对于图中所示的取向来指示的。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施方案可在空间上以任何取向或方式布置，其限制条件是本发明的实施例的优点不因此类布置而有偏差。
以下描述涉及半导体装置封装。在一些实施例中，半导体装置封装包括在具有模制层的传导框上囊封的一或多个电子装置。模制层覆盖电子装置，并且位于传导框的引线之间。在一些实施例中，传导框被配置为保形屏蔽件以用于减少EMI。在一些实施例中，传导框经配置以增强半导体装置封装的稳固性。在一些实施例中，传导框经配置以改善散热性能。以下描述还涉及制造半导体装置封装的方法，如下文所论述。
图1是根据本发明的一些实施例的半导体装置封装1的仰视图，图2是根据本发明的一些实施例的半导体装置封装1的俯视图，图3是根据本发明的一些实施例的半导体装置封装1的侧视图，以及图4是根据本发明的一些实施例的半导体装置封装1的截面视图。应注意，为了说明清楚起见，第一模制层32的一部分在图1的仰视图中未示出。如图1到4中所示，半导体装置封装1包括一或多个电子装置10、传导框20和第一模制层32。传导框20安置在电子装置10上并且电连接到电子装置10。传导框20包括引线22。第一模制层32覆盖电子装置10和传导框20的一部分，并且第一模制层32进一步安置在至少两个邻近引线22之间。在一些实施例中，第一模制层32的材料包括(但不限于)模制化合物，例如，环氧树脂或类似物。
在一些实施例中，电子装置10包括电子组件12和再分布层(RDL)14，所述再分布层(RDL)14在电子组件12的有源表面或前表面上并且电连接到电子组件12。在一些实施例中，电子组件12是具有形成于其中的集成电路的半导体裸片。在一些实施例中，电子组件12包括电连接到集成电路并且从钝化层12B中暴露的接触垫12A。RDL 14经配置以重新布置电子组件12的输入/输出(I/O)触点。第一绝热层13安置在钝化层12B上并且暴露接触垫12A。RDL14安置在第一绝缘层13上并且电连接到从第一绝缘层13中暴露的接触垫12A。在一些实施例中，第二绝缘层15安置在第一绝缘层13上并且暴露RDL 14的一部分。
传导框(其还可被称为引线框)20由传导材料(例如，金属或金属合金)形成。借助于实例，传导材料可以包括(但不限于)铜合金、镍合金或类似物。传导框20可以通过锯切、冲压、蚀刻或其它合适的过程形成。在一些实施例中，传导框20作为整体结构形成，其中各部分彼此一体地形成。在一些实施例中，传导框20包括第一部分24和第二部分26。第一部分24面向电子装置10的第一表面(例如，后表面)101，并且第一部分24从第一模制层32中暴露。第二部分26在一端处连接到第一部分24且面向电子装置10的横向侧面10S，并且第二部分26在另一端处连接到引线22。在一些实施例中，第一部分24和第二部分26形成或限定容纳空间，其中第一部分24是被配置为遮盖电子装置10的传导框20的顶盖部分的板结构，并且第二部分26被配置为围绕电子装置10的横向侧面10S且从第一部分24向下延伸的横向部分。每个引线22的一端连接到第二部分26并且从第二部分26的端部向外延伸。引线22单独地布置，并且两个邻近引线22由凹口28间隔开。第一模制层32填充到传导框20的凹口28中，并且因此能够增强半导体装置封装1的结构稳固性和可靠性。在一些实施例中，每个引线22的一端从第一模制层32的横向侧面中暴露，并且可以大体上与第一模制层32的横向侧面共平面。
在一些实施例中，电子装置10的第一表面101通过粘合层11(例如，裸片附接膜(DAF))接合到传导框20的第一部分(顶盖部分)24。借助于实例，电子组件12附接到具有包括传导材料的粘合层11的传导框20。在一些实施例中，电子装置10进一步包括接地组件16。在一些实施例中，接地组件16是可以为RDL 14的一部分的接地衬垫。在一些实施例中，电子装置10进一步包括通过导线接合技术将传导框20连接到接地组件16的一或多个接合导线19，例如金属导线(例如，金或铜导线)。借助于实例，每个接合导线19的一端接合到传导框20的第二部分26，并且每个接合导线19的另一端接合到接地组件16。在一些实施例中，接合导线19连接到传导框20的第二部分26的一个侧面，但不限于此。接合导线19可以连接到传导框20的第二部分26的两个或大于两个侧面。在一些实施例中，第一模制层32囊封接合导线19以保护接合导线19。
在一些实施例中，半导体装置封装1进一步包括安置在RDL 14上并且电连接到RDL14的电触点18。电触点18被配置为外部连接器以电连接电子装置10和传导框20与另一电子装置(例如，电路板或另一封装)。在一些实施例中，电触点18是传导凸点，例如，焊接凸点、焊料球、焊料膏或类似物。在一些实施例中，第一模制层32进一步囊封电触点18中的每一个的一部分(例如，在图4中描绘的取向中的电触点18中的每一个的上部部分)以保护电触点18。在一些实施例中，凸点下金属层(UBM)17安置在每个相应的电触点18的下面。在一些实施例中，UBM 17包括用于增强电触点18与RDL 14之间的粘附的粘附层171，以及用于控制电触点18的形状的在粘附层171上的润湿层172。在一些实施例中，第一模制层32限定开口，在所述开口内安置UBM 17的相应的一者，并且在所述开口内安置电触点18的一部分。
在一些实施例中，传导框20通过接合导线19和接地组件16电连接到一或多个电触点18，并且一或多个电触点18可以进一步电连接到电路板的接地电路。在一些实施例中，接地组件16和一或多个电触点18还可以向电子组件12提供接地路径。电子装置10可以通过RDL 14和电触点18的另一子集电连接到电路板。
半导体装置封装1与晶片级芯片规模封装(WLCSP)兼容。传导框20围绕电子装置10的横向侧面10S，并且因此可以提供针对半导体装置封装1的侧壁保护。此外，包围横向侧面10S和电子装置10的第一表面(例如，背表面)101的传导框20可以被配置为保形屏蔽件以用于减少EMI。此外，半导体装置封装1可以通过电触点18电连接到另一个电子装置或半导体装置封装以形成系统级封装(SIP)或堆叠封装。此外，由金属、金属合金或具有足够的热导率的其它传导材料形成的传导框20也可以被配置为散热片以为电子装置10提供散热路径。
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H、图5I、图5J、图5K和图5L说明根据本发明的一些实施例的半导体装置封装1的制造方法的实例。
如图5A中所描绘，提供电子组件12。在一些实施例中，电子组件12包括以基板中的集成电路的形式形成的半导体组件，例如，晶片。在一些实施例中，每个电子组件12包括电连接到集成电路并且从钝化层12B中暴露的接触垫12A。
如图5B中所描绘，第一绝缘层13形成于钝化层12B上。图案化第一绝缘层13以暴露接触垫12A。在一些实施例中，第一绝缘层13的材料包括可为光敏的且可通过光刻图案化的有机材料，例如聚酰亚胺(PI)或聚苯并噁唑(PBO)。第一绝缘层13的材料可为另一有机或无机绝缘材料。
如图5C中所描绘，再分布层(RDL)14形成于第一绝缘层13上，并且电连接到从第一绝缘层13中暴露的接触垫12A。在一些实施例中，RDL 14的材料包括金属(例如，铜或铜合金)或另一合适的传导材料。在一些实施例中，RDL 14可以通过电镀、物理气相沉积(PVD)、化学气相沉积(CVD)或其它合适的过程形成。在一些实施例中，接地组件16与RDL 14一起形成。
如图5D中所描绘，第二绝缘层15形成于第一绝缘层13、RDL 14和接地组件16上。第二绝缘层15暴露RDL 14和接地组件16的一部分。在一些实施例中，第二绝缘层15的材料包括可为光敏的且可通过光刻图案化的有机材料，例如PI或PBO。第二绝缘层15的材料可为另一有机或无机绝缘材料。第二绝缘层15的材料可以与第一绝缘层13的材料相同或不同。
如图5E中所描绘，形成UBM 17以便UBM 17安置在RDL 14和接地组件16的暴露部分上。在一些实施例中，每个UBM 17的形成包括在RDL 14和接地组件16上形成粘附层171以及在粘附层171上形成润湿层172。在一些实施例中，粘附层171的材料包括(但不限于)钛、铬、氮化钛或类似物，并且润湿层172的材料包括(但不限于)铜、镍或类似物。
如图5F中所描绘，电触点18形成在RDL 14和接地组件16上，并且通过UBM 17电连接到RDL 14和接地组件16。在一些实施例中，电触点18包括(但不限于)传导凸块，例如，焊接凸点、焊料球、焊膏或类似物。在一些实施例中，电触点18的材料包括(但不限于)锡(Sn)、金(Au)或类似物。在一些实施例中，在电触点18上执行回焊过程。
如图5G中所描绘，电子组件12从第一表面(例如，后表面)101通过(例如)研磨变薄。如图5H中所描绘，第一表面101附接到临时承载架40，例如具有粘合层42(例如，黏合带)的玻璃承载架。在一些实施例中，从第二表面(例如，前表面)102中锯切电子组件12以形成若干单独的电子装置10。
如图5I中所描绘，提供连接到彼此的若干传导框20。在一些实施例中，传导框20安装在临时支撑件44上。在一些实施例中，传导框20中的每一个包括第一部分(顶盖部分)24、第二部分(横向部分)26和引线22。第二部分26在一端处连接到第一部分24，并且第二部分26在另一端处连接到引线22。在一些实施例中，第一部分24和第二部分26形成用于安置电子装置10的容纳空间。每个引线22的一端电连接到第二部分26且从第二部分26的端部向外延伸，并且每个引线22的另一端电连接到邻近传导框20的相应的引线22。引线22与形成于两个邻近引线22之间的凹口28(如图1中所示)分开地布置。电子装置10从临时承载架40(如图5H中所示)传送，并且接合到传导框20的相应者。在一些实施例中，单个电子装置10接合到相应的传导框20。在一些实施例中，两个或大于两个电子装置10可以接合到相应的传导框20。在一些实施例中，电子装置10的第一表面101接合到具有粘合层11(例如，DAF)的相应的传导框20的第一部分24。
如图5J中所描绘，接合导线19(例如,金导线)形成在电子装置10和传导框20上。在一些实施例中，每个接合导线19的一端接合到相应的传导框20，并且接合导线19的另一端接合到接地组件16使得电子装置10的接地组件16电连接到传导框20。
如图5K中所描绘，第一模制层32形成在电子装置10和传导框20上，并且填充到两个邻近引线22之间的凹口28中(如图1中所示)。在一些实施例中，第一模制层32囊封接合导线19以保护接合导线19。在一些实施例中，第一模制层32进一步囊封电触点18中的每一个的一部分(例如，在图5K中描绘的取向中的电触点18中的每一个的下部部分)以保护电触点18。
如图5L中所描绘，锯切传导框20和第一模制层32以形成单独的半导体装置封装。随后，从传导框20中释放临时支撑件44以形成如图1到4中所说明的半导体装置封装1。
本发明的半导体装置封装和制造方法不限于上述实施例，并且可以根据其它实施例实施。为了简化对本发明的各种实施例之间的比较的描述以及比较的便利性，用相同编号来标记以下实施例中的每一个中的相似组件。
图6是根据本发明的一些实施例的半导体装置封装2的截面视图。如图6中所示，与半导体装置封装1不同，半导体装置封装2的电子装置10为已封装到一定程度的半导体装置封装。在一些实施例中，电子装置10包括电子组件12、RDL 14和第二模制层34。RDL 14安置在电子组件12的有源表面或前表面上，并且电连接到电子组件12。第二模制层34囊封电子组件12和RDL 14的一部分。在一些实施例中，第二模制层34的材料包括(但不限于)模制化合物，例如，环氧树脂或类似物。第二模制层34的材料可以与第一模制层32的材料相同或不同。在一些实施例中，电子装置10进一步包括在电子组件12与RDL 14之间的接触垫36和导体38，并且RDL 14和电子组件12通过接触垫36和导体38电连接到彼此。在一些实施例中，导体38包括传导凸点，例如，焊接凸点、焊料球、焊料膏或类似物。在一些实施例中，电子装置10进一步包括第二电子组件39，所述第二电子组件39电连接到RDL 14并且通过第二模制层34囊封。在一些实施例中，第二电子组件39包括(但不限于)有源组件(例如，存储器组件)或无源组件(例如，电容器、电感器、电阻器或类似物)。在一些实施例中，电触点18安置在RDL14上并且电连接到RDL 14。
在一些实施例中，在具有第二模制层34的RDL 14上封装电子组件12以形成电子装置10，并且囊封电子组件12的第二模制层34随后通过粘合层11附接到传导框20的第一部分24。随后，形成接合导线19以电连接传导框20与接地组件16。随后，形成第一模制层32以囊封第二模制层34、RDL 14、接合导线19和电触点18的一部分。
本发明的各种实施例的半导体装置封装与WLCSP兼容。围绕电子装置的横向侧面的传导框能够为半导体装置封装提供侧壁保护。包围电子装置的横向侧面和后表面的传导框可以被配置为保形屏蔽件以减少EMI。半导体装置封装可以通过电触点电连接到另一电子装置或半导体装置封装以形成SIP或堆叠封装。由金属、金属合金或具有足够的热导率的其它传导材料形成的传导框也可以被配置为散热片以提供用于电子装置的散热路径。电子装置可为半导体裸片或预封装结构。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可以包括复数指示物。
如本文所使用，术语“传导”和“导电性”和“导电率”指传输电流的能力。导电材料通常指示呈现对电流流动极少对抗或无对抗的那些材料。导电率的一个量度是西门子/米(S/m)。通常，导电材料为具有大于约104S/m(例如，至少105S/m或至少106S/m)的导电率的一种材料。材料的导电率有时可随温度而变化。除非另外规定，否则在室温下测量材料的导电率。
如本文中所使用，术语“大致”、“基本上”、“实质”和“约”用于描述和解释小的变化。当与事件或情形结合使用时，所述术语可指事件或情形明确发生的例子以及事件或情形极近似地发生的例子。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“基本上”相同或相等。举例来说，“基本上”平行可指相对于0°的小于或等于±10°的角变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可指相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。
如果两个表面之间的位移不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为这两个表面是共面的或大体上是共面的。
另外，有时在本文中按范围格式呈现量、比率以及其它数值。应理解，此类范围格式是用于便利和简洁起见，且应灵活地理解，不仅包括明确地指定为范围限制的数值，且还包括涵盖于所述范围内的所有个体数值或子范围，如同明确地指定每一数值和子范围一般。
尽管已参考本发明的特定实施例描述并说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应理解，在不脱离如由所附权利要求书界定的本发明的真实精神及范围的情况下，可作出各种改变且可取代等效物。所述图式可能未必按比例绘制。归因于制造过程及容差，本发明中的艺术再现与实际设备之间可能存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可作出修改，以使特定情况、材料、物质组成、方法或过程适应于本发明的目标、精神以及范围。所有此类修改都意图在所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组不是对本发明的限制。

Claims (20)

1.一种半导体装置封装，其包括：
电子装置；
传导框，其安置在电子装置上并且电连接到所述电子装置，所述传导框包括多个引线；以及
第一模制层，其覆盖所述电子装置和所述传导帧的一部分，并且安置在所述引线中的至少邻近的两者之间。
2.根据权利要求1所述的半导体装置封装，其中所述传导框包括第一部分和第二部分，所述第一部分面向所述电子装置的第一表面，所述第二部分面向所述电子装置的横向侧面，所述第二部分的一端连接到所述第一部分并且所述第二部分的另一端连接到所述引线，所述第一模制层囊封所述第二部分、所述电子装置的所述横向侧面以及与所述电子装置的所述第一表面相对的所述电子装置的第二表面的一部分。
3.根据权利要求1所述的半导体装置封装，其中所述电子装置包括接地组件和接合导线，所述接合导线将所述传导框电连接到所述接地组件。
4.根据权利要求3所述的半导体装置封装，其中所述第一模制层囊封所述接合导线。
5.根据权利要求3所述的半导体装置封装，其中所述电子装置进一步包括电子组件和再分布层，所述再分布层安置在所述电子组件上并且电连接到所述电子组件。
6.根据权利要求5所述的半导体装置封装，其进一步包括多个电触点和所述第一模制层，所述多个电触点安置在所述再分布层上并且电连接到所述再分布层，所述第一模制层囊封所述电触点中的每一个的一部分。
7.根据权利要求5所述的半导体装置封装，其中所述电子组件附接到所述传导框。
8.根据权利要求5所述的半导体装置封装，其中所述电子装置进一步包括囊封所述电子组件的第二模制层，所述第二模制层的一部分通过所述第一模制层囊封，并且所述第二模制层附接到所述传导框。
9.一种半导体装置封装，其包括：
电子装置，其具有第一表面、与所述第一表面相对的第二表面，以及多个横向侧面；
传导框，其包括面向所述电子装置的所述第一表面的顶盖部分和围绕所述电子装置的所述横向侧面的横向部分，所述横向部分限定至少一个凹口以及电连接到所述电子装置的所述传导框；以及
第一模制层，其囊封所述电子装置的所述横向侧面和所述第二表面的一部分、所述传导框的所述横向部分以及所述顶盖部分的一部分，并且填充到所述至少一个凹口中。
10.根据权利要求9所述的半导体装置封装，其中所述横向部分的一端连接到所述顶盖部分，并且所述至少一个凹口安置在所述横向部分的另一端处。
11.根据权利要求9所述的半导体装置封装，其中所述电子装置包括接地组件和接合导线，所述接合导线将所述传导框电连接到所述接地组件。
12.根据权利要求11所述的半导体装置封装，其中所述第一模制层囊封所述接合导线。
13.根据权利要求11所述的半导体装置封装，其中所述电子装置进一步包括电子组件和安置在所述电子组件上的再分布层。
14.根据权利要求13所述的半导体装置封装，其进一步包括多个电触点，所述多个电触点安置在所述再分布层上，并且所述第一模制层囊封所述电触点中的每一个的一部分。
15.根据权利要求13所述的半导体装置封装，其中所述电子组件附接到所述传导框。
16.根据权利要求13所述的半导体装置封装，其中所述电子装置进一步包括囊封所述电子组件的第二模制层，所述第二模制层的一部分通过所述第一模制层囊封，并且所述第二模制层附接到所述传导框。
17.一种制造半导体装置封装的方法，其包括：
提供包括多个引线的传导框；
将电子装置安置在传导框上，所述传导框覆盖所述电子装置的第一表面并且围绕所述电子装置的横向侧面，所述传导框电连接到所述电子装置；以及
在所述电子装置和所述传导框上形成模制层，并且所述模制层形成于所述引线中的至少邻近的两者之间。
18.根据权利要求17所述的方法，其进一步包括在形成所述模制层之前形成接合导线，所述接合导线将所述电子装置的接地组件电连接到所述传导框。
19.根据权利要求18所述的方法，其中所述模制层囊封所述接合导线。
20.根据权利要求17所述的方法，其进一步包括在所述电子装置上形成多个电触点，其中所述模制层暴露所述电触点中的每一个的一部分。
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