CN108735717A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN108735717A
CN108735717A CN201710455400.5A CN201710455400A CN108735717A CN 108735717 A CN108735717 A CN 108735717A CN 201710455400 A CN201710455400 A CN 201710455400A CN 108735717 A CN108735717 A CN 108735717A
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CN
China
Prior art keywords
semiconductor
emi
shielded layers
emi shielded
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710455400.5A
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English (en)
Inventor
金舒永
娜捷明
金德宫
黄泰坤
林广莫里斯
朴孙杉
金凯领
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Anrely Technology Singapore Holdings Pte Ltd
Original Assignee
Imark Technology Co
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Application filed by Imark Technology Co filed Critical Imark Technology Co
Publication of CN108735717A publication Critical patent/CN108735717A/zh
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Abstract

本发明提供一种半导体装置，其包括：半导体晶粒，包括第一表面、与所述第一表面相对的第二表面、形成在所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；EMI屏蔽层，其包括屏蔽所述半导体晶粒的所述第一表面的第一导电层和屏蔽所述半导体晶粒的所述第三表面的第二导电层；基板，其电连接到所述半导体晶粒的所述多个互连结构；以及囊封部分，其囊封所述EMI屏蔽层和所述基板。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。本发明公开的实施例提供一种半导体装置。
背景技术
近年来的电子装置，例如智能型手机、膝上型计算机和平板计算机，包括配备有无线通信功能的多个无线半导体装置。无线半导体装置由于内建集成电路的时序频率和高数据传输速度而产生电磁噪声。为了抑制电磁噪声，通常使用基板级“金属屏蔽”方法。然而，基板级“金属屏蔽”方法涉及可能导致低生产率和不良合格率的复杂的制造过程。此外，复杂的制造过程可能阻碍利用该制造过程的电子装置的小型化和薄化。
发明内容
包括半导体晶粒及/或用EMI屏蔽处理的囊封部分的半导体装置基本上与附图中的至少一个一起显示及/或描述，并且在权利要求书中更全面地阐述。
根据本发明的一态样为一种半导体装置，所述半导体装置包括：半导体晶粒，包括第一表面、与所述第一表面相对的第二表面、形成在所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；EMI屏蔽层，其包括屏蔽所述半导体晶粒的所述第一表面的第一导电层和屏蔽所述半导体晶粒的所述第三表面的第二导电层；基板，其电连接到所述半导体晶粒的所述多个互连结构；以及囊封部分，其囊封所述EMI屏蔽层和所述基板。
所述态样的半导体装置进一步包括：另一半导体晶粒，其与所述半导体晶粒水平地间隔开；其中所述EMI屏蔽层的所述第二导电层介于所述半导体晶粒和所述另一半导体晶粒之间。
在所述态样的半导体装置中，所述半导体晶粒包括：接触垫，其电连接到所述多个互连结构中的互连结构；以及接地电路图案，其电连接所述接触垫和所述EMI屏蔽层。
在所述态样的半导体装置中，所述EMI屏蔽层包括选自导电聚合物、导电油墨、导电膏和导电箔的材料。
所述态样的半导体装置进一步包括填充所述半导体晶粒和所述基板之间的间隙的底部填充物。
在所述态样的半导体装置中，所述EMI屏蔽层包括非溅射的EMI屏蔽层。
在所述态样的半导体装置中，所述EMI屏蔽层包括铜箔。
在所述态样的半导体装置中，所述EMI屏蔽层包括旋涂的EMI屏蔽层。
在所述态样的半导体装置中，所述EMI屏蔽层包括喷射印刷的EMI屏蔽层。
根据本发明的另一态样为一种半导体装置，所述半导体装置包括：半导体晶粒，其包括第一表面、与所述第一表面相对的第二表面、形成在所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；非溅射的EMI屏蔽层，其屏蔽所述半导体晶粒的所述第一表面；多个EMI屏蔽线，其围绕所述半导体晶粒的所述第三表面定位且电连接到所述非溅射的EMI屏蔽层；基板，其电连接到所述半导体晶粒的所述多个互连结构；以及囊封部分，其囊封所述非溅射的EMI屏蔽层、所述EMI屏蔽线和所述基板。
在所述态样的半导体装置中，所述非溅射的EMI屏蔽层包括选自导电聚合物、导电油墨、导电膏和导电箔的材料。
在所述态样的半导体装置中，所述多个EMI屏蔽线围绕且感应地屏蔽所述半导体晶粒的所述第三表面。
在所述态样的半导体装置中，所述多个EMI屏蔽线与所述半导体晶粒的所述第三表面间隔开。
在所述态样的半导体装置中，所述非溅射的EMI屏蔽层具有带有四边的矩形；以及所述多个EMI屏蔽线沿着所述四边配置。
根据本发明的又一态样为一种半导体装置，所述半导体装置包括：半导体晶粒，其包括第一表面、与所述第一表面相对的第二表面、形成在所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；基板，其电连接到所述半导体晶粒的所述多个互连结构；第一囊封部分，其包括围绕所述半导体晶粒的所述第一表面的第一区域和围绕所述半导体晶粒的所述第三表面的第二区域；以及EMI屏蔽层，其屏蔽所述第一囊封部分的所述第一区域和所述第二区域中的至少一个。
在所述态样的半导体装置中，所述EMI屏蔽层屏蔽所述第一囊封部分的所述第二区域；以及所述基板进一步包括通过所述第二区域暴露的天线图案。
所述态样的半导体装置进一步包括囊封所述第一囊封部分、所述EMI屏蔽层和所述基板的第二囊封部分。
在所述态样的半导体装置中，所述EMI屏蔽层屏蔽所述第一囊封部分的所述第一区域。
所述态样的半导体装置进一步包括围绕所述半导体晶粒的所述第三表面定位且电连接到所述EMI屏蔽层的多个EMI屏蔽线。
在所述态样的半导体装置中，所述EMI屏蔽层包括非溅射的EMI屏蔽层。
附图说明
在整个附图和详细描述中使用通用附图标记来表示相同或相似的组件。
图1A和1B为根据本发明的各种示例性实施例的半导体装置和各自具有EMI屏蔽层的半导体晶粒的横截面图。
图2A和2B为根据本发明的各种示例性实施例的半导体装置和各自具有EMI屏蔽层的半导体晶粒的横截面图。
图3A和3B为根据本发明的各种示例性实施例的半导体装置和具有EMI屏蔽层的半导体晶粒的横截面图，以及图3C是EMI屏蔽层和EMI屏蔽线的平面图。
图4A和4B为根据本发明的各种示例性实施例的半导体装置的横截面图和侧视图。
图5为根据本发明的各种示例性实施例的半导体装置的横截面图。
图6为根据本发明的各种示例性实施例的半导体装置的制造方法的流程图。
图7A-7M为依序地说明根据本发明的各种示例性实施例的半导体装置的制造方法的制程步骤的横截面图。
图8A-8J为依序地说明根据本发明的各种示例性实施例的半导体装置的制造方法的处理步骤的横截面图。
图9A-9C为依序地说明根据本发明的各种示例性实施例的半导体装置的制造方法的处理步骤的横截面图。
图10A-10D为依序地说明根据本发明的各种示例性实施例的半导体装置的制造方法的处理步骤的横截面图。
图11说明了可以替代图8C的旋涂制程步骤的用于本发明的各种示例实施例之铜箔层压处理步骤。
具体实施方式
以下配合图式及本发明的较佳实施例，进一步阐述本发明为达成预定发明目的所采取的技术手段。
如本文所使用的，“及/或”是指藉由“及/或”连接的列表中的任何一个或多个项目。作为范例，“x及/或y”表示三元素集合{(x)，(y)，(x，y)}中的任何元素。也就是说，“x及/或y”表示“x和y中的一个或两个”。作为另一范例，“x、y及/或z”表示七元素集合{(x)，(y)，(z)，(x，y)，(x，z)，(y，z)，(x，y，z)}。也就是说，“x、y及/或z”表示“x、y和z中的一个或多个”。如本文中所使用的用语“例如”和“举如”表示非限制性范例、实例或图标。
本文使用的术语仅用于描述具体实施例的目的，并不意图限制本发明。如本文中所使用的单数形式也意图包括复数形式，除非上下文另有明确指出。进一步理解成，在本说明书中使用的用语“包括”、“包含”、“包括有”、“包含有”、“具有”、“含有”、“有”及相似用词指定了所描述的特征、整数、步骤、操作、组件及/或组件的存在，但不排除存在或添加一个或多个其他特征、整数、步骤、操作、组件、组件及/或其群组的存在。
应当理解的是，尽管用语第一、第二等可以在本文中用于描述各种组件，但是这些组件不应受这些用语的限制。这些用语仅用于区分一个组件和另一个组件。因此，例如，在不脱离本发明的教导的情况下，可以将下面讨论的第一组件、第一组件或第一部分称为第二组件、第二组件或第二部分。类似地，可以使用诸如“上”、“下”、“侧”、“顶”、“底”以及类似用词的各种空间用语而以相对方式区分一个组件与另一组件。然而，应当理解的是，组件可以以不同的方式定向，例如，半导体装置可以侧向转动，使得其“顶”表面为水平面向并且其“侧”表面为垂直面向，而不脱离本发明的教导。
参见图参考图1A和1B，根据本发明的各种示例性实施例提供半导体装置100的横截面图。如图所示，半导体装置100可以包括半导体晶粒110A和110B、EMI屏蔽层120、基板130和囊封部分150。另外，半导体装置100还可以包括外部互连结构160。
半导体晶粒110A和110B中的每一个可以具有基本上平坦的第一表面111、与第一表面111相对的基本上平坦的第二表面112和形成在第一表面111和第二表面112之间的第三表面113。另外，每个半导体晶粒110A和110B可以包括形成在第二表面112上的至少一个或多个接触垫114(例如，接合垫或再分布垫)，以及连接到内部接触垫的至少一个或多个内部互连结构115。基本上，第一表面111可以包括每个半导体晶粒110A和110B的顶表面，第二表面112可以包括每个半导体晶粒110A和110B的底表面，并且第三表面可以包括每个半导体晶粒110A和110B的四个侧面中的一个以上侧面。
在图1A和图1B中显出了半导体装置100具有两个半导体晶粒110A和110B。然而，在一些实施例中，半导体装置100可以包括单个半导体晶粒或比两个还多的半导体晶粒。
内部互连结构115的范例可以包括但不限于例如微型凸块、金属柱、焊料凸块或焊球的各种类型的结构，其将半导体晶粒110A和110B电接合到基板130。在一个范例中，内部互连结构115可以包括具有焊料凸块或焊料帽115a的铜柱，其藉由回焊或热压缩而接合到基板130。内部互连结构115可以具有但不限于约20-50微米(μm)的间距及/或大约90-100μm的间距。
同时，半导体晶粒110A和110B可以包括与半导体晶圆分离的集成电路晶粒，并且其范例可以包括但不限于电路，诸如数字信号处理器(digital signal processor，DSP)、微处理器、网络处理器、电源管理处理器、音频处理器、RF电路、无线基频系统单芯片(system-on-chip，SoC)处理器、传感器和特定应用集成电路(application specificintegrated circuit，ASIC)。
EMI屏蔽层120可以包括屏蔽半导体晶粒110A和110B的第一表面111的基本上平坦的第一导电层121和屏蔽半导体晶粒110A和110B的第三表面113的基本上平坦的第二导电层122。以这种方式，第一导电层121和第二导电层122可以提供具有屏蔽半导体晶粒110A和110B的顶表面和四个侧面的帽形状的EMI屏蔽层120。此外，当半导体装置100包括与第二半导体晶粒110B水平间隔开的第一半导体晶粒110A时，EMI屏蔽层120可以填充第一和第二半导体晶粒110A和110B之间的间隙。特别地，EMI屏蔽层120的第二导电层122可以被配置为使得第二导电层122被插入到第一和第二半导体晶粒110A和110B的第三表面113之间的区域中。
EMI屏蔽层120可以防止由半导体晶粒110A和110B产生的电磁波辐射到外部。此外，EMI屏蔽层120可以防止外部施加的电磁波进入半导体晶粒110A和110B。在整个详细描述中，EMI屏蔽层120的这种功能可以被称为EMI屏蔽。
为了能够屏蔽电磁波，EMI屏蔽层120可以使用各种导电材料形成。用于EMI屏蔽层120的合适导电材料的实例可包括但不限于铜(Cu)、镍(Ni)、金(Au)、银(Ag)、铂(Pt)、钴(Co)、钛(Ti)、铬(Cr)、锆(Zr)、钼(Mo)、钌(Ru)、铪(Hf)、钨(W)、铼(Re)、石墨或碳黑。在一些实施例中，EMI屏蔽层120还可以包括金属颗粒和用于结合EMI屏蔽层内部的金属颗粒的结合剂。在其它实施例中，EMI屏蔽层120还可以包括金属颗粒和用于将金属颗粒附着到半导体晶粒110A和110B的表面的结合剂。
此外，EMI屏蔽层120可以包括掺杂有金属或金属氧化物的导电聚合物，例如聚乙炔、聚苯胺、聚吡咯、聚噻吩或聚硫氮化物。此外，EMI屏蔽层120可以包括具有诸如碳黑、石墨和银的导电材料的导电油墨。
EMI屏蔽层120的厚度可以在例如约0.1μm至约1000μm的范围内，优选为1μm至100μm的范围内，更优选为3μm至30μm的范围内，但是本发明的态样不限于此。当EMI屏蔽层120的厚度小于0.1μm时，EMI屏蔽层120的EMI屏蔽效率可能小于期望的阈值，并且当EMI屏蔽层120的厚度大于1000μm时，形成EMI屏蔽层120所需的时间可能延长到经济上可行的时段之外。
此外，EMI屏蔽层120可以例如藉由诸如旋涂、喷涂、印刷、层压及/或其组合的各种非溅射工艺来形成，但不限于此。如本文中所用的术语“非溅射”和相关词和词组是用于区分已经通过溅射制程形成的层与已经由诸如旋涂、喷涂、印刷、层压及/或这些工艺的组合形成的EMI屏蔽层120的层。这种非溅射层可以具有优于溅射层的各种优点。例如，与溅射层相比，非溅射层可以每单位小时(unit per hour，UPH)更高的产量、降低操作成本、降低工具成本以及更好地控制成形层的厚度，特别是沿着侧壁。
如上所述，EMI屏蔽层120不形成于囊封部分150的表面上，而是直接形成于半导体晶粒110A和110B(例如，硅晶粒)的表面上。因此，根据本发明的各种实施例的半导体装置100可以表现出改善的EMI屏蔽效率。特别地，如果在囊封部分150的外表面上形成EMI屏蔽层120，则EMI屏蔽层120将与半导体晶粒110A和110B隔开预定间隙。这种间隔可以允许电磁波从半导体晶粒110A、110B辐射到外部，或者通过所述间隙进入到半导体晶粒110A、110B的内部。然而，通过直接形成于半导体晶粒110A和110B的表面上的EMI屏蔽层120，在EMI屏蔽层120和半导体晶粒110A和110B中的每一个之间没有间隙。因此，EMI屏蔽层120可以显著地抑制电磁波从半导体晶粒110A、110B向外部辐射，或者显著抑制电磁波从外部进入半导体晶粒110A、110B。
此外，半导体晶粒110A和110B中的每一个还可以包括连接到接触垫114的接地电路图案116。接地电路图案116可以直接电连接到EMI屏蔽层120(参见图1B)。接触垫114可以电连接到内部互连结构115。另外，内部互连结构115可以电连接到基板130的上部电路图案132。接触垫114、内部互连结构115和基板130的上部电路图案132可以电连接到接地电路图案116，并且可以提供用于接地的结构。因此，EMI屏蔽层120可以接地，并且更有效地防止电磁波辐射或感应。在一些实施例中，一些内部互连结构115可以用作接地凸块，一些内部互连结构115可以用作信号凸块，并且一些内部互连结构115可以用作功率凸块。在这样的实施例中，接地电路图案116可以电连接到用作接地凸块的内部互连结构115。
基板130可以包括用于半导体晶粒110A和110B的机械支撑结构及/或被动装置。为此，基板130可以包括介电层131和形成于介电层131的顶表面上的上部电路图案(例如，导电迹线)132。上部电路图案132可以电连接到每个半导体晶粒110A和110B的内部互连结构115。基板130还可以包括电连接到形成于介电层131的底表面上的外部电路板的下部电路图案133。特别地，基板130还可以包括在上部电路图案132和下部电路图案133之间的多个电路图案134和通孔135。进一步，多个电路图案134和通孔135可以电连接到上部电路图案132及/或下部电路图案133。基板130的范例可以包括但不限于刚性印刷电路板、挠性印刷电路板、有芯电路板、无芯电路板和积层电路板。
进一步，底部填充物140还可以填充每个半导体晶粒110A和110B与基板130之间的区域。底部填充物140可以保护内部互连结构115并且可以将半导体晶粒110A和110B机械地连接到基板130。在将半导体晶粒110A和110B与基板130电连接之前，可以将底部填充物140施加到半导体晶粒110A和110B及/或基板130。在一些实施例中，在半导体晶粒110A和110B与基板130电连接之后，底部填充物140可通过毛细作用填充每个半导体晶粒110A和110B与基板130之间的间隙。此外，底部填充物140可以包括具有或不具有有机或无机填料的非导电膏。
底部填充物140被配置为使得底部填充物140基本上黏着到EMI屏蔽层120。特别地，底部填充物140可以黏着到形成于半导体晶粒110A和110B的第三表面上的第二导电层122的底表面和侧表面。对于通过旋涂、喷涂及/或印刷形成EMI屏蔽层120的实施例，与半导体晶粒110A和110B的表面相比，EMI屏蔽层120可具有非常粗糙的多孔表面。具体地，EMI屏蔽层120可以表现出比半导体晶粒110A和110B高得多的粗糙度。因此，由于具有相对高粗糙度的底部填充物140直接黏着到EMI屏蔽层120，所以底部填充物140和EMI屏蔽层120之间的黏着力得到改善。此外，可以通过底部填充物140改善EMI屏蔽层120/半导体晶粒110A和110B与基板130之间的机械黏着力。
在一些实施例中，可以不提供底部填充物140。如果囊封部分150(下面更详细地描述)的填料尺寸小于半导体晶粒110A、110B和基板130之间的间隙的尺寸，则囊封材料可以充分地注入且填充间隙。在这样的实施例中，可以不提供底部填充物140。
囊封部分150(例如，囊封构件或囊封剂)可以囊封EMI屏蔽层120、底部填充物140和基板130。囊封部分150可以保护EMI屏蔽层120、底部填充物140和基板130免受外来环境影响。囊封部分150以及本文所述的其它囊封部分的范例可包括但不限于环氧树脂模塑化合物、环氧模塑树脂等。囊封部分150可以将在基板130上的EMI屏蔽层120完全囊封。在一些实施例中，囊封部分150可以暴露EMI屏蔽层120的一部分。例如，囊封部分150可以不形成于EMI屏蔽层120的第一导电层121上。这样，EMI屏蔽层120的第一导电层121可以直接暴露于外部。更具体地，EMI屏蔽层120的第一导电层121的顶表面可以与囊封部分150的顶表面共平面。在这样的实施例中，半导体晶粒110A和110B可以具有更高的热辐射性能。
如果囊封部分150完全囊封EMI屏蔽层120，则可能导致囊封部分150和EMI屏蔽层120之间的高黏着力。因此，可以消除囊封部分150和EMI屏蔽层120之间的界面分层。特别地，由于EMI屏蔽层120的粗糙度高，如上所述，囊封部分150和EMI屏蔽层120之间所表现的黏着力进一步增加。此外，如果囊封部分150完全囊封EMI屏蔽层120，囊封部分150可以保护EMI屏蔽层120免受外部物理和化学冲击。
外部互连结构160的范例可以包括但不限于金属柱、焊料凸块、焊球、凸块或连接盘(land)。外部互连结构160可以包括具有大约100-200μm的尺寸的凸块或具有大约20-100μm的尺寸的凸块/柱。当在外部互连结构160中使用焊料凸块时，外部互连结构160可以包括一种或多种焊料金属，所述焊料金属在比其它金属低的温度下熔化且可以在熔化和冷却工序期间在外部互连结构160和外部电路板或另一装置之间提供物理和电接合。外部互连结构160的范例可以包括但不限于球栅数组(BGA)及/或平面栅格数组(LGA)。虽然说明了在外部互连结构160中使用的焊球，但是外部互连结构160可以包括各种类型的结构。
如上所述，根据本发明的各种实施例，EMI屏蔽层120直接形成于半导体晶粒110A和110B的第一表面111(例如，顶表面)及/或第三表面113(例如，侧表面)。EMI屏蔽层120的这种形成可以提高EMI屏蔽层120的生产率和合格率，并且可以提供具有改善的EMI屏蔽效率的半导体装置100。此外，由于EMI屏蔽层120嵌入到囊封部分150中，所以可以安全地保护半导体装置100免受外部环境的影响。此外，EMI屏蔽层120的这种形成可以有助于半导体装置100的小型化和薄化。
参见图2A和2B，说明了根据本发明的各种示例性实施例的半导体装置200的横截面图。如图所示，半导体装置200可以与半导体装置100类似的方式形成。然而，半导体装置200可以包括内部互连结构215，其包括将半导体晶粒110A和110B连接到基板130的导电球。在比较后，图1A和1B所示的半导体装置100的内部互连结构115包括具有焊料的导电柱(例如，铜柱)。
内部互连结构215(诸如焊球)可以藉由质量回焊将半导体晶粒110A和110B电连接到基板130，这可以改善半导体装置200的生产率。此外，互连结构215(诸如焊球)可以比其它内部互连结构(诸如导电柱)更简化的方式形成。因此，互连结构215可以比互连结构115低的成本形成，从而与半导体装置100相比降低了半导体装置200的制造成本。
图3A和3B图示了根据本发明的各种示例性实施例的半导体装置300和具有EMI屏蔽层320的半导体晶粒110的横截面图。图3C提供EMI屏蔽层320和EMI屏蔽线370的平面图。
如图3A-3C所示，根据本发明的各种示例性实施例的半导体装置300可以包括半导体晶粒110、仅在半导体晶粒110的第一表面111(例如，顶表面)上形成的EMI屏蔽层320以及将EMI屏蔽层320电连接到基板130的多个EMI屏蔽线370。特别地，EMI屏蔽层320可以仅形成于半导体晶粒110的第一表面111上，但不能形成于半导体晶粒的第三表面113上。因此，囊封部分150可以直接黏着到形成于半导体晶粒110的第一表面111上的EMI屏蔽层320和黏着到半导体晶粒110的第三表面113。
此外，EMI屏蔽线370可以将EMI屏蔽层320电连接到基板130的接地电路图案332。特别地，EMI屏蔽线370可以与半导体晶粒110的第三表面113基本上平行。为此，EMI屏蔽线370的第一端可以球接合(或缝合)到EMI屏蔽层320，并且EMI屏蔽线370的第二端可以缝合(或球接合)到接地电路图案332。
EMI屏蔽层320的平面形状可以是但不限于具有四边的大致矩形形状。基板130的接地电路图案332的平面形状也可以是具有四边的大致矩形形状。EMI屏蔽线370可以沿着EMI屏蔽层320的四边以恒定的间距布置。每个EMI屏蔽线370可将EMI屏蔽层320的一侧电连接到接地电路图案的相应侧332。
EMI屏蔽线370可以与半导体晶粒110的第三表面113隔开预定的距离，并且可以屏蔽半导体晶粒110。EMI屏蔽线370之间的距离或间距可根据要屏蔽的电磁波的波长范围而改变。例如，要屏蔽的电磁波的波长越短，EMI屏蔽线370之间的距离或间距越小。构成EMI屏蔽线370的材料的范例可以包括但不限于各种金属，诸如金(Au)、银(Ag)、铜(Cu)或铝(Al)。
囊封部分150可以囊封且保护半导体晶粒110、EMI屏蔽层320和在基板130上的EMI屏蔽线370免受外部物理和化学环境的影响。反过来，EMI屏蔽层320和EMI屏蔽线370可以感应地屏蔽半导体晶粒110免受电磁波的影响。
如上所述，根据本发明的各种实施例，EMI屏蔽层320和EMI屏蔽线370围绕半导体晶粒110形成法拉第笼。这种法拉第笼可以防止由半导体晶粒110产生的电磁波辐射到外面。此外，法拉第笼可以防止外部电磁波进入和干扰半导体晶粒110。
参考图4A和4B，说明了根据本发明的各种示例性实施例的半导体装置400的横截面图和侧视图。如图4A和4B所示，半导体装置400可以包括半导体晶粒110、基板130、囊封部分450和EMI屏蔽层420。囊封部分450可以包括粗略地囊封半导体晶粒110的第一表面111的第一区域451及粗略地囊封半导体晶粒110的第三表面113的第二区域452。
EMI屏蔽层420可以屏蔽囊封部分450的第一区域451和至少一部分第二区域452。如图所示，EMI屏蔽层420可以屏蔽囊封部分450的第二区域452，但是本发明的态样不限于此。相反地，EMI屏蔽层420可以屏蔽囊封部分450的第一区域451。
基板130还可以包括形成于其顶表面上的天线图案434。如果天线图案434由EMI屏蔽层420囊封，则EMI屏蔽层将防止或基本上减少天线图案434作为天线的功能。因此，如图所示，天线图案434可以从EMI屏蔽层420及/或囊封部分450露出。
为此，EMI屏蔽层420可以形成于例如囊封部分450的第二区域452上，但不形成于例如天线图案434上。绝缘层435可以插入在EMI屏蔽层420和天线图案434之间。或者，EMI屏蔽层420和天线图案434可以彼此隔开预定距离。此外，EMI屏蔽层420可以电连接到形成在基板130上的接地电路图案432。由于EMI屏蔽层420形成于与天线图案434间隔开的区域(例如，囊封部分450的第二区域452)，EMI屏蔽层420可以有效地屏蔽来自半导体晶粒110的电磁波，同时不妨碍形成于基板130上的天线图案434的操作。
参考图5，说明了根据本发明的各种示例性实施例的半导体装置500的横截面图。如图5所示，半导体装置500可以包括半导体晶粒110、基板130、囊封半导体晶粒110的第一囊封部分551、形成在第一囊封部分551上的EMI屏蔽层520、连接EMI屏蔽层520至基板130的EMI屏蔽线570以及囊封第一囊封部分551、EMI屏蔽层520和EMI屏蔽线570的第二囊封部分552。
第一囊封部分551可以囊封半导体晶粒110的第一表面111和第三表面113。第一囊封部分551的第一区域551a可以囊封半导体晶粒110的第一表面111。第一囊封部分551的第二区域551b可以囊封囊封部分551的第三表面113。
EMI屏蔽层520可以形成于第一囊封部分551的第一区域551a上。特别地，EMI屏蔽层520可以形成于第一囊封部分551的对应于半导体晶粒110的第一表面111的第一区域551a上。第一囊封部分551的第一区域551a可以形成为基本上平坦的。EMI屏蔽层520也可以形成为具有基本上平坦的板。
EMI屏蔽线570可以将EMI屏蔽层520电连接到设置于基板130上的接地电路图案332。在一个范例中，EMI屏蔽线570可形成为与第一囊封部分551的第二区域551b基本上平行。另外，EMI屏蔽线570可以与第一囊封部分551的第二区域551b间隔开预定距离。特别地，可以形成EMI屏蔽线570以屏蔽第一囊封部分551(例如，半导体晶粒110的第三表面)。
第二囊封部分552可以囊封第一囊封部分551、EMI屏蔽层520和EMI屏蔽线570。第二囊封部分552的范例可以包括但不限于与第一囊封部分552相同或不同的材料。在一些实施粒中，第二囊封部分552可以具有比第一囊封部分551更小的模数。因此，与第一囊封部分551相比，第二囊封部分552可以有效地吸收或减轻外部冲击。
如上所述，半导体晶粒110被第一囊封部分551囊封。EMI屏蔽层520形成于第一囊封部分551的表面上，从而保护半导体晶粒110免受外部环境的影响。EMI屏蔽层520可以进一步提供带有改善的EMI屏蔽效率的半导体装置500。由于半导体晶粒110被第一囊封部分551和多个EMI屏蔽线570两者囊封，所以半导体装置500具有改善的EMI屏蔽效率。
在一些实施例中，可以省略第二囊封部分552。在这样的实施例中，EMI屏蔽层520和EMI屏蔽线570可以暴露于外部。进一步，未被EMI屏蔽层520覆盖的第一囊封部分551的一部分、未被第一囊封部分552覆盖的基板130的一部分和被动装置可以暴露于外部。然而，EMI屏蔽层520和EMI屏蔽线570仍然在半导体晶粒110周围形成法拉第笼。如上所述，法拉第笼可以防止由半导体晶粒110产生的电磁波辐射到外部，并且可以防止外部电磁波进入和干扰半导体晶粒110。
参照图6，说明了根据本发明的各种示例性实施例的半导体装置的制造方法的流程图。如图所示，制造方法可以包括在晶圆的前侧(例如，半导体晶粒的第二表面)上形成互连结构的晶圆凸块制程步骤(S1)和在晶圆的背侧(例如，第一表面)上层叠晶圆安装带的晶圆安装带层叠步骤(S2)。所述方法还可以包括沿着路线将晶圆分离成各个半导体晶粒的晶圆切割步骤(S3)以及在晶圆的前侧上层叠凸块保护带的凸块保护带层压步骤(S4)。
所述方法还可以包括自晶圆剥离晶圆安装带的晶圆安装带剥离步骤(S5)以及切割凸块保护带的边缘且移除其的边缘切割步骤(S6)。此外，所述方法可以包括在晶圆的背侧上旋涂EMI屏蔽层的EMI屏蔽层旋涂步骤(S7)和固化或烧结涂覆的EMI屏蔽层的固化或烧结步骤(S8)。
所述方法还可以包括在晶圆的背侧上层压经固化或烧结的晶圆安装带的晶圆安装带层压步骤(S9)以及自晶圆的前侧剥离凸块保护带的凸块保护带剥离步骤(S10)。此外，所述方法可以包括将晶圆分离成单个半导体晶粒或多个半导体晶粒的切割步骤(S11)以及使用拾取工具拾取经分离的半导体晶粒的晶粒拾取步骤(S12)。所述方法也可以包括将半导体晶粒附接到基板的晶粒附接步骤(S13)。
参考图7A-7M，其说明了依序地图示根据本发明的各种示例性实施例的半导体装置的制造方法的处理步骤的横截面图。特别地，参照半导体装置100、图1A、1B、6和7A-7M来描述所述制造方法。
如图7A所示，在晶圆凸块制程步骤(S1)中，在晶圆110W的前侧形成有多个内部互连结构115。特别地，多个内部互连结构115可以形成在形成在晶圆110W上的各个半导体晶粒110的前侧(例如，第二表面112)上。各种类型的内部互连结构115的范例可以包括但不限于微凸块、金属柱、焊料凸块、焊球等
如图7B所示，在晶圆安装带层叠步骤(S2)中，晶圆安装带601可以安装于晶圆110W的背侧上。特别地，晶圆安装带601可以安装在形成于晶圆110W上的半导体晶粒110的第一表面111上。尽管未图示，晶圆安装带601可以由大致圆形的安装环支撑。更具体地，晶圆110W的背侧可以临时黏着到由圆形的安装环支撑的晶圆安装带601。
如图7C所示，在晶圆切割步骤(S3)中，各个半导体晶粒110可以使用例如金刚石刀片、金刚石磨轮或雷射束的切割工具602沿着形成于晶圆110W上的路线分离。因此，由于这种晶圆切割，形成在晶圆110W上的各个半导体晶粒110可以彼此隔开预定距离。此外，晶圆切割可以将各个半导体晶粒110保持半导体晶粒110仍然黏着到晶圆安装带601的状态。
如图7D所示，在凸块保护带层压步骤(S4)中，可以在包括彼此间隔开的多个半导体晶粒110的晶圆110W上层叠凸块保护带603。特别地，凸块保护带603可以临时黏着到晶圆110W的前侧。形成在晶圆110W的前侧上的内部互连结构115可以在制造工序期间被凸块保护带603保护。
如图7E所示，在晶圆安装带剥离步骤(S5)中，黏着在晶圆110W背侧的晶圆安装带601可以被剥离。因此，晶圆110W的背侧可以暴露于外部。特别地，晶圆安装剥离步骤可以使分离的多个半导体晶粒110中的每一个的第一表面111和第三表面113暴露于外部。然而，晶圆安装带剥离步骤可以保持半导体晶粒110或晶圆110W的前侧(例如第二表面112)处于半导体晶粒110保持黏着到凸块保护带603的状态。
如图7F所示，在边缘切割步骤(S6)中，边缘切割工具604可以切割对应于晶圆110W的圆周边缘的凸块保护带603的圆周边缘。以这种方式，延伸超过晶圆110W的圆周边缘的多余的凸块保护带603因而藉由边缘切割工具604移除。因此，晶圆110W和凸块保护带603可以在边缘切割步骤(S6)之后具有相同的平面形状。
如图7G所示，在EMI屏蔽层旋涂步骤(S7)中，晶圆110W可以经由凸块保护带603安装于旋涂设备605上。然后可以藉由涂覆工具606将EMI屏蔽层120旋涂于晶圆110W的背侧上。因此，旋涂设备602可以不仅在半导体晶粒110的顶表面(例如，第一表面111)上涂覆EMI屏蔽层120，而且还可以在半导体晶粒110的侧表面(例如，第三表面113)上涂覆EMI屏蔽层120。为此，旋涂设备605可以使用包括金属颗粒、用于结合金属颗粒的结合剂和溶剂的高黏性涂覆溶液或浆料。在用于EMI屏蔽层120的高黏性浆料涂覆在晶圆110W的背侧上之后，旋涂设备605可以高速旋转晶圆110W，使得EMI屏蔽层120均匀地分布在半导体晶粒110的第一及第三表面111和113上。在一些实施例中，EMI屏蔽层120可以由例如导电聚合物、导电油墨或导电膏形成。
如图7H所示，在固化或烧结步骤(S8)中，形成在晶圆110W的背侧上的EMI屏蔽层120可以通过热及/或光来固化及/或烧结。例如，当EMI屏蔽层120是由可热固化材料制成时，可以向EMI屏蔽层120施加热，及/或当EMI屏蔽层120是由可光固化材料制成时，可以向EMI屏蔽层120施加光。包含在浆料中的溶液可以通过固化及/或烧结工序而被完全挥发除去。结果，只有导电金属或导电聚合物和结合剂可能残留在EMI屏蔽层120中。
如图7I所示，在晶圆安装带层压步骤(S9)中，晶圆安装带607可以再次层压在经固化及/或烧结的EMI屏蔽层120的表面上。
如图7J所示，在凸块保护带剥离步骤(S10)中，可剥离黏着到晶圆110W的前侧(例如，第二表面112)的凸块保护带603。因此，晶圆110W的前侧和内部互连结构115可以暴露于外部。
如图7K所示，在切割步骤(S11)中，各个半导体晶粒110或多个半导体晶粒110通过诸如金刚石磨轮或雷射束的切割工具608自晶圆110W分离。切割工具608可以切锯在每个半导体晶粒110和其相邻的半导体晶粒110之间形成的EMI屏蔽层120。因此，单个半导体晶粒110可以被分离，或者一群半导体晶粒可以自晶圆110W分离。切割工具608的宽度可以小于形成在每个半导体晶粒110及其相邻半导体晶粒110之间的间隙中的EMI屏蔽层120的厚度或宽度。因此，即使在切割之后，EMI屏蔽层120可以保持在半导体晶粒110的侧表面(例如，第三表面113)上。残留在半导体晶粒110的第三表面113上的EMI屏蔽层120的厚度可以在例如约0.1μm至约1000μm的范围内，或者在1μm至100μm的较窄范围内，或者在10μm至30μm的更窄范围内，但本发明的态样不限于此。
如图7L所示，在晶粒拾取步骤(S12)中，弹出销610可以向上推动相关的半导体晶粒110。拾取工具609可以从晶圆安装带607拾取且移除相关的半导体晶粒110。拾取工具609可以进一步将相关的半导体晶粒110移动到预定位置。
如图7M所示，在晶粒附接步骤(S13)中，拾取工具609可以将具有EMI屏蔽层120的优质半导体晶粒110转移到矩形基板130或单独的晶圆托盘。放置在基板130上的半导体晶粒110可以通过质量回焊或热压缩而与基板130电连接。此后，依次进行底部填充步骤、囊封步骤和外部互连结构形成步骤。
如上所述，根据本发明的示例性实施例的半导体装置100的制造方法允许具有EMI屏蔽层120的半导体晶粒110以大规模低成本快速大量生产。因此，根据本发明的实施例，具有EMI屏蔽层120的半导体晶粒110可以高合格率/高生产率且以低成本生产。此外，由于EMI屏蔽层120直接形成于半导体晶粒110的表面上，所以带有改良的小型化和薄化的半导体装置100可以具有高的EMI屏蔽效率。此外，由于EMI屏蔽层120嵌入到囊封部分150中，所以可以保护半导体装置100免受外部环境的影响。
参照图8A-8J，其说明了依序地图示根据本发明的各种示例性实施例的半导体装置的制造方法的处理步骤的横截面图。特别是，参照半导体装置300、图3A-3C和图8A-8J来描述所述制造方法。
如图8A所示，凸块保护带603可以层叠在经凸块制程的晶圆110W的前侧(例如，第二表面112)上。晶圆110W的背侧(例如，第一表面111)可以保持暴露于外部。
如图8B所示，边缘切割工具604可以切割对应于晶圆110W的周边边缘的凸块保护带603的区域。因此，可以藉由边缘切割工具604来移除延伸超过晶圆110W的圆周边缘的凸块保护带603。在这种切割和移除之后，晶圆110W和凸块保护带603可以具有基本上相同的平面形状。
如图8C所示，晶圆110W可以安装于旋涂设备605上。特别地，晶圆110W可以经由凸块保护带603黏着到旋涂设备605。用于形成EMI屏蔽层320的浆料然后可以旋涂于晶圆110W的背侧上。除了旋涂之外，EMI屏蔽层320也可以通过喷涂、印刷及/或层压形成。
在其它实施例中，EMI屏蔽层320可以使用诸如铜箔的导电箔321形成。特别地，在这样的实施例中，如图11所示，具有铜层322和黏着层323的导电箔321可以在晶圆110W的背侧上被滚压或真空层叠。在一些实施例中，铜层322可以具有至少12μm的厚度，并且黏着层323可以具有至少10μm的厚度，从而导致铜箔321具有至少22μm的厚度。
由于晶圆110W在旋涂或层压EMI屏蔽层320之前没有被切割，所以不用如图7A-7M所示的方法在每个半导体晶粒110及其相邻的半导体晶粒110之间产生间隙。因此，图8A-8J的方法中的旋涂设备605不在相邻的半导体晶粒110之间形成EMI屏蔽层320，而仅在晶圆110W的背面上形成。
如图8D所示，经旋涂的EMI屏蔽层320可以通过热及/或光来固化及/或烧结。然后可以将晶圆安装带607层压在经固化及/或烧结的EMI屏蔽层320的表面上，如图8E所示。如图8F所示，可以剥离和去除凸块保护带603。因此，晶圆110W的前侧可以暴露于外部。
如图8G所示，可以通过诸如金刚石磨轮或雷射束的切割工具608沿着设置在晶圆110W上的路线进行切割。形成于晶圆110W上的多个半导体晶粒110可以透过执行个别地切割或群组地切割来分离。结果，多个半导体晶粒110的第三表面113可以直接暴露于外部。特别地，多个半导体晶粒110的第三表面113可以直接暴露于外部，而EMI屏蔽层320屏蔽多个半导体晶粒110的第一表面111。
如图8H所示，通过拾取工具609和弹出销610的操作，从晶圆110W拾取分离的单个或一群半导体晶粒110。如图8I所示，半导体晶粒110可以被放置在基板130上。以这种方式，EMI屏蔽层320可以仅形成于半导体晶粒110的顶表面(例如，第一表面111)上。在半导体晶粒110被拾取并且放置于基板130上之后，半导体晶粒110的内部互连结构115可以通过质量回焊或热压缩而电连接到基板130。
如图8J所示，线接合器611可以经由EMI屏蔽线370而将形成在半导体晶粒110上的EMI屏蔽层320电连接到基板130的接地电路图案。特别地，线接合器611可以多个EMI屏蔽线370围绕半导体晶粒110。因此，半导体晶粒110的顶表面(例如，第一表面111)可以通过EMI屏蔽层320屏蔽电磁波。半导体晶粒110的侧表面(例如，第三表面113)可以通过EMI屏蔽线370屏蔽电磁波。
图9A-9C说明了依序图示根据本发明的各种示例性实施例的半导体装置的制造方法的处理步骤的横截面图。特别地，参照半导体装置400、图4A-4B和图9A-9C来描述所述制造方法。
如图9A所示，放置于基板130上的半导体晶粒110可以由半导体装置400的囊封部分450囊封。此外，基板130的天线图案434可能暴露于外部。囊封部分450可以被分成囊封半导体晶粒110的第一表面111的第一区域451和囊封半导体晶粒110的第三表面113的第二区域452。天线图案434可以被暴露并且可以经由囊封部分450的第二区域452突出到达外部。
如图9B所示，印刷机612可以使用诸如导电油墨的EMI屏蔽材料来印刷EMI屏蔽层420。特别地，印刷机612可以仅在囊封部分450的第二区域452上印刷不与天线图案434电连接的EMI屏蔽层420。此外，EMI屏蔽层420可以电连接到接地电路图案432。
如图9C所示，闪光灯613可以烧结及/或固化经印刷的EMI屏蔽层420。特别地，闪光灯613可以包括氙灯和通过强脉冲光(intense pulsed light，IPL)对EMI屏蔽层420进行光烧结的反射器。在示例性实施例中，闪光灯613可以用约0.1μs至约100μs的脉冲光辐射EMI屏蔽层420。脉冲光可以烧结包含于导电油墨中的金属颗粒或金属氧化物颗粒以形成EMI屏蔽层420。
参考图10A-10D，其说明了依序地图示根据本发明的各种实施例的半导体装置的制造方法的处理步骤的横截面图。参照半导体装置500、图5和图10A-10D来描述所述制造方法。
如图10A所示，第一囊封部分551可以囊封半导体晶粒110。进一步，印刷机612可以在第一囊封部分551的表面上印刷EMI屏蔽材料，以形成EMI屏蔽层520。特别地，第一囊封部分551的第一区域551a可以形成于半导体晶粒110的第一表面111上，第一囊封部分551的第二区域551b可以形成于半导体晶粒110的第三表面113上，并且具有预定厚度的EMI屏蔽层520可以印刷于第一囊封部分551的第一区域551a上，而不在第一囊封部分551的第二区域551b上形成EMI屏蔽层520。如图所示，第一囊封部分551的第二区域551b可以插入于第一和第二半导体晶粒110之间。特别地，第一囊封部分551的第二区域551b可以被插入于第一和第二半导体晶粒110的第三表面113之间的区域。
如图10B所示，闪光灯613可以用辐射光对形成于第一区域551a上的EMI屏蔽层520进行光烧结。特别地，EMI屏蔽层520可以形成为液相或凝胶相。来自闪光灯613的辐射光可以将液相或凝胶相的EMI屏蔽层520转换成在第一囊封部分551上刚性固化的固相。
如图10C所示，切割工具608可以将第一半导体晶粒110与第二半导体晶粒110分离。特别地，这种分离可导致分离的EMI屏蔽层520和第一囊封部分551的第二区域551b是共平面的。
在这种分离之后，包括第一囊封部分551和EMI屏蔽层520的第一半导体晶粒110可以通过质量回焊或热压缩而电连接到基板130，如图10D所示。线接合器611可以在第一囊封部分551附近形成多个EMI屏蔽线570。特别地，线接合器611可以将EMI屏蔽线570的第一端接合到EMI屏蔽层520，且将EMI屏蔽线570的第二端接合到基板130的接地电路图案332。
此后，第一囊封部分551、EMI屏蔽层520和EMI屏蔽线570可以被第二囊封部分552囊封，并且多个外部互连结构160可形成于基板130的底表面上。如上所述，一些实施例可以省略第二囊封部分552。在这样的实施例中，半导体装置可以具有暴露的EMI屏蔽层520和EMI屏蔽线570来销售。
以上所述仅是本发明的优选实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以优选实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案的范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (20)

1.一种半导体装置，其特征在于，包括：
半导体晶粒，包括第一表面、与所述第一表面相对的第二表面、形成于所述第一表面和所述第二表面之间的第三表面以及形成于所述第二表面上的多个互连结构；
EMI屏蔽层，其包括屏蔽所述半导体晶粒的所述第一表面的第一导电层和屏蔽所述半导体晶粒的所述第三表面的第二导电层；
基板，其电连接到所述半导体晶粒的所述多个互连结构；以及
囊封部分，其囊封所述EMI屏蔽层和所述基板。
2.根据权利要求1所述的半导体装置，进一步包括：
另一半导体晶粒，其与所述半导体晶粒水平地间隔开；
其中所述EMI屏蔽层的所述第二导电层介于所述半导体晶粒和所述另一半导体晶粒之间。
3.根据权利要求1所述的半导体装置，其中所述半导体晶粒包括：
接触垫，其电连接到所述多个互连结构中的互连结构；以及
接地电路图案，其电连接所述接触垫和所述EMI屏蔽层。
4.根据权利要求1所述的半导体装置，其中所述EMI屏蔽层包括选自导电聚合物、导电油墨、导电膏和导电箔的材料。
5.根据权利要求1所述的半导体装置，进一步包括填充所述半导体晶粒和所述基板之间的间隙的底部填充物。
6.根据权利要求1所述的半导体装置，其中所述EMI屏蔽层包括非溅射的EMI屏蔽层。
7.根据权利要求1所述的半导体装置，其中所述EMI屏蔽层包括铜箔。
8.根据权利要求1所述的半导体装置，其中所述EMI屏蔽层包括旋涂的EMI屏蔽层。
9.根据权利要求1所述的半导体装置，其中所述EMI屏蔽层包括喷射印刷的EMI屏蔽层。
10.一种半导体装置，包括：
半导体晶粒，其包括第一表面、与所述第一表面相对的第二表面、形成于所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；
非溅射的EMI屏蔽层，其屏蔽所述半导体晶粒的所述第一表面；
多个EMI屏蔽线，其围绕所述半导体晶粒的所述第三表面定位且电连接到所述非溅射的EMI屏蔽层；
基板，其电连接到所述半导体晶粒的所述多个互连结构；以及
囊封部分，其囊封所述非溅射的EMI屏蔽层、所述EMI屏蔽线和所述基板。
11.根据权利要求10所述的半导体装置，其中所述非溅射的EMI屏蔽层包括选自导电聚合物、导电油墨、导电膏和导电箔的材料。
12.根据权利要求10所述的半导体装置，其中所述多个EMI屏蔽线围绕且感应地屏蔽所述半导体晶粒的所述第三表面。
13.根据权利要求12所述的半导体装置，其中所述多个EMI屏蔽线与所述半导体晶粒的所述第三表面间隔开。
14.根据权利要求10所述的半导体装置，其中：
所述非溅射的EMI屏蔽层具有带有四边的矩形；以及
所述多个EMI屏蔽线沿着所述四边配置。
15.一种半导体装置，其特征在于，包括：
半导体晶粒，其包括第一表面、与所述第一表面相对的第二表面、形成于所述第一表面和所述第二表面之间的第三表面以及形成于所述第二表面上的多个互连结构；
基板，其电连接到所述半导体晶粒的所述多个互连结构；
第一囊封部分，其包括围绕所述半导体晶粒的所述第一表面的第一区域和围绕所述半导体晶粒的所述第三表面的第二区域；以及
EMI屏蔽层，其屏蔽所述第一囊封部分的所述第一区域和所述第二区域中的至少一个。
16.根据权利要求15所述的半导体装置，其中：
所述EMI屏蔽层屏蔽所述第一囊封部分的所述第二区域；以及
所述基板进一步包括通过所述第二区域暴露的天线图案。
17.根据权利要求15所述的半导体装置，进一步包括囊封所述第一囊封部分、所述EMI屏蔽层和所述基板的第二囊封部分。
18.根据权利要求17所述的半导体装置，其中所述EMI屏蔽层屏蔽所述第一囊封部分的所述第一区域。
19.根据权利要求15所述的半导体装置，进一步包括围绕所述半导体晶粒的所述第三表面定位且电连接到所述EMI屏蔽层的多个EMI屏蔽线。
20.根据权利要求15所述的半导体装置，其中所述EMI屏蔽层包括非溅射的EMI屏蔽层。
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