TW201838138A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201838138A
TW201838138A TW106116317A TW106116317A TW201838138A TW 201838138 A TW201838138 A TW 201838138A TW 106116317 A TW106116317 A TW 106116317A TW 106116317 A TW106116317 A TW 106116317A TW 201838138 A TW201838138 A TW 201838138A
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Taiwan
Prior art keywords
emi shielding
shielding layer
semiconductor device
semiconductor die
semiconductor
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TW106116317A
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English (en)
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TWI745372B (zh
Inventor
金舒永
娜捷明
金德宮
黃泰坤
莫 里斯 林廣
朴孫杉
金凱領
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艾馬克科技公司
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Abstract

本發明提供了具有EMI屏蔽層及/或EMI屏蔽線的半導體裝置及其製造方法。在示例性實施例中，半導體裝置包括半導體晶粒、屏蔽半導體晶粒的EMI屏蔽層和囊封EMI屏蔽層的囊封部分。在另一個示例實施例中，半導體裝置還包括從EMI屏蔽層延伸且屏蔽半導體晶粒的EMI屏蔽線。

Description

半導體裝置及其製造方法
本發明涉及半導體裝置及其製造方法。本案公開的實施例提供半導體裝置及其製造方法。
近年來的電子裝置，例如智慧型手機、膝上型電腦和平板電腦，包括配備有無線通信功能的多個無線半導體裝置。無線半導體裝置由於內建積體電路的時序頻率和高數據傳輸速度而產生電磁雜訊。為了抑制電磁雜訊，通常使用基板級“金屬屏蔽”方法。然而，基板級“金屬屏蔽”方法涉及可能導致低生產率和不良良率之複雜的製造過程。此外，複雜的製造過程可能阻礙利用該製造過程的電子裝置的小型化和薄化。
包括半導體晶粒及/或用EMI屏蔽處理的囊封部分之半導體裝置基本上與附圖中的至少一個一起顯示及/或描述，並且在申請專利範圍中更全面地闡述。
從以下描述和附圖將更充分地理解本發明的各種優點、態樣和新穎特徵以及各種支持實施例的說明性範例的細節。
100‧‧‧半導體裝置
110‧‧‧半導體晶粒
110A‧‧‧半導體晶粒/第一半導體晶粒
110B‧‧‧半導體晶粒/第二半導體晶粒
110W‧‧‧晶圓
111‧‧‧第一表面
112‧‧‧第二表面
113‧‧‧第三表面
114‧‧‧接觸墊
115‧‧‧內部互連結構/互連結構
115a‧‧‧焊料凸塊或焊料帽
116‧‧‧接地電路圖案
120‧‧‧EMI屏蔽層
121‧‧‧第一導電層
122‧‧‧第二導電層
130‧‧‧基板
131‧‧‧介電層
132‧‧‧上部電路圖案
133‧‧‧下部電路圖案
134‧‧‧電路圖案
135‧‧‧通孔
140‧‧‧底部填充物
150‧‧‧囊封部分
160‧‧‧外部互連結構
200‧‧‧半導體裝置
215‧‧‧內部互連結構/互連結構
300‧‧‧半導體裝置
320‧‧‧EMI屏蔽層
321‧‧‧導電箔
322‧‧‧銅層
323‧‧‧黏著層
332‧‧‧接地電路圖案
370‧‧‧EMI屏蔽線
400‧‧‧半導體裝置
420‧‧‧EMI屏蔽層
432‧‧‧接地電路圖案
434‧‧‧天線圖案
435‧‧‧絕緣層
450‧‧‧囊封部分
451‧‧‧第一區域
452‧‧‧第二區域
500‧‧‧半導體裝置
520‧‧‧EMI屏蔽層
551‧‧‧第一囊封部分
551a‧‧‧第一區域
551b‧‧‧第二區域
552‧‧‧第二囊封部分
570‧‧‧EMI屏蔽線
601‧‧‧晶圓安裝帶
602‧‧‧切割工具
603‧‧‧凸塊保護帶
604‧‧‧邊緣切割工具
605‧‧‧旋塗設備
606‧‧‧塗覆工具
607‧‧‧晶圓安裝帶
608‧‧‧切割工具
609‧‧‧拾取工具
610‧‧‧彈出銷
611‧‧‧線接合器
612‧‧‧印刷機
613‧‧‧閃光燈
在整個附圖和詳細描述中使用通用附圖標記來表示相同或相似的元件。
圖1A和1B是根據本發明的各種示例性實施例的半導體裝置和各自具有EMI屏蔽層的半導體晶粒的橫截面圖。
圖2A和2B是根據本發明的各種示例性實施例的半導體裝置和各自具有EMI屏蔽層的半導體晶粒的橫截面圖。
圖3A和3B是根據本發明的各種示例性實施例的半導體裝置和具有EMI屏蔽層的半導體晶粒的橫截面圖，以及圖3C是EMI屏蔽層和EMI屏蔽線的平面圖。
圖4A和4B是根據本發明的各種示例性實施例的半導體裝置的橫截面圖和側視圖。
圖5是根據本發明的各種示例性實施例的半導體裝置的橫截面圖。
圖6是根據本發明的各種示例性實施例的半導體裝置的製造方法的流程圖。
圖7A-7M是依序地說明根據本發明的各種示例性實施例的半導體裝置的製造方法的製程步驟的橫截面圖。
圖8A-8J是依序地說明根據本發明的各種示例性實施例的半導體裝置的製造方法的製程步驟的橫截面圖。
圖9A-9C是依序地說明根據本發明的各種示例性實施例的半導體裝置的製造方法的製程步驟的橫截面圖。
圖10A-10D是依序地說明根據本發明的各種示例性實施例 的半導體裝置的製造方法的製程步驟的橫截面圖。
圖11說明了可以替代圖8C的旋塗製程步驟之用於本發明的各種示例實施例之銅箔層壓製程步驟。
如本文所使用的，“及/或”是指藉由“及/或”連接的列表中的任何一個或多個項目。作為範例，“x及/或y”表示三元素集合{(x)，(y)，(x，y)}中的任何元素。也就是說，“x及/或y”表示“x和y中的一個或兩個”。作為另一範例，“x、y及/或z”表示七元素集合{(x)，(y)，(z)，(x，y)，(x，z)，(y，z)，(x，y，z)}。也就是說，“x、y及/或z”表示“x、y和z中的一個或多個”。如本文中所使用的用語“例如”和“舉如”表示非限制性範例、實例或圖示。
本文使用的術語僅用於描述具體實施例的目的，並不意圖限制本發明。如本文中所使用的單數形式也意圖包括複數形式，除非上下文另有明確指出。進一步理解成，在本說明書中使用的用語“包括”、“包含”、“包括有”、“包含有”、“具有”、“含有”、“有”及相似用詞指定了所描述的特徵、整數、步驟、操作、元件及/或組件的存在，但不排除存在或添加一個或多個其他特徵、整數、步驟、操作、元件、組件及/或其群組之存在。
應當理解的是，儘管用語第一、第二等可以在本文中用於描述各種元件，但是這些元件不應受這些用語的限制。這些用語僅用於區分一個元件和另一個元件。因此，例如，在不脫離本發明的教導的情況下，可以將下面討論的第一元件、第一組件或第一部分稱為第二元件、第二組 件或第二部分。類似地，可以使用諸如“上”、“下”、“側”、“頂”、“底”以及類似用詞之各種空間用語而以相對方式區分一個元件與另一元件。然而，應當理解的是，組件可以以不同的方式定向，例如，半導體裝置可以側向轉動，使得其“頂”表面為水平面向並且其“側”表面為垂直面向，而不脫離本發明的教導。
參見圖參考圖1A和1B，根據本發明的各種示例性實施例提供半導體裝置100的橫截面圖。如圖所示，半導體裝置100可以包括半導體晶粒110A和110B、EMI屏蔽層120、基板130和囊封部分150。另外，半導體裝置100還可以包括外部互連結構160。
半導體晶粒110A和110B中的每一個可以具有基本上平坦的第一表面111、與第一表面111相對的基本上平坦的第二表面112和形成在第一表面111和第二表面112之間的第三表面113。另外，每個半導體晶粒110A和110B可以包括形成在第二表面112上的至少一個或多個接觸墊114(例如，接合墊或再分佈墊)，以及連接到內部接觸墊的至少一個或多個內部互連結構115。基本上，第一表面111可以包括每個半導體晶粒110A和110B的頂表面，第二表面112可以包括每個半導體晶粒110A和110B的底表面，並且第三表面可以包括每個半導體晶粒110A和110B的四個側面中的一個以上側面。
在圖1A和圖1B中顯出了半導體裝置100具有兩個半導體晶粒110A和110B。然而，在一些實施例中，半導體裝置100可以包括單個半導體晶粒或比兩個還多的半導體晶粒。
內部互連結構115的範例可以包括但不限於例如微型凸 塊、金屬柱、焊料凸塊或焊球之各種類型的結構，其將半導體晶粒110A和110B電接合到基板130。在一個範例中，內部互連結構115可以包括具有焊料凸塊或焊料帽115a的銅柱，其藉由回焊或熱壓縮而接合到基板130。內部互連結構115可以具有但不限於約20-50微米(μm)的間距及/或大約90-100μm的間距。
同時，半導體晶粒110A和110B可以包括與半導體晶圓分離的積體電路晶粒，並且其範例可以包括但不限於電路，諸如數位信號處理器(digital signal processor，DSP)、微處理器、網絡處理器、電源管理處理器、音頻處理器、RF電路、無線基頻系統單晶片(system-on-chip，SoC)處理器、感測器和特定應用積體電路(application specific integrated circuit，ASIC)。
EMI屏蔽層120可以包括屏蔽半導體晶粒110A和110B的第一表面111之基本上平坦的第一導電層121和屏蔽半導體晶粒110A和110B的第三表面113之基本上平坦的第二導電層122。以這種方式，第一導電層121和第二導電層122可以提供具有屏蔽半導體晶粒110A和110B的頂表面和四個側面的帽形狀之EMI屏蔽層120。此外，當半導體裝置100包括與第二半導體晶粒110B水平間隔開的第一半導體晶粒110A時，EMI屏蔽層120可以填充第一和第二半導體晶粒110A和110B之間的間隙。特別地，EMI屏蔽層120的第二導電層122可以被配置為使得第二導電層122被插入到第一和第二半導體晶粒110A和110B的第三表面113之間的區域中。
EMI屏蔽層120可以防止由半導體晶粒110A和110B產生的電磁波輻射到外部。此外，EMI屏蔽層120可以防止外部施加的電磁波進入 半導體晶粒110A和110B。在整個詳細描述中，EMI屏蔽層120的這種功能可以被稱為EMI屏蔽。
為了能夠屏蔽電磁波，EMI屏蔽層120可以使用各種導電材料形成。用於EMI屏蔽層120的合適導電材料的實例可包括但不限於銅(Cu)、鎳(Ni)、金(Au)、銀(Ag)、鉑(Pt)、鈷(Co)、鈦(Ti)、鉻(Cr)、鋯(Zr)、鉬(Mo)、釕(Ru)、鉿(Hf)、鎢(W)、錸(Re)、石墨或碳黑。在一些實施例中，EMI屏蔽層120還可以包括金屬顆粒和用於結合EMI屏蔽層內部的金屬顆粒的結合劑。在其它實施例中，EMI屏蔽層120還可以包括金屬顆粒和用於將金屬顆粒附著到半導體晶粒110A和110B的表面的結合劑。
此外，EMI屏蔽層120可以包括摻雜有金屬或金屬氧化物的導電聚合物，例如聚乙炔、聚苯胺、聚吡咯、聚噻吩或聚硫氮化物。此外，EMI屏蔽層120可以包括具有諸如碳黑、石墨和銀的導電材料的導電油墨。
EMI屏蔽層120的厚度可以在例如約0.1μm至約1000μm的範圍內，優選為1μm至100μm的範圍內，更優選為3μm至30μm的範圍內，但是本發明的態樣不限於此。當EMI屏蔽層120的厚度小於0.1μm時，EMI屏蔽層120的EMI屏蔽效率可能小於期望的閾值，並且當EMI屏蔽層120的厚度大於1000μm時，形成EMI屏蔽層120所需的時間可能延長到經濟上可行的時段之外。
此外，EMI屏蔽層120可以例如藉由諸如旋塗、噴塗、印刷、層壓及/或其組合之各種非濺射製程來形成，但不限於此。如本文中所用的術語“非濺射”和相關詞和片語係用於區分已經透過濺射製程形成的層與 已經由諸如旋塗、噴塗、印刷、層壓及/或這些製程的組合形成的EMI屏蔽層120的層。這種非濺射層可以具有優於濺射層的各種優點。例如，與濺射層相比，非濺射層可以每單位小時(unit per hour，UPH)更高的產量、降低操作成本、降低工具成本以及更好地控制成形層的厚度，特別是沿著側壁。
如上所述，EMI屏蔽層120不形成在囊封部分150的表面上，而是直接形成在半導體晶粒110A和110B(例如，矽晶粒)的表面上。因此，根據本發明的各種實施例的半導體裝置100可以表現出改善的EMI屏蔽效率。特別地，如果在囊封部分150的外表面上形成EMI屏蔽層120，則EMI屏蔽層120將與半導體晶粒110A和110B隔開預定間隙。這種間隔可以允許電磁波從半導體晶粒110A、110B輻射到外部，或者透過所述間隙進入到半導體晶粒110A、110B的內部。然而，透過直接形成在半導體晶粒110A和110B的表面上的EMI屏蔽層120，在EMI屏蔽層120和半導體晶粒110A和110B中的每一個之間沒有間隙。因此，EMI屏蔽層120可以顯著地抑制電磁波從半導體晶粒110A、110B向外部輻射，或者顯著抑制電磁波從外部進入半導體晶粒110A、110B。
此外，半導體晶粒110A和110B中的每一個還可以包括連接到接觸墊114的接地電路圖案116。接地電路圖案116可以直接電連接到EMI屏蔽層120(參見圖1B)。接觸墊114可以電連接到內部互連結構115。另外，內部互連結構115可以電連接到基板130的上部電路圖案132。接觸墊114、內部互連結構115和基板130的上部電路圖案132可以電連接到接地電路圖案116，並且可以提供用於接地的結構。因此，EMI屏蔽層120可 以接地，並且更有效地防止電磁波輻射或感應。在一些實施例中，一些內部互連結構115可以用作接地凸塊，一些內部互連結構115可以用作信號凸塊，並且一些內部互連結構115可以用作功率凸塊。在這樣的實施例中，接地電路圖案116可以電連接到用作接地凸塊的內部互連結構115。
基板130可以包括用於半導體晶粒110A和110B的機械支撐結構及/或被動裝置。為此，基板130可以包括介電層131和形成在介電層131的頂表面上的上部電路圖案(例如，導電跡線)132。上部電路圖案132可以電連接到每個半導體晶粒110A和110B的內部互連結構115。基板130還可以包括電連接到形成在介電層131的底表面上的外部電路板之下部電路圖案133。特別地，基板130還可以包括在上部電路圖案132和下部電路圖案133之間的複數個電路圖案134和通孔135。進一步，複數個電路圖案134和通孔135可以電連接到上部電路圖案132及/或下部電路圖案133。基板130的範例可以包括但不限於剛性印刷電路板、撓性印刷電路板、有芯電路板、無芯電路板和積層電路板。
進一步，底部填充物140還可以填充每個半導體晶粒110A和110B與基板130之間的區域。底部填充物140可以保護內部互連結構115並且可以將半導體晶粒110A和110B機械地連接到基板130。在將半導體晶粒110A和110B與基板130電連接之前，可以將底部填充物140施加到半導體晶粒110A和110B及/或基板130。在一些實施例中，在半導體晶粒110A和110B與基板130電連接之後，底部填充物140可透過毛細作用填充每個半導體晶粒110A和110B與基板130之間的間隙。此外，底部填充物140可以包括具有或不具有有機或無機填料的非導電膏。
底部填充物140被配置為使得底部填充物140基本上黏著到EMI屏蔽層120。特別地，底部填充物140可以黏著到形成在半導體晶粒110A和110B的第三表面上的第二導電層122的底表面和側表面。對於透過旋塗、噴塗及/或印刷形成EMI屏蔽層120的實施例，與半導體晶粒110A和110B的表面相比，EMI屏蔽層120可具有非常粗糙的多孔表面。具體地，EMI屏蔽層120可以表現出比半導體晶粒110A和110B高得多的粗糙度。因此，由於具有相對高粗糙度的底部填充物140直接黏著到EMI屏蔽層120，所以底部填充物140和EMI屏蔽層120之間的黏著力得到改善。此外，可以透過底部填充物140改善EMI屏蔽層120/半導體晶粒110A和110B與基板130之間的機械黏著力。
在一些實施例中，可以不提供底部填充物140。如果囊封部分150(下面更詳細地描述)的填料尺寸小於半導體晶粒110A、110B和基板130之間的間隙的尺寸，則囊封材料可以充分地注入且填充間隙。在這樣的實施例中，可以不提供底部填充物140。
囊封部分150(例如，囊封構件或囊封劑)可以囊封EMI屏蔽層120、底部填充物140和基板130。囊封部分150可以保護EMI屏蔽層120、底部填充物140和基板130免受外來環境影響。囊封部分150以及本文所述的其它囊封部分的範例可包括但不限於環氧樹脂模塑化合物、環氧模塑樹脂等。囊封部分150可以將在基板130上的EMI屏蔽層120完全囊封。在一些實施例中，囊封部分150可以暴露EMI屏蔽層120的一部分。例如，囊封部分150可以不形成在EMI屏蔽層120的第一導電層121上。這樣，EMI屏蔽層120的第一導電層121可以直接暴露於外部。更具體地， EMI屏蔽層120的第一導電層121的頂表面可以與囊封部分150的頂表面共平面。在這樣的實施例中，半導體晶粒110A和110B可以具有更高的熱輻射性能。
如果囊封部分150完全囊封EMI屏蔽層120，則可能導致囊封部分150和EMI屏蔽層120之間的高黏著力。因此，可以消除囊封部分150和EMI屏蔽層120之間的界面分層。特別地，由於EMI屏蔽層120的粗糙度高，如上所述，囊封部分150和EMI屏蔽層120之間所表現的黏著力進一步增加。此外，如果囊封部分150完全囊封EMI屏蔽層120，囊封部分150可以保護EMI屏蔽層120免受外部物理和化學衝擊。
外部互連結構160的範例可以包括但不限於金屬柱、焊料凸塊、焊球、凸塊或連接盤(land)。外部互連結構160可以包括具有大約100-200μm的尺寸的凸塊或具有大約20-100μm的尺寸的凸塊/柱。當在外部互連結構160中使用焊料凸塊時，外部互連結構160可以包括一種或多種焊料金屬，所述焊料金屬在比其它金屬低的溫度下熔化且可以在熔化和冷卻製程期間在外部互連結構160和外部電路板或另一裝置之間提供物理和電接合。外部互連結構160的範例可以包括但不限於球柵陣列(BGA)及/或平面柵格陣列(LGA)。雖然說明了在外部互連結構160中使用的焊球，但是外部互連結構160可以包括各種類型的結構。
如上所述，根據本發明的各種實施例，EMI屏蔽層120直接形成在半導體晶粒110A和110B的第一表面111(例如，頂表面)及/或第三表面113(例如，側表面)。EMI屏蔽層120的這種形成可以提高EMI屏蔽層120的生產率和良率，並且可以提供具有改善的EMI屏蔽效率之半導 體裝置100。此外，由於EMI屏蔽層120嵌入到囊封部分150中，所以可以安全地保護半導體裝置100免受外部環境的影響。此外，EMI屏蔽層120的這種形成可以有助於半導體裝置100的小型化和薄化。
參見圖2A和2B，說明了根據本發明的各種示例性實施例的半導體裝置200的橫截面圖。如圖所示，半導體裝置200可以與半導體裝置100類似的方式形成。然而，半導體裝置200可以包括內部互連結構215，其包括將半導體晶粒110A和110B連接到基板130的導電球。在比較後，圖1A和1B所示的半導體裝置100的內部互連結構115包括具有焊料的導電柱(例如，銅柱)。
內部互連結構215(諸如焊球)可以藉由質量回焊將半導體晶粒110A和110B電連接到基板130，這可以改善半導體裝置200的生產率。此外，互連結構215(諸如焊球)可以比其它內部互連結構(諸如導電柱)更簡化的方式形成。因此，互連結構215可以比互連結構115低的成本形成，從而與半導體裝置100相比降低了半導體裝置200的製造成本。
圖3A和3B圖示了根據本發明的各種示例性實施例的半導體裝置300和具有EMI屏蔽層320的半導體晶粒110的橫截面圖。圖3C提供EMI屏蔽層320和EMI屏蔽線370的平面圖。
如圖3A-3C所示，根據本發明的各種示例性實施例的半導體裝置300可以包括半導體晶粒110、僅在半導體晶粒110的第一表面111(例如，頂表面)上形成的EMI屏蔽層320以及將EMI屏蔽層320電連接到基板130之複數個EMI屏蔽線370。特別地，EMI屏蔽層320可以僅形成在半導體晶粒110的第一表面111上，但不能形成在半導體晶粒的第三表面 113上。因此，囊封部分150可以直接黏著到形成在半導體晶粒110的第一表面111上的EMI屏蔽層320和黏著到半導體晶粒110的第三表面113。
此外，EMI屏蔽線370可以將EMI屏蔽層320電連接到基板130的接地電路圖案332。特別地，EMI屏蔽線370可以與半導體晶粒110的第三表面113基本上平行。為此，EMI屏蔽線370的第一端可以球接合(或縫合)到EMI屏蔽層320，並且EMI屏蔽線370的第二端可以縫合(或球接合)到接地電路圖案332。
EMI屏蔽層320的平面形狀可以是但不限於具有四邊的大致矩形形狀。基板130的接地電路圖案332的平面形狀也可以是具有四邊的大致矩形形狀。EMI屏蔽線370可以沿著EMI屏蔽層320的四邊以恆定的間距佈置。每個EMI屏蔽線370可將EMI屏蔽層320的一側電連接到接地電路圖案的相應側332。
EMI屏蔽線370可以與半導體晶粒110的第三表面113隔開預定的距離，並且可以屏蔽半導體晶粒110。EMI屏蔽線370之間的距離或間距可根據要屏蔽的電磁波的波長範圍而改變。例如，要屏蔽的電磁波的波長越短，EMI屏蔽線370之間的距離或間距越小。構成EMI屏蔽線370的材料的範例可以包括但不限於各種金屬，諸如金(Au)、銀(Ag)、銅(Cu)或鋁(Al)。
囊封部分150可以囊封且保護半導體晶粒110、EMI屏蔽層320和在基板130上的EMI屏蔽線370免受外部物理和化學環境的影響。反過來，EMI屏蔽層320和EMI屏蔽線370可以感應地屏蔽半導體晶粒110免受電磁波的影響。
如上所述，根據本發明的各種實施例，EMI屏蔽層320和EMI屏蔽線370圍繞半導體晶粒110形成法拉第籠。這種法拉第籠可以防止由半導體晶粒110產生的電磁波輻射到外面。此外，法拉第籠可以防止外部電磁波進入和干擾半導體晶粒110。
參考圖4A和4B，說明了根據本發明的各種示例性實施例的半導體裝置400的橫截面圖和側視圖。如圖4A和4B所示，半導體裝置400可以包括半導體晶粒110、基板130、囊封部分450和EMI屏蔽層420。囊封部分450可以包括粗略地囊封半導體晶粒110的第一表面111的第一區域451及粗略地囊封半導體晶粒110的第三表面113的第二區域452。
EMI屏蔽層420可以屏蔽囊封部分450的第一區域451和至少一部分第二區域452。如圖所示，EMI屏蔽層420可以屏蔽囊封部分450的第二區域452，但是本發明的態樣不限於此。相反地，EMI屏蔽層420可以屏蔽囊封部分450的第一區域451。
基板130還可以包括形成在其頂表面上的天線圖案434。如果天線圖案434由EMI屏蔽層420囊封，則EMI屏蔽層將防止或基本上減少天線圖案434作為天線的功能。因此，如圖所示，天線圖案434可以從EMI屏蔽層420及/或囊封部分450露出。
為此，EMI屏蔽層420可以形成在例如囊封部分450的第二區域452上，但不形成在例如天線圖案434上。絕緣層435可以插入在EMI屏蔽層420和天線圖案434之間。或者，EMI屏蔽層420和天線圖案434可以彼此隔開預定距離。此外，EMI屏蔽層420可以電連接到形成在基板130上的接地電路圖案432。由於EMI屏蔽層420形成在與天線圖案434間隔開 的區域(例如，囊封部分450的第二區域452)，EMI屏蔽層420可以有效地屏蔽來自半導體晶粒110的電磁波，同時不妨礙形成在基板130上的天線圖案434的操作。
參考圖5，說明了根據本發明的各種示例性實施例的半導體裝置500的橫截面圖。如圖5所示，半導體裝置500可以包括半導體晶粒110、基板130、囊封半導體晶粒110的第一囊封部分551、形成在第一囊封部分551上的EMI屏蔽層520、連接EMI屏蔽層520至基板130的EMI屏蔽線570以及囊封第一囊封部分551、EMI屏蔽層520和EMI屏蔽線570的第二囊封部分552。
第一囊封部分551可以囊封半導體晶粒110的第一表面111和第三表面113。第一囊封部分551的第一區域551a可以囊封半導體晶粒110的第一表面111。第一囊封部分551的第二區域551b可以囊封囊封部分551的第三表面113。
EMI屏蔽層520可以形成在第一囊封部分551的第一區域551a上。特別地，EMI屏蔽層520可以形成在第一囊封部分551的對應於半導體晶粒110的第一表面111之第一區域551a上。第一囊封部分551的第一區域551a可以形成為基本上平坦的。EMI屏蔽層520也可以形成為具有基本上平坦的板。
EMI屏蔽線570可以將EMI屏蔽層520電連接到設置在基板130上的接地電路圖案332。在一個範例中，EMI屏蔽線570可形成為與第一囊封部分551的第二區域551b基本上平行。另外，EMI屏蔽線570可以與第一囊封部分551的第二區域551b間隔開預定距離。特別地，可以形成 EMI屏蔽線570以屏蔽第一囊封部分551(例如，半導體晶粒110的第三表面)。
第二囊封部分552可以囊封第一囊封部分551、EMI屏蔽層520和EMI屏蔽線570。第二囊封部分552的範例可以包括但不限於與第一囊封部分552相同或不同的材料。在一些實施粒中，第二囊封部分552可以具有比第一囊封部分551更小的模數。因此，與第一囊封部分551相比，第二囊封部分552可以有效地吸收或減輕外部衝擊。
如上所述，半導體晶粒110被第一囊封部分551囊封。EMI屏蔽層520形成在第一囊封部分551的表面上，從而保護半導體晶粒110免受外部環境的影響。EMI屏蔽層520可以進一步提供帶有改善的EMI屏蔽效率之半導體裝置500。由於半導體晶粒110被第一囊封部分551和複數個EMI屏蔽線570兩者囊封，所以半導體裝置500具有改善的EMI屏蔽效率。
在一些實施例中，可以省略第二囊封部分552。在這樣的實施例中，EMI屏蔽層520和EMI屏蔽線570可以暴露於外部。進一步，未被EMI屏蔽層520覆蓋的第一囊封部分551的一部分、未被第一囊封部分552覆蓋的基板130的一部分和被動裝置可以暴露於外部。然而，EMI屏蔽層520和EMI屏蔽線570仍然在半導體晶粒110周圍形成法拉第籠。如上所述，法拉第籠可以防止由半導體晶粒110產生的電磁波輻射到外部，並且可以防止外部電磁波進入和干擾半導體晶粒110。
參照圖6，說明了根據本發明的各種示例性實施例的半導體裝置的製造方法的流程圖。如圖所示，製造方法可以包括在晶圓的前側(例如，半導體晶粒的第二表面)上形成互連結構之晶圓凸塊製程步驟(S1) 和在晶圓的背側(例如，第一表面)上層疊晶圓安裝帶之晶圓安裝帶層壓步驟(S2)。所述方法還可以包括沿著路線將晶圓分離成各個半導體晶粒之晶圓切割步驟(S3)以及在晶圓的前側上層疊凸塊保護帶之凸塊保護帶層壓步驟(S4)。
所述方法還可以包括自晶圓剝離晶圓安裝帶之晶圓安裝帶剝離步驟(S5)以及切割凸塊保護帶的邊緣且移除其之邊緣切割步驟(S6)。此外，所述方法可以包括在晶圓的背側上旋塗EMI屏蔽層之EMI屏蔽層旋塗步驟(S7)和固化或燒結塗覆的EMI屏蔽層之固化或燒結步驟(S8)。
所述方法還可以包括在晶圓的背側上層壓經固化或燒結的晶圓安裝帶之晶圓安裝帶層壓步驟(S9)以及自晶圓的前側剝離凸塊保護帶之凸塊保護帶剝離步驟(S10)。此外，所述方法可以包括將晶圓分離成單個半導體晶粒或複數個半導體晶粒之切割步驟(S11)以及使用拾取工具拾取經分離的半導體晶粒之晶粒拾取步驟(S12)。所述方法也可以包括將半導體晶粒附接到基板之晶粒附接步驟(S13)。
參考圖7A-7M，其說明了依序地圖示根據本發明的各種示例性實施例的半導體裝置的製造方法的製程步驟的橫截面圖。特別地，參照半導體裝置100、圖1A、1B、6和7A-7M來描述所述製造方法。
如圖7A所示，在晶圓凸塊製程步驟(S1)中，在晶圓110W的前側形成有複數個內部互連結構115。特別地，複數個內部互連結構115可以形成在形成在晶圓110W上的各個半導體晶粒110的前側(例如，第二表面112)上。各種類型的內部互連結構115的範例可以包括但不限於微凸塊、金屬柱、焊料凸塊、焊球等
如圖7B所示，在晶圓安裝帶層壓步驟(S2)中，晶圓安裝帶601可以安裝在晶圓110W的背側上。特別地，晶圓安裝帶601可以安裝在形成在晶圓110W上的半導體晶粒110的第一表面111上。儘管未圖示，晶圓安裝帶601可以由大致圓形的安裝環支撐。更具體地，晶圓110W的背側可以臨時黏著到由圓形的安裝環支撐的晶圓安裝帶601。
如圖7C所示，在晶圓切割步驟(S3)中，各個半導體晶粒110可以使用例如金剛石刀片、金剛石磨輪或雷射束的切割工具602沿著形成在晶圓110W上的路線分離。因此，由於這種晶圓切割，形成在晶圓110W上的各個半導體晶粒110可以彼此隔開預定距離。此外，晶圓切割可以將各個半導體晶粒110保持半導體晶粒110仍然黏著到晶圓安裝帶601的狀態。
如圖7D所示，在凸塊保護帶層壓步驟(S4)中，可以在包括彼此間隔開的複數個半導體晶粒110的晶圓110W上層疊凸塊保護帶603。特別地，凸塊保護帶603可以臨時黏著到晶圓110W的前側。形成在晶圓110W的前側上的內部互連結構115可以在製造製成期間被凸塊保護帶603保護。
如圖7E所示，在晶圓安裝帶剝離步驟(S5)中，黏著在晶圓110W背側的晶圓安裝帶601可以被剝離。因此，晶圓110W的背側可以暴露於外部。特別地，晶圓安裝剝離步驟可以使分離的複數個半導體晶粒110中的每一個的第一表面111和第三表面113暴露於外部。然而，晶圓安裝帶剝離步驟可以保持半導體晶粒110或晶圓110W的前側(例如第二表面112)處於半導體晶粒110保持黏著到凸塊保護帶603的狀態。
如圖7F所示，在邊緣切割步驟(S6)中，邊緣切割工具604可以切割對應於晶圓110W的圓周邊緣之凸塊保護帶603的圓周邊緣。以這種方式，延伸超過晶圓110W的圓周邊緣之多餘的凸塊保護帶603因而藉由邊緣切割工具604移除。因此，晶圓110W和凸塊保護帶603可以在邊緣切割步驟(S6)之後具有相同的平面形狀。
如圖7G所示，在EMI屏蔽層旋塗步驟(S7)中，晶圓110W可以經由凸塊保護帶603安裝在旋塗設備605上。然後可以藉由塗覆工具606將EMI屏蔽層120旋塗在晶圓110W的背側上。因此，旋塗設備602可以不僅在半導體晶粒110的頂表面(例如，第一表面111)上塗覆EMI屏蔽層120，而且還可以在半導體晶粒110的側表面(例如，第三表面113)上塗覆EMI屏蔽層120。為此，旋塗設備605可以使用包括金屬顆粒、用於結合金屬顆粒的結合劑和溶劑之高黏性塗覆溶液或漿料。在用於EMI屏蔽層120的高黏性漿料塗覆在晶圓110W的背側上之後，旋塗設備605可以高速旋轉晶圓110W，使得EMI屏蔽層120均勻地分佈在半導體晶粒110的第一及第三表面111和113上。在一些實施例中，EMI屏蔽層120可以由例如導電聚合物、導電油墨或導電膏形成。
如圖7H所示，在固化或燒結步驟(S8)中，形成在晶圓110W的背側上的EMI屏蔽層120可以透過熱及/或光來固化及/或燒結。例如，當EMI屏蔽層120是由可熱固化材料製成時，可以向EMI屏蔽層120施加熱，及/或當EMI屏蔽層120是由可光固化材料製成時，可以向EMI屏蔽層120施加光。包含在漿料中的溶液可以透過固化及/或燒結製程而被完全揮發除去。結果，只有導電金屬或導電聚合物和結合劑可能殘留在EMI屏蔽層120 中。
如圖7I所示，在晶圓安裝帶層壓步驟(S9)中，晶圓安裝帶607可以再次層壓在經固化及/或燒結的EMI屏蔽層120的表面上。
如圖7J所示，在凸塊保護帶剝離步驟(S10)中，可剝離黏著到晶圓110W的前側(例如，第二表面112)的凸塊保護帶603。因此，晶圓110W的前側和內部互連結構115可以暴露於外部。
如圖7K所示，在切割步驟(S11)中，各個半導體晶粒110或複數個半導體晶粒110透過諸如金剛石磨輪或雷射束的切割工具608自晶圓110W分離。切割工具608可以切鋸在每個半導體晶粒110和其相鄰的半導體晶粒110之間形成的EMI屏蔽層120。因此，單個半導體晶粒110可以被分離，或者一群半導體晶粒可以自晶圓110W分離。切割工具608的寬度可以小於形成在每個半導體晶粒110及其相鄰半導體晶粒110之間的間隙中的EMI屏蔽層120的厚度或寬度。因此，即使在切割之後，EMI屏蔽層120可以保持在半導體晶粒110的側表面(例如，第三表面113)上。殘留在半導體晶粒110的第三表面113上的EMI屏蔽層120的厚度可以在例如約0.1μm至約1000μm的範圍內，或者在1μm至100μm的較窄範圍內，或者在10μm至30μm的更窄範圍內，但本發明的態樣不限於此。
如圖7L所示，在晶粒拾取步驟(S12)中，彈出銷610可以向上推動相關的半導體晶粒110。拾取工具609可以從晶圓安裝帶607拾取且移除相關的半導體晶粒110。拾取工具609可以進一步將相關的半導體晶粒110移動到預定位置。
如圖7M所示，在晶粒附接步驟(S13)中，拾取工具609 可以將具有EMI屏蔽層120的優質半導體晶粒110轉移到矩形基板130或單獨的晶圓托盤。放置在基板130上的半導體晶粒110可以透過質量回焊或熱壓縮而與基板130電連接。此後，依次進行底部填充步驟、囊封步驟和外部互連結構形成步驟。
如上所述，根據本發明的示例性實施例的半導體裝置100的製造方法允許具有EMI屏蔽層120的半導體晶粒110以大規模低成本快速大量生產。因此，根據本發明的實施例，具有EMI屏蔽層120的半導體晶粒110可以高良率/高生產率且以低成本生產。此外，由於EMI屏蔽層120直接形成在半導體晶粒110的表面上，所以帶有改良的小型化和薄化之半導體裝置100可以具有高的EMI屏蔽效率。此外，由於EMI屏蔽層120嵌入到囊封部分150中，所以可以保護半導體裝置100免受外部環境的影響。
參照圖8A-8J，其說明了依序地圖示根據本發明的各種示例性實施例的半導體裝置的製造方法的製程步驟的橫截面圖。特別是，參照半導體裝置300、圖3A-3C和圖8A-8J來描述所述製造方法。
如圖8A所示，凸塊保護帶603可以層疊在經凸塊製程的晶圓110W的前側(例如，第二表面112)上。晶圓110W的背側(例如，第一表面111)可以保持暴露於外部。
如圖8B所示，邊緣切割工具604可以切割對應於晶圓110W的周邊邊緣之凸塊保護帶603的區域。因此，可以藉由邊緣切割工具604來移除延伸超過晶圓110W的圓周邊緣之凸塊保護帶603。在這種切割和移除之後，晶圓110W和凸塊保護帶603可以具有基本上相同的平面形狀。
如圖8C所示，晶圓110W可以安裝在旋塗設備605上。特 別地，晶圓110W可以經由凸塊保護帶603黏著到旋塗設備605。用於形成EMI屏蔽層320的漿料然後可以旋塗在晶圓110W的背側上。除了旋塗之外，EMI屏蔽層320也可以透過噴塗、印刷及/或層壓形成。
在其它實施例中，EMI屏蔽層320可以使用諸如銅箔的導電箔321形成。特別地，在這樣的實施例中，如圖11所示，具有銅層322和黏著層323的導電箔321可以在晶圓110W的背側上被滾壓或真空層疊。在一些實施例中，銅層322可以具有至少12μm的厚度，並且黏著層323可以具有至少10μm的厚度，從而導致銅箔321具有至少22μm的厚度。
由於晶圓110W在旋塗或層壓EMI屏蔽層320之前沒有被切割，所以不用如圖7A-7M所示的方法在每個半導體晶粒110及其相鄰的半導體晶粒110之間產生間隙。因此，圖8A-8J的方法中的旋塗設備605不在相鄰的半導體晶粒110之間形成EMI屏蔽層320，而僅在晶圓110W的背面上形成。
如圖8D所示，經旋塗的EMI屏蔽層320可以透過熱及/或光來固化及/或燒結。然後可以將晶圓安裝帶607層壓在經固化及/或燒結的EMI屏蔽層320的表面上，如圖8E所示。如圖8F所示，可以剝離和去除凸塊保護帶603。因此，晶圓110W的前側可以暴露於外部。
如圖8G所示，可以透過諸如金剛石磨輪或雷射束的切割工具608沿著設置在晶圓110W上的路線進行切割。形成在晶圓110W上的複數個半導體晶粒110可以透過執行個別地切割或群組地切割來分離。結果，複數個半導體晶粒110的第三表面113可以直接暴露於外部。特別地，複數個半導體晶粒110的第三表面113可以直接暴露於外部，而EMI屏蔽層320 屏蔽複數個半導體晶粒110的第一表面111。
如圖8H所示，透過拾取工具609和彈出銷610的操作，從晶圓110W拾取分離的單個或一群半導體晶粒110。如圖8I所示，半導體晶粒110可以被放置在基板130上。以這種方式，EMI屏蔽層320可以僅形成在半導體晶粒110的頂表面(例如，第一表面111)上。在半導體晶粒110被拾取並且放置在基板130上之後，半導體晶粒110的內部互連結構115可以透過質量回焊或熱壓縮而電連接到基板130。
如圖8J所示，線接合器611可以經由EMI屏蔽線370而將形成在半導體晶粒110上的EMI屏蔽層320電連接到基板130的接地電路圖案。特別地，線接合器611可以複數個EMI屏蔽線370圍繞半導體晶粒110。因此，半導體晶粒110的頂表面(例如，第一表面111)可以透過EMI屏蔽層320屏蔽電磁波。半導體晶粒110的側表面(例如，第三表面113)可以透過EMI屏蔽線370屏蔽電磁波。
圖9A-9C說明了依序圖示根據本發明的各種示例性實施例的半導體裝置的製造方法的製程步驟的橫截面圖。特別地，參照半導體裝置400、圖4A-4B和圖9A-9C來描述所述製造方法。
如圖9A所示，放置在基板130上的半導體晶粒110可以由半導體裝置400的囊封部分450囊封。此外，基板130的天線圖案434可能暴露於外部。囊封部分450可以被分成囊封半導體晶粒110的第一表面111之第一區域451和囊封半導體晶粒110的第三表面113之第二區域452。天線圖案434可以被暴露並且可以經由囊封部分450的第二區域452突出到達外部。
如圖9B所示，印刷機612可以使用諸如導電油墨的EMI屏蔽材料來印刷EMI屏蔽層420。特別地，印刷機612可以僅在囊封部分450的第二區域452上印刷不與天線圖案434電連接之EMI屏蔽層420。此外，EMI屏蔽層420可以電連接到接地電路圖案432。
如圖9C所示，閃光燈613可以燒結及/或固化經印刷的EMI屏蔽層420。特別地，閃光燈613可以包括氙燈和透過強脈衝光(intense pulsed light，IPL)對EMI屏蔽層420進行光燒結的反射器。在示例性實施例中，閃光燈613可以用約0.1μs至約100μs的脈衝光輻射EMI屏蔽層420。脈衝光可以燒結包含在導電油墨中的金屬顆粒或金屬氧化物顆粒以形成EMI屏蔽層420。
參考圖10A-10D，其說明了依序地圖示根據本發明的各種實施例的半導體裝置的製造方法的製程步驟的橫截面圖。參照半導體裝置500、圖5和圖10A-10D來描述所述製造方法。
如圖10A所示，第一囊封部分551可以囊封半導體晶粒110。進一步，印刷機612可以在第一囊封部分551的表面上印刷EMI屏蔽材料，以形成EMI屏蔽層520。特別地，第一囊封部分551的第一區域551a可以形成在半導體晶粒110的第一表面111上，第一囊封部分551的第二區域551b可以形成在半導體晶粒110的第三表面113上，並且具有預定厚度的EMI屏蔽層520可以印刷在第一囊封部分551的第一區域551a上，而不在第一囊封部分551的第二區域551b上形成EMI屏蔽層520。如圖所示，第一囊封部分551的第二區域551b可以插入在第一和第二半導體晶粒110之間。特別地，第一囊封部分551的第二區域551b可以被插入到第一和第 二半導體晶粒110的第三表面113之間的區域。
如圖10B所示，閃光燈613可以用輻射光對形成在第一區域551a上的EMI屏蔽層520進行光燒結。特別地，EMI屏蔽層520可以形成為液相或凝膠相。來自閃光燈613的輻射光可以將液相或凝膠相的EMI屏蔽層520轉換成在第一囊封部分551上剛性固化的固相。
如圖10C所示，切割工具608可以將第一半導體晶粒110與第二半導體晶粒110分離。特別地，這種分離可導致分離的EMI屏蔽層520和第一囊封部分551的第二區域551b是共平面的。
在這種分離之後，包括第一囊封部分551和EMI屏蔽層520的第一半導體晶粒110可以透過質量回焊或熱壓縮而電連接到基板130，如圖10D所示。線接合器611可以在第一囊封部分551附近形成複數個EMI屏蔽線570。特別地，線接合器611可以將EMI屏蔽線570的第一端接合到EMI屏蔽層520，且將EMI屏蔽線570的第二端接合到基板130的接地電路圖案332。
此後，第一囊封部分551、EMI屏蔽層520和EMI屏蔽線570可以被第二囊封部分552囊封，並且複數個外部互連結構160可形成在基板130的底表面上。如上所述，一些實施例可以省略第二囊封部分552。在這樣的實施例中，半導體裝置可以具有暴露的EMI屏蔽層520和EMI屏蔽線570來銷售。
儘管已經參照本發明的示例性實施例具體說明和描述了本發明的半導體裝置及其製造方法，但是所屬技術領域中具有通常知識者將會理解在不脫離由所附申請專利範圍限定的本發明的精神和範圍的情況下 可以進行形式和細節的各種改變。

Claims (20)

  1. 一種半導體裝置，包括：半導體晶粒，包括第一表面、與所述第一表面相對的第二表面、形成在所述第一表面和所述第二表面之間的第三表面以及形成在所述第二表面上的複數個互連結構；EMI屏蔽層，其包括屏蔽所述半導體晶粒的所述第一表面之第一導電層和屏蔽所述半導體晶粒的所述第三表面之第二導電層；基板，其電連接到所述半導體晶粒的所述複數個互連結構；以及囊封部分，其囊封所述EMI屏蔽層和所述基板。
  2. 根據請求項1所述的半導體裝置，進一步包括：另一半導體晶粒，其與所述半導體晶粒水平地間隔開；其中所述EMI屏蔽層的所述第二導電層介於所述半導體晶粒和所述另一半導體晶粒之間。
  3. 根據請求項1所述的半導體裝置，其中所述半導體晶粒包括：接觸墊，其電連接到所述複數個互連結構中的互連結構；以及接地電路圖案，其電連接所述接觸墊和所述EMI屏蔽層。
  4. 根據請求項1所述的半導體裝置，其中所述EMI屏蔽層包括選自導電聚合物、導電油墨、導電膏和導電箔的材料。
  5. 根據請求項1所述的半導體裝置，進一步包括填充所述半導體晶粒和所述基板之間的間隙的底部填充物。
  6. 根據請求項1所述的半導體裝置，其中所述EMI屏蔽層包括非濺射的EMI屏蔽層。
  7. 根據請求項1所述的半導體裝置，其中所述EMI屏蔽層包括銅箔。
  8. 根據請求項1所述的半導體裝置，其中所述EMI屏蔽層包括旋塗的EMI屏蔽層。
  9. 根據請求項1所述的半導體裝置，其中所述EMI屏蔽層包括噴射印刷的EMI屏蔽層。
  10. 一種半導體裝置，包括：半導體晶粒，其包括第一表面、與所述第一表面相對的第二表面、形成在所述第一表面和所述第二表面之間的第三表面以及形成在所述第二表面上的複數個互連結構；非濺射的EMI屏蔽層，其屏蔽所述半導體晶粒的所述第一表面；複數個EMI屏蔽線，其圍繞所述半導體晶粒的所述第三表面定位且電連接到所述非濺射的EMI屏蔽層；基板，其電連接到所述半導體晶粒的所述複數個互連結構；以及囊封部分，其囊封所述非濺射的EMI屏蔽層、所述EMI屏蔽線和所述基板。
  11. 根據請求項10所述的半導體裝置，其中所述非濺射的EMI屏蔽層包括選自導電聚合物、導電油墨、導電膏和導電箔的材料。
  12. 根據請求項10所述的半導體裝置，其中所述複數個EMI屏蔽線圍繞且感應地屏蔽所述半導體晶粒的所述第三表面。
  13. 根據請求項12所述的半導體裝置，其中所述複數個EMI屏蔽線與所述半導體晶粒的所述第三表面間隔開。
  14. 根據請求項10所述的半導體裝置，其中： 所述非濺射的EMI屏蔽層具有帶有四邊的矩形；以及所述複數個EMI屏蔽線沿著所述四邊配置。
  15. 一種半導體裝置，包括：半導體晶粒，其包括第一表面、與所述第一表面相對的第二表面、形成在所述第一表面和所述第二表面之間的第三表面以及形成在所述第二表面上的複數個互連結構；基板，其電連接到所述半導體晶粒的所述複數個互連結構；第一囊封部分，其包括圍繞所述半導體晶粒的所述第一表面之第一區域和圍繞所述半導體晶粒的所述第三表面之第二區域；以及EMI屏蔽層，其屏蔽所述第一囊封部分的所述第一區域和所述第二區域中的至少一個。
  16. 根據請求項15所述的半導體裝置，其中：所述EMI屏蔽層屏蔽所述第一囊封部分的所述第二區域；以及所述基板進一步包括透過所述第二區域暴露的天線圖案。
  17. 根據請求項15所述的半導體裝置，進一步包括囊封所述第一囊封部分、所述EMI屏蔽層和所述基板的第二囊封部分。
  18. 根據請求項17所述的半導體裝置，其中所述EMI屏蔽層屏蔽所述第一囊封部分的所述第一區域。
  19. 根據請求項15所述的半導體裝置，進一步包括圍繞所述半導體晶粒的所述第三表面定位且電連接到所述EMI屏蔽層的複數個EMI屏蔽線。
  20. 根據請求項15所述的半導體裝置，其中所述EMI屏蔽層包括非濺射的EMI屏蔽層。
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