CN1286803A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

Info

Publication number
CN1286803A
CN1286803A CN98813167A CN98813167A CN1286803A CN 1286803 A CN1286803 A CN 1286803A CN 98813167 A CN98813167 A CN 98813167A CN 98813167 A CN98813167 A CN 98813167A CN 1286803 A CN1286803 A CN 1286803A
Authority
CN
China
Prior art keywords
layer
embedding
semiconductor element
collector electrode
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN98813167A
Other languages
English (en)
Other versions
CN1132238C (zh
Inventor
A·瑟德贝里
H·舍丁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of CN1286803A publication Critical patent/CN1286803A/zh
Application granted granted Critical
Publication of CN1132238C publication Critical patent/CN1132238C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Abstract

包括埋置导电层(108)例如埋置集电极的半导体包括一个沟槽,沟槽壁上覆盖一层(109′),在层(109′)中掺杂剂的扩散比在单晶硅中快。在离沟槽壁(109′)很近的地方掺杂接触区。掺杂剂扩散穿过层(109′)形成到埋置层(108)的低阻连接。所述层(109′)包括多晶硅或多孔硅,或硅化物。如果层(109′)的材料自身不导电,元件的尺寸可以显著降低。

Description

半导体元件及其制造方法
本发明涉及半导体元件，特别涉及在包括埋置导电层的半导体元件中获得低电阻的方法，以及这种半导体元件。
绝缘体上硅(SOI)材料在制造半导体时提供许多优点，例如免受锁定、元件之间的电绝缘以及减少了寄生电容。目前最经常使用的SOI材料包括在例如二氧化硅等的绝缘层上的例如厚度在500和30μm之间的薄硅层。有源元件位于硅层内，借助沟槽相互隔离，沟槽一直腐蚀到埋置的氧化物并通常填充有氧化物和多晶硅(多晶硅)。经常，使用埋置的导电层，其与埋置的氧化物相邻设置。
所述导电层可以为例如双极元件中的集电极，或场效应元件中的漏极。为简化起见，在下面的讨论中，使用术语集电极，或埋置的集电极。此外使用术语集电极电阻用于说明从表面的接触到埋置导电层的电阻。
根据元件的类型，元件也包括其它的掺杂区域，例如双极元件中的基极和发射极、场效应元件中的栅极和源极，以及二极管中的阳极或阴极。
要减少成本，应减少元件的面积。此外元件的性能必须很好，例如集电极电阻应该低。如果沟槽壁掺杂，使用沟槽可以减小集电极电阻。所述掺杂区域环绕元件，并向下延伸到埋置的集电极。减小集电极电阻的另一方式是从靠近集电极接触的表面向下深扩散到埋置的集电极。埋置的集电极中的掺杂剂同时向上扩散。所述扩散必须使用较厚的硅层进行补偿。这就使制造工艺增加了一个额外的掩蔽步骤，并且很难借助沟槽得到绝缘。
要减少元件的面积，可以保持沟槽壁不掺杂。
相反掺杂类型的区域可以较靠近沟槽设置，形成例如基极、阳极或阴极。然而，由于增加了集电极电阻，造成元件性能降低。由此，功率晶体管必须制得很大。
本发明的一个目的是得到具有低集电极电阻的埋置集电极的半导体元件。
本发明的另一目的是得到较小的半导体元件。
根据本发明通过在半导体元件组成部分的器件层中或下面获得到埋置导电层的低阻连接的方法可以达到这些目的，所述方法包括以下步骤：
在器件层中腐蚀出至少一个沟槽，划分出有源元件区；
提供材料的沟槽壁层，其中掺杂剂在沟槽壁上的扩散比在设置有埋置层的物质中扩散的快；
如果与沟槽壁层直接连接的所述有源元件表面上的区域被掺杂，那么所述区域的掺杂剂将扩散穿过所述沟槽壁层，短路进入到器件层中形成到埋置层的接触。
沟槽壁层包括多晶硅或多孔硅、或金属硅化物。如果使用多晶硅或多孔硅，那么沟槽壁仅在掺杂的接触区域附近导电。因此沟槽的所有其它部分可以随意设置在元件的任何其它掺杂区域附近，甚至与它们相邻。
硅化物自身为导体；因此使用硅化物可以改善接触。另一方面，在元件的基极区域不能使用硅化物用为多晶硅或多孔硅。因此如果使用硅化物，与现有技术的元件相比，不能减小元件的尺寸。
本发明提供以下优点：
不使用额外的掩蔽步骤就可以获得具有低集电极电阻的半导体元件。
利用附近的吸杂中心，可以增加元件的成品率和可靠性。吸杂中心为能捕获使元件性能下降的金属杂质的区域。
与使用从上表面到埋置集电极的向下深扩散的常规技术相比，上硅层可以制得更薄。与常规技术相比，元件可以制得更小，例如沟槽壁的掺杂。
如果根据本发明的沟槽在较早的阶段形成，那么它将作为吸杂中心，吸收金属杂质。
图1为在SOI材料中制造的现有技术的双极晶体管的剖面图；
图2示出了从上向下看到的图1的元件。
图3A-3F为根据本发明的一个实施例在制造工艺中部分半导体的剖面图。
图4为由图3A-3F中画出的工艺得到的元件的一部分剖面图。
图5为从上向下看到的图4的双极晶体管。
图1为在SOI材料中制造的现有技术的双极晶体管的剖面图。在基片层1上，设置有如二氧化硅的绝缘层3。在绝缘层上，有一个硅层5，包括有源元件7a，7b，由横向绝缘各元件的沟槽9隔开。这里，仅考虑其中一个有源元件7a。埋置的集电极11位于硅层5中，与绝缘层3相邻。
发射极13位于有源元件7a的表面，以与现有技术中相同的方式由基极15环绕。集电极接触17位于有源元件7a的表面，靠近沟槽壁。沟槽壁的区域19已掺杂，形成了从集电极接触17到埋置集电极11的低阻连接。
通常由以下方式形成沟槽9：
以常规的方式将沟槽向下腐蚀到埋置的氧化物。然后以常规的方式掺杂沟槽壁，例如在炉中由气体源掺杂杂质或大角度注入。然后在沟槽中生长或淀积氧化层21，之后由多晶硅填充沟槽。由于沟槽壁19始终环绕元件7a掺杂，因此基极15和沟槽壁19之间的距离必须保持得很大，以防止在基极附近形成太强的电场，导致雪崩击穿。
图2示出了从上向下看到的图1的元件，其中相同的参考标号表示与图1中相同的元件。元件7a由沟槽9环绕。掺杂沟槽壁作为集电极接触17和埋置的集电极(未示出)之间的连接。可以看出，基极15和沟槽壁19必须在所有的方向中隔开基本相同的距离，如箭头23所示。
图3A到3F示出了与根据本发明制造低集电极连接，即制造图4中所示的元件相关的制造工艺的重要步骤。
图3A示出了包括基片层101、绝缘层103和硅层105的半导体元件，其中已使用常规的掩蔽和腐蚀技术形成了一个沟槽。元件包括带埋置导电层108的有源元件17。在该阶段之前，元件的表面可以由氧化物和/或氮化层(未示出)覆盖。
图3B示出了具有淀积在元件表面上的层109的相同半导体元件，包括沟槽的各壁和底部。层109包括其中掺杂离子比在单晶硅中扩散显著快得多的材料，例如多晶硅、多孔硅或硅化物。当层109为硅化物时，首先将金属施加到元件上，包括沟槽的各壁和底部。在随后的热处理期间，在沟槽中硅-金属界面形成硅化物，通过选择性腐蚀金属不腐蚀硅化物除去其余的金属。
图3C示出了从元件的顶部和沟槽的底部深腐蚀了层109留下了覆盖沟槽壁的材料层109’之后的相同的半导体元件。不必从沟槽的底部除去层109，但由于使用各向异性反应离子腐蚀的实际原因，通常这样做。
图3D示出了在元件的整个表面上已生长或淀积了氧化物的层111之后相同的半导体元件。代替氧化物，可以淀积氮化硅或其它的绝缘材料。
在图3E中，用如多晶硅等的适当材料填充元件的沟槽，通过掩蔽和掺杂步骤，以与现有技术中相同的方式形成发射极113和基极115。
在图3F中，以与现有技术中相同的方式通过掩蔽和掺杂步骤形成集电极接触117。集电极接触117接触覆盖沟槽壁的部分层109’(该部分109a显示在图5中)。
然后以与现有技术中相同的方式对元件进行退火工艺。进行退火工艺直到掺杂剂达到埋置的集电极。然而，掺杂剂不允许扩散到增加掺杂区域雪崩击穿危险的程度。其中，退火时间和温度取决于沟槽的深度。典型的值为1-10小时，温度约800-1250℃。
由于多晶硅、多孔硅和硅化物中掺杂剂的扩散速度比单晶硅中高得多，来自集电极接触117的扩散剂将扩散穿过层109a(见图5)向下到埋置的集电极108，也轻微地扩散到相邻的有源元件的硅内，并形成从集电极接触到埋置的集电极108的低阻连接。
硅化物自身为导体。因此，使用硅化物比使用多晶硅或多孔硅将使集电极电阻减少得更多。另一方面，如果沟槽壁包括导体，那么沟槽壁和基极之间的距离将增加。如果使用多晶硅或多孔硅，那么沟槽壁仅在集电极接触的周围导电，所以只有那部分沟槽要远离基极，如图5所示。
图4为图3F中所示元件的部分剖面图，示出了掺杂剂离子从集电极接触117向下扩散到埋置的集电极108。可以看出，扩散剂从集电极接触117穿过层109’向下扩散到埋置的集电极108，也扩散到有源元件107的硅内较短的距离。层109’和掺杂剂扩散到其内的有源元件107的区域一起形成从集电极接触117到集电极108的低阻连接。
可以在半导体的制造工艺的任何点进行沟槽形成工序，即在形成有源元件之前或之后。如果在较早的阶段形成沟槽，在形成任何元件之前，那么它将作为吸杂中心，捕获在工艺中引入的任何金属杂质。即使在较后的阶段形成，根据本发明的沟槽仍可以用于减少漏电流，但不能吸收杂质，或在一定程度上恢复如发射极短路等的损伤，如果存在的话，同时形成有源部件。
图5示出了从上向下看到的图3F的有源部件，假设在层109’中使用的材料自身不导电。此时，由于掺杂剂由接触117的扩散，仅有层109的一部分109a和该部分109a附近中有源元件的区域导电。可以看出，除了集电极接触117所处的侧面109a之外，基极115非常靠近所有侧面上的沟槽壁109’。如果需要，沟槽壁可以设置在距基极小于1μm的距离处，或甚至与基极115相邻。这可以使元件显著小于图2中所示的现有技术的元件。
如上所述，本发明不仅适用于包括埋置集电极的晶体管，而且当需要到埋置导电层的低阻接触时，本发明同样适用于包括埋置导电层的其它半导体，例如二极管、晶闸管、MOS或DMOS晶体管或IGBT。

Claims (24)

1．一种在组成半导体元件一部分的器件层(105)中或下面获得到埋置导电层(108)的低阻连接的方法，所述方法包括以下步骤：
在器件层(105)中腐蚀出至少一个沟槽，划分出有源元件区(107)；
沟槽壁层上提供材料层(109′)，其中掺杂剂在层(109′)中的扩散比在设置有埋置层的物质中的扩散快；
掺杂与层(109’)直接接触的所述有源元件(107)的区域，形成接触(117)；
退火元件，直到掺杂剂向下扩散到埋置的导体(108)。
2．根据权利要求1的方法，其中退火元件直到掺杂剂向下扩散到埋置的导体(108)，但距离其它的掺杂区域(115)仍足够远，以避免降低击穿电压。
3．根据权利要求1或2的方法，特征在于以下步骤：
在沟槽中层(109)上淀积或生长氧化物和/或氮化硅层(111’)。
4．根据以上任何一个权利要求的方法，特征在于与接触(117)相邻的那部分沟槽壁(109a)位于比沟槽壁的其余部分离掺杂的区域(115)更远的位置。
5．根据权利要求4的方法，特征在于与接触(117)相邻的那部分沟槽壁(109a)位于比沟槽壁的其余部分离掺杂的区域(115)远至少两倍的距离。
6．根据权利要求4的方法，特征在于不与接触(117)相邻的那部分沟槽壁距离掺杂区域(115)小于1μm。
7．根据以上任何一个权利要求的方法，特征在于在层(109’)中使用多晶硅或多孔硅。
8．根据以上任何一个权利要求的方法，特征在于在层(109’)中使用硅化物。
9．根据权利要求以上的任何一个的方法，特征在于器件层(105)包括单晶硅。
10．根据权利要求10的方法，特征在于在器件层(105)位于绝缘层(103)上。
11．根据以上任何一个权利要求的方法，特征在于埋置导体(108)包括硅化物。
12．一种半导体元件，包括器件层(105)，其中设置有至少一个有源元件(107)，由沟槽横向地划分出，并具有一个埋置的导电层(108)，在所述沟槽的壁上有一层(109’)，在所述层(109’)的材料中掺杂剂的扩散快于在设置有埋置层的器件层的物质中的扩散，所述元件的特征在于掺杂所述层(109’)的至少一部分，而所述层的至少一部分基本上未掺杂。
13．根据权利要求12的半导体元件，特征在于在有源元件(107)的表面上有一个到埋置导电层的接触(117)，直接接触层(109’)的掺杂部分。
14．根据权利要求12或13的半导体元件，特征在于接触(117)的掺杂剂穿过层(109’)扩散到埋置导体(108)，由此形成了从接触(117)到埋置导体(108)的低阻连接。
15．一种半导体元件，包括器件层(105)，其中设置有至少一个有源元件(7a)，所述元件(7a)由沟槽横向地划分出，并具有至少一个掺杂区(115)和员工埋置导体(108)，特征在于
在所述沟槽的壁上有一层(109’)，在所述层(109’)的材料中掺杂剂的扩散快于在设置有埋置集电极(108)的物质中的扩散，
在有源元件表面上的接触(117)，其与层(109′)的一部分直接接触，
层(109′)的所述部分包括与集电极接触(117)中相同的掺杂剂，形成从集电极接触(117)到埋置集电极(108)的低阻连接，而层(109′)的至少一个其他部分基本不掺杂。
16．一种半导体元件，包括器件层(105)，其中设置有至少一个有源元件(7a)，所述元件(7a)由沟槽横向地划分出，并具有基极(115)、发射极(113)和埋置集电极(108)，特征在于
在所述沟槽的壁上有一层(109’)，在所述层(109’)的材料中掺杂剂的扩散快于在设置有埋置集电极(108)的物质中的扩散，
在有源元件表面上的接触(117)，其与层(109′)直接接触，
层(109′)的至少一部分包括与集电极接触(117)中相同的掺杂剂，形成从集电极接触(117)到埋置集电极(108)的低阻连接，而层(109′)的至少一个其他部分基本不掺杂。
17．根据权利要求12-16中任一个的半导体元件，特征在于所述层(109′)包括多晶硅或多孔硅。
18．根据权利要求12-16中任一个的半导体元件，特征在于所述层(109′)包括硅化物。
19．根据权利要求12-18中任一个的半导体元件，特征在于所述包括有源元件(107)的器件层(105)是位于衬底(101)上的硅层，其间设置有绝缘层(103)。
20．根据权利要求12-19中任一个的半导体元件，特征在于邻接接触(117)的沟槽壁部分(109a)比沟槽壁的其他部分距离掺杂区(115)较远。
21．根据权利要求20的半导体元件，特征在于邻接接触(117)的沟槽壁部分(109a)比沟槽壁的其他部分距离掺杂区(115)远至少两倍。
22．根据权利要求20的半导体元件，特征在于不邻接接触(117)的沟槽壁部分距离掺杂区(115)小于1微米。
23．根据权利要求12-22中任一个的半导体元件，特征在于所述层(109′)包括多晶硅或多孔硅。
24．根据权利要求12-23中任一个的方法，特征在于所述层(109′)包括硅化物。
CN988131676A 1997-11-17 1998-11-16 半导体元件及其制造方法 Expired - Fee Related CN1132238C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9704211A SE513471C2 (sv) 1997-11-17 1997-11-17 Halvledarkomponent och tillverkningsförfarande för halvledarkomponent
SE97042113 1997-11-17

Publications (2)

Publication Number Publication Date
CN1286803A true CN1286803A (zh) 2001-03-07
CN1132238C CN1132238C (zh) 2003-12-24

Family

ID=20409015

Family Applications (1)

Application Number Title Priority Date Filing Date
CN988131676A Expired - Fee Related CN1132238C (zh) 1997-11-17 1998-11-16 半导体元件及其制造方法

Country Status (11)

Country Link
US (1) US6326292B1 (zh)
EP (1) EP1040517B1 (zh)
JP (1) JP2001523893A (zh)
KR (1) KR100584969B1 (zh)
CN (1) CN1132238C (zh)
AU (1) AU1183999A (zh)
CA (1) CA2310280A1 (zh)
DE (1) DE69838683D1 (zh)
SE (1) SE513471C2 (zh)
TW (1) TW385526B (zh)
WO (1) WO1999026293A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102210019A (zh) * 2008-11-12 2011-10-05 国际商业机器公司 用于掩埋的导电层的硅化沟槽接触
CN103022088A (zh) * 2011-09-21 2013-04-03 株式会社东芝 具有沟道结构体的半导体装置及其制造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020140030A1 (en) * 2001-03-30 2002-10-03 Mandelman Jack A. SOI devices with integrated gettering structure
US6830986B2 (en) * 2002-01-24 2004-12-14 Matsushita Electric Industrial Co., Ltd. SOI semiconductor device having gettering layer and method for producing the same
EP1353368A1 (en) * 2002-04-11 2003-10-15 AMI Semiconductor Belgium BVBA Semiconductor structure and method for manufacturing the same
JP4020195B2 (ja) * 2002-12-19 2007-12-12 三菱電機株式会社 誘電体分離型半導体装置の製造方法
ITTO20050056A1 (it) * 2005-02-03 2006-08-04 St Microelectronics Srl Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'
US20080121985A1 (en) * 2006-11-07 2008-05-29 International Business Machines Corporation Structure and method to improve short channel effects in metal oxide semiconductor field effect transistors
US7679164B2 (en) * 2007-01-05 2010-03-16 International Business Machines Corporation Bipolar transistor with silicided sub-collector
DE102008046388A1 (de) * 2008-09-09 2010-03-18 Infineon Technologies Ag Vertikaler Bipolartransistor
DE102012003748B4 (de) * 2011-03-01 2016-12-15 Infineon Technologies Austria Ag Verfahren zum Herstellen eines porösen Halbleiterkörpergebiets und zum Einbringen eines Fremdstoffes
CN105977333B (zh) * 2016-07-12 2017-11-14 李会欣 光伏电池组件及光伏发电系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61191043A (ja) 1985-02-20 1986-08-25 Toshiba Corp 半導体装置
US4704368A (en) * 1985-10-30 1987-11-03 International Business Machines Corporation Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor
US5057443A (en) 1988-06-29 1991-10-15 Texas Instruments Incorporated Method for fabricating a trench bipolar transistor
US4965217A (en) 1989-04-13 1990-10-23 International Business Machines Corporation Method of making a lateral transistor
US5109263A (en) * 1989-07-28 1992-04-28 Hitachi, Ltd. Semiconductor device with optimal distance between emitter and trench isolation
US5278438A (en) 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
US5283454A (en) * 1992-09-11 1994-02-01 Motorola, Inc. Semiconductor device including very low sheet resistivity buried layer
US5358884A (en) * 1992-09-11 1994-10-25 Micron Technology, Inc. Dual purpose collector contact and isolation scheme for advanced bicmos processes
US5478758A (en) * 1994-06-03 1995-12-26 At&T Corp. Method of making a getterer for multi-layer wafers
US5643821A (en) * 1994-11-09 1997-07-01 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
JP2708027B2 (ja) 1995-10-05 1998-02-04 日本電気株式会社 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102210019A (zh) * 2008-11-12 2011-10-05 国际商业机器公司 用于掩埋的导电层的硅化沟槽接触
CN102210019B (zh) * 2008-11-12 2013-11-27 国际商业机器公司 用于掩埋的导电层的硅化沟槽接触
US8872281B2 (en) 2008-11-12 2014-10-28 International Business Machines Corporation Silicided trench contact to buried conductive layer
CN103022088A (zh) * 2011-09-21 2013-04-03 株式会社东芝 具有沟道结构体的半导体装置及其制造方法

Also Published As

Publication number Publication date
WO1999026293A2 (en) 1999-05-27
TW385526B (en) 2000-03-21
CA2310280A1 (en) 1999-05-27
DE69838683D1 (de) 2007-12-20
WO1999026293A3 (en) 1999-07-15
SE9704211L (sv) 1999-05-18
CN1132238C (zh) 2003-12-24
SE9704211D0 (sv) 1997-11-17
US6326292B1 (en) 2001-12-04
KR20010032149A (ko) 2001-04-16
JP2001523893A (ja) 2001-11-27
KR100584969B1 (ko) 2006-05-29
SE513471C2 (sv) 2000-09-18
AU1183999A (en) 1999-06-07
EP1040517A2 (en) 2000-10-04
EP1040517B1 (en) 2007-11-07

Similar Documents

Publication Publication Date Title
US6144065A (en) MOS gated device with self aligned cells
CN100474616C (zh) 具有增加的导通电阻的沟槽mosfet器件
US4682405A (en) Methods for forming lateral and vertical DMOS transistors
US7015125B2 (en) Trench MOSFET device with polycrystalline silicon source contact structure
KR19990022910A (ko) 반도체장치의 제작
CN1152419C (zh) 功率半导体器件及其制造方法
CN1132238C (zh) 半导体元件及其制造方法
CN101043053A (zh) 具有改善性能的功率半导体器件和方法
CN1539169A (zh) 对称沟槽mosfet器件及其制造方法
CN1094654C (zh) 隔离栅半导体器件及其制造方法
CN1463034A (zh) 半导体结构和处理这种结构的方法
CN101211978A (zh) 半导体装置
CN1274028C (zh) 具有减小导通电阻的双扩散场效应晶体管
US4625388A (en) Method of fabricating mesa MOSFET using overhang mask and resulting structure
KR100948663B1 (ko) 복수의 트렌치 ｍｏｓｆｅｔ 셀들을 포함하는 디바이스를 형성하는 방법, 및 얕은 및 깊은 도펀트 주입물 형성 방법
CN1190832C (zh) 半导体结构
JP2006140239A (ja) 半導体装置及びその製造方法
CN113937167A (zh) Vdmos器件及其制造方法
US7105410B2 (en) Contact process and structure for a semiconductor device
CN101136436A (zh) 半导体器件及其制造方法
CN1519953A (zh) 半导体器件及其制造方法
CN102956479B (zh) 绝缘栅双极晶体管结构及其制作方法
KR20000050396A (ko) 트렌치 게이트형 전력 반도체 소자 및 그 제조방법
KR0183669B1 (ko) 고전압용 반도체소자 및 그 제조방법
CN113948573A (zh) 高压半导体器件及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: INFINEON TECHNOLOGIES AG

Free format text: FORMER OWNER: ELLISON TELEPHONE CO., LTD.

Effective date: 20040827

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20040827

Address after: Munich, Germany

Patentee after: Infennian Technologies AG

Address before: Stockholm

Patentee before: Ericsson Telephone AB

REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1035437

Country of ref document: HK

C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee