ITTO20050056A1 - Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita' - Google Patents

Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'

Info

Publication number
ITTO20050056A1
ITTO20050056A1 IT000056A ITTO20050056A ITTO20050056A1 IT TO20050056 A1 ITTO20050056 A1 IT TO20050056A1 IT 000056 A IT000056 A IT 000056A IT TO20050056 A ITTO20050056 A IT TO20050056A IT TO20050056 A1 ITTO20050056 A1 IT TO20050056A1
Authority
IT
Italy
Prior art keywords
segregation
impurities
manufacturing
increased capacity
soi slice
Prior art date
Application number
IT000056A
Other languages
English (en)
Inventor
Roberto Campedelli
Turi Luigi Di
Dino Faralli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000056A priority Critical patent/ITTO20050056A1/it
Priority to US11/347,801 priority patent/US20060194409A1/en
Publication of ITTO20050056A1 publication Critical patent/ITTO20050056A1/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
IT000056A 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita' ITTO20050056A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000056A ITTO20050056A1 (it) 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'
US11/347,801 US20060194409A1 (en) 2005-02-03 2006-02-03 Process for manufacturing a SOI wafer with improved gettering capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000056A ITTO20050056A1 (it) 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'

Publications (1)

Publication Number Publication Date
ITTO20050056A1 true ITTO20050056A1 (it) 2006-08-04

Family

ID=36932450

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000056A ITTO20050056A1 (it) 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'

Country Status (2)

Country Link
US (1) US20060194409A1 (it)
IT (1) ITTO20050056A1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130104728A (ko) * 2012-03-15 2013-09-25 에스케이하이닉스 주식회사 반도체 칩 및 이를 갖는 적층 반도체 패키지
US9231020B2 (en) 2014-01-16 2016-01-05 Tower Semiconductor Ltd. Device and method of gettering on silicon on insulator (SOI) substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106776A (en) * 1988-06-01 1992-04-21 Texas Instruments Incorporated Method of making high performance composed pillar dRAM cell
EP0631306B1 (de) * 1993-06-23 2000-04-26 Siemens Aktiengesellschaft Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
US5478758A (en) * 1994-06-03 1995-12-26 At&T Corp. Method of making a getterer for multi-layer wafers
JPH09172061A (ja) * 1995-12-18 1997-06-30 Fuji Electric Co Ltd 半導体装置の製造方法
SE513471C2 (sv) * 1997-11-17 2000-09-18 Ericsson Telefon Ab L M Halvledarkomponent och tillverkningsförfarande för halvledarkomponent
US5929508A (en) * 1998-05-21 1999-07-27 Harris Corp Defect gettering by induced stress

Also Published As

Publication number Publication date
US20060194409A1 (en) 2006-08-31

Similar Documents

Publication Publication Date Title
ATE518856T1 (de) Herstellverfahren
ITTO20050209A1 (it) Macchina percolatrice per la preparazione di una bevanda
ITTO20050815A1 (it) Macchina mantecatrice per la produzione di gelato ed affini
ITBO20050696A1 (it) Macchina per la produzione di filtri composti
ITMI20062176A1 (it) Dispositivo semiconduttore avente una regione di separazione
FR2887543B1 (fr) Composition du rdx et procede pour sa fabrication
ITTO20060245A1 (it) Procedimento per la fabbricazione di una biella
GB2422378B (en) Fabrication of nanowires
ITTO20050056A1 (it) Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'
EP1946163A4 (en) MANUFACTURE OF NANOWIL
DE602004003638D1 (de) Konfokales Mikroskop
ITMI20040620A1 (it) Metodo e dispositivo per ispezionare l'interno di una calzatura
DE502004003890D1 (de) Kontaktherstellungsverfahren
ITMI20050981A1 (it) "struttura ottimizzata di mux/demux ottico"
ITRE20030086A1 (it) Metodo per la fabbricazione di manufatti con proprieta'
FI20030945A (fi) Sähkömekaaninen muuttaja ja valmistusmenetelmä
ITMI20040452A1 (it) Processo per la preparazione di oxcarbazepina
ITUD20060247A1 (it) Procedimento per la produzione di una cerniera per occhiali e cerniera per occhiali cosi' realizzata
DE112004000646D2 (de) SOI Kontaktstruktur(en) und zugehöriges Herstellungsverfahren
ITMI20052419A1 (it) Processo per la preparazione di carbotioati androstanici
ITMI20051395A1 (it) Processo continuo per la preparazione di 5-cloropentan-2-one
ITVR20050036A1 (it) Procedimento per la produzione di una struttura di serramento
ITVR20040093A1 (it) Procedimento per la produzione di una struttura di cassonetto o simili
ITPC20050059A1 (it) Macchina per la produzione di gnocchetti di pasta e in particolare di trofie
ITMI20040003A1 (it) Processo per la preparazione di 6-fluoro-2-metil-1-indanone