TW385526B - Semiconductor component and manufacturing method for semiconductor component - Google Patents
Semiconductor component and manufacturing method for semiconductor component Download PDFInfo
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- TW385526B TW385526B TW087100712A TW87100712A TW385526B TW 385526 B TW385526 B TW 385526B TW 087100712 A TW087100712 A TW 087100712A TW 87100712 A TW87100712 A TW 87100712A TW 385526 B TW385526 B TW 385526B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000002019 doping agent Substances 0.000 claims abstract description 21
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000002079 cooperative effect Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012634 fragment Substances 0.000 claims description 3
- 239000004575 stone Substances 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 2
- 239000013589 supplement Substances 0.000 claims 2
- 238000009434 installation Methods 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- 239000012535 impurity Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- WKBPZYKAUNRMKP-UHFFFAOYSA-N 1-[2-(2,4-dichlorophenyl)pentyl]1,2,4-triazole Chemical compound C=1C=C(Cl)C=C(Cl)C=1C(CCC)CN1C=NC=N1 WKBPZYKAUNRMKP-UHFFFAOYSA-N 0.000 description 1
- 108091005960 Citrine Proteins 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011035 citrine Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052701 rubidium Inorganic materials 0.000 description 1
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011031 topaz Substances 0.000 description 1
- 229910052853 topaz Inorganic materials 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明( 技術領域 本發明是有關於半導體组件,特別是有關於在—包括有 -掩埋導電層之半導體組件中完成一低電阻,及此半導於 組件。 發明背景 當製造半導體時,SO·質提供—些優點,例如:問鎖 免疫、組件間的電流絕緣、及降低寄生電容。現今經常被 使用之S〇I物質包括一薄矽層,例如:5〇〇埃,微米間的厚 度,而此一薄矽層是在絕緣層之頂部,如:二氧化矽。主 動组件是位於上述珍層中,且彼此藉由溝槽而隔離,上述 溝槽由蚀刻掩埋氧化物所形成,而溝槽中充填有氧 複晶梦。經常使用-掩埋導電層,而此掩埋導電層是鄰近 於上述掩埋氧化物。 例如:此一導電層可以是在雙極紐件中的集極,或者在 場效组件中的没極。A 了下面討論方便起見,會使用術語 集極或掩埋集極。. 也會使用術語集極電阻來描述自表面上之—接觸到上述 掩埋導電層之電阻。 依組件形態而定,組件也包括其他摻植區域,如:在雙 極组件中之-基極及—射極,在—場效組件中之—閉極Z 一源極,以及在一二極體中之一陽極或陰,極。 爲使成本爲最小,應使組件之面積爲最小。同時組件之 表現也要好,如同集極電阻應該要小一樣。如果,對溝槽 之邊牆實施掺植,則溝槽之使用能使集極電阻爲最小。上 _私衣------_、訂--- (請先聞讀背面之注意事項再#寫本頁) κ 1 n -- n In u —i n -4 -
A7 B7 五、發明説明( 述摻植區域環繞組件周图, 圍且向下延伸至掩埋集極。使隹 極電阻爲最小之另一替代方法爲實施自靠近集極接觸之: 面’向下至掩埋集極的深擴散。同時在上述掩埋集極中的 摻雖劑會向上擴散。而此擴散必須藉由使用一較厚矽層來 補償。此對於製程會增加_額外面.罩步驟,而且藉由溝槽 來獲得絕緣變得較困難。 ^ 爲了減少組件之面積,可不對溝槽邊牆實施摻植。 —相反摻植形態之面積可放置在靠近溝槽的位置,以形 成如-基極、-陽極或—陰極。但是,此一增加之集極電 極方面會導致組件表現變差。結果,特別是功率電晶體要 做得非常大。 發明综述 本發明又目的是要獲得一具有低集極電阻之掩埋集極的 半導體組件。 本發明之另一目的是要獲得一小半導體组件。 依據本發明藉由完成連接在一裝置層中或下之一掩埋導 電層的低電阻來達成上述目的,其中上述裝置層構成—半 導體组件之一部分,其包括下列步驟: -~於上述裝置層中蝕刻至少一溝槽,並且界定一主動組 件之區域; -在上述溝槽之邊牆上塗抹一溝槽邊牆'層,其中在上述 溝槽邊牆層之掺雜劑擴散速度比在基底中快,此外掩埋層 疋位於上述基中; 如果對直接與溝槽邊牆層連接之上述成份表面上的面積 -5- 本紙張尺度適用中国國家揉準(CNS ) Α4規格(210Χ297公釐) 裂__ (許先閲讀背面之注意事項再jl寫本頁) -、?τ 經濟部中央標隼局員工消費合作社印製 五、發明説明( A7 B7 實施摻植,則此面積之松%滅丨 一 <摻雖劑將經由上述溝槽邊牆層擴散 ’且以缸路牷進入裳置a,α你π -丄、 衣匕層以便形成至上述掩埋層之接 觸0 經濟部中央標準局員工消費合作社印製 上述溝槽邊牆層可包括赖El & , I括稷阳矽或多孔矽,或者金屬金屬 矽化物。如果使用複晶矽或容 、.、 阳夕孔矽,則溝槽逢牆將只在上 述所接植之接觸區域之附近壤泰 „ 附迓導%。因此上述溝槽邊牆之所 有其他部分可被放置靠 非近,.且件(任何其他已摻植區域,且 甚至可與其相鄰。 金屬金屬秒化物本身爲填轉 牙馬等姐。因此,使用金屬金屬矽化 物可導致接觸之改善。另外— 另外万面,不能使上述金屬金屬 石夕化物像複晶K多切-樣靠近組件之基極面積。因此 ’如果使用金屬金屬矽化物,則與昔知技術比較的話,將 無法減少组件之大小。 本發明提供下列之優點: 可完成具有低集極電阻之半導體組件,而不需要额外之 面罩步骤。 運用吸氣中心,以增加組件之產能及信賴度。吸氣中心 局可捕捉金屬雜質的面積,而此雜質會降低组件之表現。 所製U之上矽層可比使用具有一從頂部表面下至掩埋集 極I木擴散的傳統技術的要薄。而所製造之組件比使用傳 統技術(如:溝槽邊牆的摻植)要小。< 若孩根據本發明之溝槽係在較早之階段形成,其將作用 爲一吸附中心,吸附金屬雜質。 圖式之簡單説明 __. ** 6 - 本纸張尺度適用準( 裝-- (請先閱讀背面之注意事項再每寫本頁) --° --線-- I. I I I m .f-I -1- -1 · A7 五 發明説明( 經濟部中央標準局員工消費合作社印製 圖1係顯不出依據昔知接 夜術心製造於S0][物質中之 晶體的剖面圖; < 又極電 圖2係顯示出圖1之組件的了員視圖; 圖3A-3F係顯示出依據本發明者 面圖; 發明只施例义半導體的部分剖 圖4係顯不出依圖3 a q Έ? »+*、 分剖面圖; ·中所述之製程所獲得之㈣的部 圖5係顯tf出圖4之榧紅^ 心又極電晶體的頂視圖。 實施例 圖1係顯示出依據普知 曰知技術之製造於SOI物質中之雜拓哈 晶體的剖面圖。在—甚Λ a 貝τ <又極電 於“展層1上具有-絕緣層3,例如: —虱化矽。在上述絕緣層 ir_D上具有—矽層5,而此 括由溝槽9所隔離的主動 匕 間㈣…多 L 7b,而此溝槽9提供組件 間的杈向絕緣。在這裏,σ 衣 /、考慮王動組件7a。而一捺埋隹 極11是位於矽層5中,B * 衔埋木 十且鄰近於此絕緣層3。 與昔知方式一搏,__虹』 —射極13位於主動组件7a之表面,且 Π15所環繞。-集極接觸17是位於主動組件7a之表 且非近於溝槽邊牆。上述溝槽邊牆之區域19已被摻 …便提供—從集極接觸口連接到掩壤集極Η的低電 阻0 上述溝槽9疋依據下列方法所形成的:< 專、充方法任下餘刻掩埋氧化物以形成溝槽。然後,以 傳統方法對此溝槽邊 这牆只施佈植,例如:使用來自在一爐 中之氣體源的換枯,斗、土、,一 ^ ^ 或者以向角度佈植。然後,在此溝槽 本紙張尺度 (請先閱讀背面之注意事項再填寫本頁) 裝.
、1T 線-----------;__ (210X297公釐) 五、發明説明( A? B7 中成長或沈積一氧化物層21,再以複晶矽充填此溝槽。因 爲在組件7a周圍之溝槽邊牆19已被摻植,所以要將上述基 極15與溝槽邊牆19間之距離保持大些,以防止在靠近基極 地方形成會導致突崩潰(avalanche breakd〇wn)之太強的電 場。 圖2係顯示出圖1之組件以的頂視圖,其中使用相同的數 字符號來表示如圖1所示之相同的組件。组件7a被溝槽9所 %繞。摻植溝槽邊牆以做爲集極接觸17及掩埋集極(未顯 示於圖中)之間的連接器。基極15及溝槽邊牆19必須在所 有万向(如箭頭23所示)以相同距離彼此保持分離。 圖3A-3F係顯示出有關於依據产發明之低集極電阻連接 之製程的重 圖3 A顯示 卜--------¾|_: (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作社印掣 要步驟,亦即,製造 出一包括有一基底層1〇1、一絕緣層1〇3及一矽 層105的半球體組件,其中一溝]f已以傳統面罩及蝕刻技 術形成於上述矽層105中。上述組件包括一具有一掩埋導 電層108之主動組件1〇7。在此階段之前,组件之表面可用 一氧化物及/或氮化物層(未顯示於圖中)來覆蓋。 圖3B顯示出具有沈積於上述組件表面之—層1〇9之相同 半導體組件,包括形成於溝槽之邊牆及底部。 上述層109包括一物質,摻雜劑在此物質之擴散速度比 在單結晶矽(如:複晶矽、多孔矽或金屬矽化物)要快。在 該層1〇9爲金屬矽化物之情況中.,首先,塗袜一金屬於此 、..件上包括塗抹於溝槽之邊牆與底部。在随後之熱處理 中,在溝槽中之矽_金屬界面上形成金屬矽化物。然後, 如圖4所示之組件
、1T A7 ~~~--~____ Β7 五、發明説明(6 ) 經濟部中央標準局負工消費合作社印製 藉由選擇性蚀刻上述金屬,以去除所剩餘之金屬。 圖職示出在對該層職組件之頂部及溝槽之底部實 施回钱刻,以留下靂苫、、婆搞、 義溝槽邊牆疋—層109丨後之相同半導 體組件。溝槽底部之層 層1〇9並/又有必要去除,但是當使用 非等向離子餘刻時,甚认承敗L 基於貝際上的理由通常會將其去除。 圖3D顯示出在組件之整個 、 面上成長或沈積一氧化物層 111後之相同半導辦知/土 ,ι al 千導版...且件。此外,可以沈積氮化矽或其他 絕緣物質來替代上述氧化物。 在圖财,以昔知技術,利用適當物質(如:複晶靖 无填上述组件之溝槽,以及藉由面罩及接植步驟來形成一 射極113及一基極115。 在圖3F中,以昔知技術,藉由面罩及摻植步驟形成集極 接觸117。上述集極接觸117與覆蓋於溝槽邊牆上之層· 的一部分接觸(此部份如圖5之1〇^所示)。 然後’以昔知方法對此组件實施退火處理,直到捧雜劑 到達上述掩埋集極爲止。但是,此轉劑不可擴散太遠, 進而增加對已摻植區域之突崩潰—姐咖^似。·)的危 險:退火時間及溫度是決定於溝槽的深度。通常,在溫度 約爲800-125(TC之退火時間爲卜1〇小時。 因爲在複晶碎、多切及金屬碎化物中之接雜劑的擴散 速度比在單結晶石夕中快很多,所以來自集極接觸117的摻 雜㈣會經由層109a (參考圖5)往下擴散至掩埋集極,也 會稍微擴散進入上述主動組件之鄰近石夕,以便從集極接觸 連接到掩埋集極108以形成一低電阻。 .-9- 本紙張尺度適用中國國士標準(CNS ) l·--------dI-. (锖先閱讀背面之注意事項再试‘寫本頁) ,1r
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• - -- - -- - I 、發明説明(7 孟屬石夕化物本身爲導電體。 用複晶矽或多孔矽更能減少集 因此,使用金屬石夕化物比使 極電阻。另外一方面,如果 經濟部中央標準局員工消費合作社印製 溝槽邊牆包括一導電體, v 』必項增加溝槽邊牆及基極間的 距離。如果使用複晶矽 隹i 4 ^孔石夕,則溝槽邊牆將只在上述 术極接觸之附近導電,.以致 (如圖5所示) 圖4係顯示出圖.3F中泛知! 、 T ,.且件的郅分剖面圖,以描述摻雜 劑從集極接觸117下至掩埋集極1〇8之擴散。如户斤見,捧雜 劑從集極接觸騰由層游往下擴散至掩埋集極1〇8,同 時也會短距離進入到主動組件1〇7摻雜劑所擴散進去的上 迟層109及主動組件1〇7之面積一起形成從集極接觸117連 接至集極1〇8的一低電阻。 在半導體製程中之任何時間可實施溝槽形成之程序,亦 即在主動组件形成之前或之後。如果依據本發明之溝槽是 在較早階段形成(在任何組件形成之前),則此溝槽也可做 爲一吸氣中心,以捕捉任何引進製程中之金屬雜質。縱使 是在較晚階段形成,則依據本發明之溝槽仍可用來降低漏 電電流,但是無法吸引雜質,或復原損害(如射極短路)至 宛如當主動組件正在形成時其出現之相同的程度。 圖5係顯示出圖3F之主動組件的頂視圖,假設使用在層 109'中之物質本身無法導電。在此情況中(,因爲摻雜劑從 接觸117擴散,所以在此部分109a附近只有此層109,之一部 分109a及主動组件之.一區域是導電的。如所見,基極115可 以非常靠近溝槽邊牆109'之所有邊’除了邊l〇9a之外,其 此爲唯一部分必須遠離基極 -10- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) •裝. 訂 A 7 B7 ' 五、發明説明(8 ) 中集極接觸117是位於此邊109a上。如果要的話,溝槽邊牆 可放置於離基極少於1微米的距離,或者甚至相鄰於基極 115。如此可使組件遠小於如圖2所示之昔知組件。 如以上所述,當一低電阻接觸到掩埋導電層時,本發明 不僅可應用於包括有一掩埋集極的電晶體,而且可應用於 包括有一掩埋導電層之其他半導體,如:二極體、閘流體 (thyristors)、MOS或 DMOS 電晶體或 IGBTs。 L---------批衣--^-----——ΐτ------.^ # (請先閲讀背面之注意事項再螇寫本頁) 經濟部中央標準局員工消費合作社印製 -11- 本纸張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐)
Claims (1)
- A8 B8 时年ί。月丨I日1丨夕 C8 D8 ^ 補充 丨丨 1 .... 第8710〇712號專利申請案 申請專利範圍修正本(88年10月) 六、申請專利範圍 1. 一種達成接觸到一裝置層(105)中或下之一掩埋導電層 (108)之低電阻的方法,該裝置層(1〇5)構成一半導體組 件的部分’其包括下列步驟: 在遠裝置層(105)中蚀刻至少一溝槽,界定一主動 組件(107)之面積; ~在該溝槽之邊牆上塗抹一層(109,),其摻雜劑在該 層(1091)中之擴散速度比在該掩埋層所處;之基底中快。 2. 如申請專利範圍第1項之方法,其特擎在於: —對與孩層(109’)直接接觸之該主動组件(1〇7)的面積. 實施梦植,以形成一接觸(丨丨乃。 3. 如申請專利範圍第1或2項之方法,其特徵在於: —在孩溝槽中之該層(1〇9|)上沈積或成長氧化物層 (11Γ)及/或氮化梦層。 4·如申請專利範圍第2項之方法,其特徵在於: 對該組件實施退火,直到掺雜劑往下擴散到該掩埋 導電層(108) ’但是仍離已摻植區域(115)很遠,以避免 造成崩潰電壓的下降。 5. 如申請專利範圍第4項之方法,其特徵在於:鄰近該接 觸(117)之該溝槽邊牆的部分(1〇9a)比剩餘之該溝槽邊 牆還遠離該已接植區域(11 5)。… 6. 如申請專利範圍第5項之方法,其特徵在於:鄰近該接 觸(117)之該溝槽邊牆的部分(109幻遠離已摻植區域(115) 之距離至少是2倍於剩餘之該溝槽邊輪。 7. 如申請專利範園第5項之方法’其特徵在於··非鄰近該 -1 - 本紙張尺度逋用中國國家標準(CNS) A4· (21GX297公董) -— -- (諳先閩讀背面之注意事項再填寫本頁) .裝. 、va 經濟部中央標準局員工消費合作社印製 A8 B8 时年ί。月丨I日1丨夕 C8 D8 ^ 補充 丨丨 1 .... 第8710〇712號專利申請案 申請專利範圍修正本(88年10月) 六、申請專利範圍 1. 一種達成接觸到一裝置層(105)中或下之一掩埋導電層 (108)之低電阻的方法,該裝置層(1〇5)構成一半導體組 件的部分’其包括下列步驟: 在遠裝置層(105)中蚀刻至少一溝槽,界定一主動 組件(107)之面積; ~在該溝槽之邊牆上塗抹一層(109,),其摻雜劑在該 層(1091)中之擴散速度比在該掩埋層所處;之基底中快。 2. 如申請專利範圍第1項之方法,其特擎在於: —對與孩層(109’)直接接觸之該主動组件(1〇7)的面積. 實施梦植,以形成一接觸(丨丨乃。 3. 如申請專利範圍第1或2項之方法,其特徵在於: —在孩溝槽中之該層(1〇9|)上沈積或成長氧化物層 (11Γ)及/或氮化梦層。 4·如申請專利範圍第2項之方法,其特徵在於: 對該組件實施退火,直到掺雜劑往下擴散到該掩埋 導電層(108) ’但是仍離已摻植區域(115)很遠,以避免 造成崩潰電壓的下降。 5. 如申請專利範圍第4項之方法,其特徵在於:鄰近該接 觸(117)之該溝槽邊牆的部分(1〇9a)比剩餘之該溝槽邊 牆還遠離該已接植區域(11 5)。… 6. 如申請專利範圍第5項之方法,其特徵在於:鄰近該接 觸(117)之該溝槽邊牆的部分(109幻遠離已摻植區域(115) 之距離至少是2倍於剩餘之該溝槽邊輪。 7. 如申請專利範園第5項之方法’其特徵在於··非鄰近該 -1 - 本紙張尺度逋用中國國家標準(CNS) A4· (21GX297公董) -— -- (諳先閩讀背面之注意事項再填寫本頁) .裝. 、va 經濟部中央標準局員工消費合作社印製 申請專利範圍 接觸(117)之該溝槽邊牆的部分是位於離已摻植區域 (115)小於1微米的位置。 8·如先前申請專利範圍第丨或2項之方法,其特徵在於: 在該層(1097、中使用複晶矽或多孔石夕。 9·如先前申請寻利範園第丄或〗項之方法,其特徵在於: 在該層(10少)中使用金屬矽化物。 10_如先前申請專利範圍第1或2項之方法,其特徵在於: 該裝置·層(105)包括單結晶矽。 11.如申請專利範圍第1〇項之方法,其特徵在於:該裝置 層(105)是位於一絕緣層(1〇3)上。 12·如先前申請專利範圍第!或2項之方法,其特徵在於: 該掩埋導電層(108)包括金屬矽化物。 13. ——種包括一裝置層(1〇5)之半導體組件,其中至少一主 動組件(107)是位於該裝置層(1〇5)中,且該主動组件 (107)疋以一溝槽來界定,並具有一掩埋導電層(1〇8), 其特徵在於: 經濟部中央標隼局員工消費合作社印製 (請先間讀背面之注意事項再填寫本頁) 一在該溝槽之邊牆上具有—層(1〇9,),其中摻雜劑在 該層(109)之擴散速度比該掩埋層所處之該裝置層中 快。 14. 如申請專利範圍第i 3項之半導體組件,其特徵在於: 在該主動組件(107)表面上具有一直接與該層(1〇9,) 接觸之一對掩埋導電層的接觸(丨17)。 15. 如申請專利範圍第13項之半導體组件,其特徵在於: 一該接觸(117)之摻雜劑經由該層(1〇9')擴散至掩埋導 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 電層(108),以便形成從接觸(117)連接至掩埋導電層 (108)之一低電阻。 16. —種包括一裝置層(105)之半導體组件,其中至少一主 動組件(7a)是位於該裝置層(105)中,且該主動組件(7a) 是以一溝槽來橫向界,定,並具有至少一已摻植區域(115) 及一掩埋導電層(10 :3 ),其特徵在於: —在該溝槽之邊牆上具有一層(109'),其中摻雜劑在 該層(1091)之擴散速度比該掩埋導電層(1〇8)所處之物質 中快; 一在該主動组件之表面上具有與該層(109')直接接觸 之接觸(117); 一該層(109,)包括與該集極接觸(in)相同的摻雜劑, 以形成從該集極接觸(117)連接至該掩埋集極(1〇8)的一 低電阻。 17. —種包括一裝置層(1〇5)之半導體組件,其中至少一主 動組件(7a)是位於該裝置層(1〇5)中,且該主動組件(7a) 是以一溝槽來橫向界定,並具有一基極(i丨5)、一射極 (113)及一掩埋集極(108) ’其特徵在於: —在該溝槽之邊牆上具有一層(1〇91),其中摻雜劑在 該層(1091)之擴散速度比該掩埋導電層(1〇8)所處之物質 中快; —在該主動組件之表面上具有與該層(1〇9,)直接接觸 之集極接觸(117); —該層(109')包括與該集極接觸(117)相同的摻雜劑, _ 3 · 本^氏張尺度適用中國國家標準(CNS ) A4規格(210X297公釐ΐ - (請先閱讀背面之注意事項再填寫本頁) -裝. 、1Τ 經濟部中央標準局員工消費合作社印裝 ^85526 as B8 C8 —_______08 _ '申請專利範圍 以形成從该集極接觸(1 17)連接至該掩埋集極(log)的一 低電阻。 18.如申請專利範圍第13, 14, 15, 16或17項之半導體組件,其 特徵在於:該層(109,)包括複晶矽或多孔矽。 19·如申請專利,圍第13> 14, 15, 16或17項之半導體組件,其 t 特徵在於:該層(10十)包括金屬矽化物。 > . 20.如申請專利範圍第13, 14, 15, 16或17項之半導體組件,其 特徵在於:包括該主動組件(107)之該裝置層(1〇5)是位 於一基底(101)上的一矽層’而在該裝置層(1〇5)及基底 (101)之間具有一絕緣層(103)。 21·如申請專利範圍第13, H,15, 16或17項之半導磕组件,其 特徵在於:鄰近該接觸(117)之該溝槽邊牆的部分(1〇9a) 比剩餘之該溝槽邊牆還遠離該已摻植區域(115)。 22. 如申請專利範圍第21項之半導體組件,其特徵在於: 鄰近該接觸(117)之該溝槽邊牆的部分(l〇9a)遠離已摻 植區域(115)之距離至少是2倍於剩餘之該溝槽邊牆·。 23. 如申請專利範圍第21項之半導體組件,其特徵在於: 非鄰近該接觸(117)之該溝槽邊牆的部分是位於離已摻 植區域(115)小於1微米的位置。 24. 如申請專利範圍第13, 14, 15, 16或17項之半導體组件,其 .特徵在於:該層(109·)包括複晶碎或多.孔碎。 25. 如申請專利範圍第13, 14, 15, 16或17項之半導體組.件,其 特徵在於:該層(1091)包括金屬矽化物。 本紙張尺度適用中國國家標準(CNS ) A4規格Ul〇X297公釐) --------裝------訂 — ----- (請先聞讀背面之注意事項再填寫本貢)
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US20020140030A1 (en) * | 2001-03-30 | 2002-10-03 | Mandelman Jack A. | SOI devices with integrated gettering structure |
US6830986B2 (en) * | 2002-01-24 | 2004-12-14 | Matsushita Electric Industrial Co., Ltd. | SOI semiconductor device having gettering layer and method for producing the same |
EP1353368A1 (en) * | 2002-04-11 | 2003-10-15 | AMI Semiconductor Belgium BVBA | Semiconductor structure and method for manufacturing the same |
JP4020195B2 (ja) * | 2002-12-19 | 2007-12-12 | 三菱電機株式会社 | 誘電体分離型半導体装置の製造方法 |
ITTO20050056A1 (it) * | 2005-02-03 | 2006-08-04 | St Microelectronics Srl | Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita' |
US20080121985A1 (en) * | 2006-11-07 | 2008-05-29 | International Business Machines Corporation | Structure and method to improve short channel effects in metal oxide semiconductor field effect transistors |
US7679164B2 (en) * | 2007-01-05 | 2010-03-16 | International Business Machines Corporation | Bipolar transistor with silicided sub-collector |
DE102008046388A1 (de) * | 2008-09-09 | 2010-03-18 | Infineon Technologies Ag | Vertikaler Bipolartransistor |
US8338265B2 (en) * | 2008-11-12 | 2012-12-25 | International Business Machines Corporation | Silicided trench contact to buried conductive layer |
DE102012003748B4 (de) * | 2011-03-01 | 2016-12-15 | Infineon Technologies Austria Ag | Verfahren zum Herstellen eines porösen Halbleiterkörpergebiets und zum Einbringen eines Fremdstoffes |
CN103022088A (zh) * | 2011-09-21 | 2013-04-03 | 株式会社东芝 | 具有沟道结构体的半导体装置及其制造方法 |
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JPS61191043A (ja) * | 1985-02-20 | 1986-08-25 | Toshiba Corp | 半導体装置 |
US4704368A (en) * | 1985-10-30 | 1987-11-03 | International Business Machines Corporation | Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor |
US5057443A (en) | 1988-06-29 | 1991-10-15 | Texas Instruments Incorporated | Method for fabricating a trench bipolar transistor |
US4965217A (en) | 1989-04-13 | 1990-10-23 | International Business Machines Corporation | Method of making a lateral transistor |
US5109263A (en) * | 1989-07-28 | 1992-04-28 | Hitachi, Ltd. | Semiconductor device with optimal distance between emitter and trench isolation |
US5278438A (en) | 1991-12-19 | 1994-01-11 | North American Philips Corporation | Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure |
US5358884A (en) | 1992-09-11 | 1994-10-25 | Micron Technology, Inc. | Dual purpose collector contact and isolation scheme for advanced bicmos processes |
US5283454A (en) * | 1992-09-11 | 1994-02-01 | Motorola, Inc. | Semiconductor device including very low sheet resistivity buried layer |
US5478758A (en) * | 1994-06-03 | 1995-12-26 | At&T Corp. | Method of making a getterer for multi-layer wafers |
US5643821A (en) * | 1994-11-09 | 1997-07-01 | Harris Corporation | Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications |
JP2708027B2 (ja) | 1995-10-05 | 1998-02-04 | 日本電気株式会社 | 半導体装置およびその製造方法 |
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CN1286803A (zh) | 2001-03-07 |
WO1999026293A3 (en) | 1999-07-15 |
CA2310280A1 (en) | 1999-05-27 |
JP2001523893A (ja) | 2001-11-27 |
EP1040517A2 (en) | 2000-10-04 |
KR100584969B1 (ko) | 2006-05-29 |
CN1132238C (zh) | 2003-12-24 |
SE9704211L (sv) | 1999-05-18 |
EP1040517B1 (en) | 2007-11-07 |
KR20010032149A (ko) | 2001-04-16 |
SE513471C2 (sv) | 2000-09-18 |
SE9704211D0 (sv) | 1997-11-17 |
DE69838683D1 (de) | 2007-12-20 |
WO1999026293A2 (en) | 1999-05-27 |
US6326292B1 (en) | 2001-12-04 |
AU1183999A (en) | 1999-06-07 |
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