TW510055B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Description

[Technical field to which this invention belongs] This meminger is related to a semiconductor device with an SOI (Silicon on Insulating Layer: Si 丨 icon 0n n ^ l at tor) structure and a method for manufacturing the same, especially for a semiconductor device that has no reach Isolation of an oxide film ”ρτγ (Partial Trench Isolation): a semiconductor device of Partial Trench Isolati and its manufacturing method. [Prior art] It has a semiconductor substrate, a buried oxide film, and a semiconductor layer. (Silicon on the insulation layer: SiliconON 0n Insulatt〇r) structure of the semiconductor device 'through the buried oxide film and the isolation of the elements reaching the buried oxide film (hereinafter referred to as " FTI "(full trench isolation): FuU Trench

Insulation), there is no need to worry about blocking when it surrounds the activation body. Therefore, compared with the surface of the semiconductor substrate, the junction capacitance is smaller, which can reduce the power consumption. Therefore, fields such as LSI are eager to obtain applications. Therefore, even if a CMOS transistor is formed and a very thin semiconductor layer is formed, the semiconductor device phase that forms the transistor can be used to achieve high-speed operation. At the same time, it can be used recently, especially for portable devices. However, it can be formed on a semiconductor substrate. The transistor is different. The semiconductor layer of the conventional structure has a semiconductor layer electrically buried from the buried oxide film and the semiconductor beauty plate, so it is produced by impact ionization in the active region.-Carrier (nMOS is a hole 'pMOS Are electrons) gathered in the channel forming region and the square semiconductor layer, thereby causing obstacles, making the working voltage withstand characteristics ^ / and the potential in the channel region is unstable, resulting in substrate floating effects such as the relationship between delay time and frequency Private peaks of various problems. ^ Dependence on King Su 4 solved

90102669.ptd 510055 V. Description of the invention (2) For these problems, the method of fixing the potential of the channel formation region is extremely effective. Japanese Patent Laid-Open No. Sho 5 8-1 2 4 2 4 3 has proposed a semiconductor device that fixes the potential of a channel formation region. ^ In recent years ^ 'It is not proposed to fix the potential of the channel formation region of each transistor, but to fix the channel formation region of several transistors of the same conductivity type together, and to isolate it by PTI for miniaturization. This structure Already at the IEEE International SOI Conference, Oct. 1999

Published in Pl31-132 and other literatures. Figure 22 is a cross-sectional view of a conventional semiconductor device. In the figure, a semiconductor substrate, 102 is a buried oxide film, 103 is a p-type semiconductor layer, 104 is an isolation oxide film, and 105 is Gate insulating film, 106 is the gate, and 108 is the source drain region, 109 is the side wall insulating film, ι is the wiring, 1 〇11〇 interlayer insulating film, 1 〇 丨2 is a p-type impurity region, 丨 0, and 3 are lice-forming films 104 that do not reach the buried oxide film 102 when they are formed. The two ^ -channel formation regions are connected to each other. For several of the same conductivity type, Electricity-body =: solid: the wiring of the potential of the channel formation region u 10 and the mouth-type impurities; impurities to reduce resistance. Respectful ΓΓΓΓ :: The two will: i wiring 1010 is placed at the isolation oxide high. In the following, it is called " borderless contact " to increase the element density. FIG. 23 is a cross-sectional view of a conventional semiconductor device. It is connected to the source. The wiring of the drain regions 107 and 108 is 1010 divisions. Isolated oxidation

510055 5. Description of the invention (3) The film 104 is formed on the surface. [Problems to be Solved by the Invention] However, using an isolation oxide film as the p TI structure, for a semiconductor device in which the potential of the channel formation region is fixed, the semiconductor layer under the PTI is very thin (about 5 nm squat), so substrate floating effects, etc. problem. This is because if the semiconductor layer under the PTI is thin, the PTI will detach from the potential distribution and line of the fixed channel formation area, which will cause the resistance between the wiring and the transistor to increase and affect the characteristics of the transistor. In addition, the resistance of each transistor and the channel forming region fluctuates according to the distance of the wiring from the potential of the fixed channel forming region, which causes the problem of fluctuations in device characteristics. If an unbounded contact structure is used to increase the density of the device, the interlayer insulating film 1 0 11 composed of the isolation oxide film 104 and the TEOS oxide film (tetraethyloxysilicate) is a homogeneous film, so it is an interlayer insulating film. When a contact hole 1 0 1 3 is formed on the substrate, a problem arises that the isolation oxide film 04 is also etched. 24 are cross-sectional views of a conventional semiconductor device. As shown in the figure, if the isolation oxide film 104 is etched, the pn junction and wiring 1 formed by the p-type semiconductor layer 103 and the source / drain region 1 07 or 108 under the isolation oxide film 10 are etched. The distance between 丨 〇 is shortened, causing an increase in junction leakage current. The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to suppress a semiconductor device having an "Isolation Insulation Film of PTI Structure ~" having the "the voltage of the channel formation region of several transistors can be fixed together" to suppress A floating effect of a substrate, a semiconductor device with improved isolation characteristics and withstand voltage, and a manufacturing method thereof. / 、 Its purpose is: for semiconductor devices without border contact structure, suppress

510055 5. Description of the invention (4) Semiconductor device with junction leakage current, miniaturization and low power consumption, and manufacturing method thereof. [Means for Solving the Problem] A semiconductor device to which the present invention belongs has a semiconductor substrate, a buried insulating film entirely disposed on a main surface of the semiconductor substrate, and a first conductivity type disposed on a surface of the buried insulating film. The semiconductor layer is composed of a SOI substrate. An isolation insulating film formed on the main surface of the semiconductor is provided between the first activation region and the second activation region disposed on the main surface of the semiconductor layer, and a conductive layer is left between the buried insulating films. Semiconductor in the first activation zone

The first source region stone of the second conductivity type formed at regular intervals on the main surface of the bulk layer, and the first region and the first source electrode are formed on the main surface of the semiconductor layer with the first gate insulating film interposed therebetween. The first gate opposite to the region between the drain region and the drain region, < the i-th conductive type that electrically connects the semiconductor layer under the insulation film with the region sandwiched between the first source region and the drain region The j-th impurity region, the first interlayer insulating film formed on the surface of the f-conductor layer and the isolation insulating film in the first and fourth activation regions, the hafnium nitride formed on the first interlayer insulating film, and the surface of the nitride film The second interlayer insulating film formed and the contact holes formed by the first and second interlayer insulating films are respectively connected to the first source region and the non-electrode region.

/ Wiring connected to the ridge and the shell area, through the interlayer insulation film to form a lice silicon film on the surface of the element, Tian a L i — semiconductor under the film] stress of the silicon nitride film, in the isolation QinUM0S as a hole / 5 ^ = Defect of the life-controlling body, resulting in a shortened life of the carrier. The third activation region, 、, and 铽 are provided with a separation between the third activation region and the first activation region on the main surface of the semiconductor layer.

Page 7 510055 V. Description of the invention (5) The insulating film is provided on the fourth activation region of the main surface of the semiconductor layer, the second impurity region of the second conductivity type formed on the main surface of the semiconductor layer of the fourth activation region, and A second source region and a drain region of the first conductivity type formed at a certain distance from the main surface of the second impurity region are formed on the main surface of the semiconductor layer through a second gate insulating film and a first gate electrode. 2 The second gate, the semiconductor layer under the isolation insulating film, which is opposite to the area separated by the source region and the drain region, is formed on the main surface of the semiconductor layer in the third active region, and is the same as the second source region and the drain. The third impurity region of the second conductivity type in which the regions separated by the electrodes are electrically connected. The isolation insulating film is formed on the main surface of the semiconductor layer with the semiconductor layer buried between the insulating films remaining. The first interlayer insulating film, the silicon nitride film, and the second interlayer insulating film are formed until the third and fourth activations. On the surface of the semiconductor layer in the region, wirings connected to the second source region, the drain region, and the second impurity region are provided through contact holes formed in the first and second interlayer insulating films and the silicon nitride film, respectively. Defects in the semiconductor layer under the insulating film increase the reciprocity between adjacent pMOS transistors and n M0S transistors. This semiconductor device is characterized by having a third activation region disposed on the main surface of the semiconductor layer, and a fourth activation region disposed on the main surface of the semiconductor layer with an isolation insulating film interposed between the third activation region and the first activation region. Region, a second impurity region of the second conductivity type formed on the main surface of the semiconductor layer in the fourth active region, and a second source of the first conductivity type formed at a certain distance on the main surface of the second impurity region. A second gate electrode facing the region separated from the second source region and the drain region on the main surface of the semiconductor layer through a second gate insulating film and an isolation insulating film via the second gate insulating film The lower semiconductor layer is formed on the main surface of the semiconductor layer in the third active region and is separated from the second source region and the drain region.

90102669.ptd page 8 5. Description of the invention (6) _ = the third impurity region of the second conductivity type. The isolation insulating film provided by the i-th activation and the second reaches the buried insulating film, the first, the second, the siliconized film, and the second interlayer insulating film extend to the surface of the semiconductor layer in the second region. The i-th and m-th intervals between j and 4 [: I Ϊ? Are provided with contact holes respectively connected to the second source region and the membrane electrode and

" The wiring in the impurity region improves the withstand voltage between adjacent pMOS transistors. Μ] The PM porosity solar body and the nMOS are connected to the source region and the drain region by the wiring extension diode = drain region's surface of the insulating insulation film " :： 于: 催 = :::: ^ The source and drain regions are connected to the I electrode. It can fully maintain the semiconductor layer: the distance between the ρη junction formed by the electrode and the wiring. The original two two ί and 4 mesh adjacent connections The 2-pole region and the drain region of the wiring extending to the surface of the isolation insulating film, the semiconductor device i in the isolated wiring line, even if it is two: the conductive type is characterized by impurities, since; = exposed when the contact hole is formed. The insulation region of the insulating film is the same as the adjacent r-pole. There is no pole region and it is dangerous to the source 1. A semiconductor device characterized by a leakage current at the junction of a double-tapped portion of the semiconductor layer, with the help of nitrogen, Invasion of the source insulating film and buried oxide film at the source i. Features of the semiconductor device, the total = 2 forms a metal oxide layer as a metal oxide layer in the first interlayer insulation during etching 90102669.ptd page 9 510055 5 Explanation of the invention (7) The film can terminate the rest of the film, and increase the safety factor of the rest of the film. It also has: via buried oxidation The first and second active regions are arranged on the main surface of the semiconductor layer of the SOI substrate with the first conductive type semiconductor layer formed on the surface of the semiconductor substrate, and a portion of the insulating insulating film is left at the lower part of the first and second active regions. A forming step, a step of forming a first impurity region of a first conductivity type on the surface of the semiconductor acoustic region of the second active region, forming a first gate 2 on the main surface of the semiconductor layer via a free insulating film, A step of isolating the main surface of the i-th gate region of the semiconductor layer of the first activation region from the π b drain region of the second conductivity type at a predetermined distance, half of the i-th and second activation regions; The step of forming the i-th interlayer insulating film on the surface of the film and the surface of the film, the step of forming a silicon nitride film on the edge of the film, and the step of forming a film of silicon nitride on the surface of the silicon nitride film. A contact hole 2+ step is formed on the i-th and second interlayer insulation films and the nitrogen-cut film to reach the first source region, the drain region, and the i-th impurity region, and is connected to the contact holes respectively through In the wiring formation step of the source region and / or the hafnium region, the lifetime of the edge conductor layer of the nitride nitride film is generated. The defect of the control body can shorten the lifetime of the carrier (nMOS is a hole and PM0S is an electron). In addition, the main surface of the semiconductor layer surrounds the third activation region and the third activation region. Adjacent to the arrangement of the :: film is completed before the step of forming the isolation insulating film; = the formation of the second conductivity type in the fourth activation region before the formation of the mass region has the step of: the mass region and has the third activation region Step of forming a third impurity region of the second conductivity type on the main surface of the semiconductor layer of the semiconductor layer, in the second centroid region: the main 90102669.ptd page 10 V. Description of the invention (8) and the second hetero YV: pole number: ί : 2 [the step of the gate f, and the main table of the area facing each other] and the second step: the step from the second source region and the drain region.丄 ^ The interlayer insulation L-nitride second region " on the surface of the conductor layer in the first and second electrode regions and the second impurity region of the self-cut / knife formation can reach the second source region and the drain device, in F A semiconductor PMOS transistor and a -8 transistor characterized by the step of forming a contact hole :::: == a semiconductor device that improves adjacent latching performance. The properties of B,, and i can be obtained to improve the resistance to the step of forming the contact hole, the step of 苴 and the formation of the ## 疋, and the second interlayer insulating film is etched. In order to suppress the over-etching of the semiconductor layer, the isolation insulating film reaching the source region, the drain region, and the non-electrode region is adjacent to each other: =: Cheng, and the source region device, respectively, with a silicon oxide film The semiconductor with the characteristics of acoustic, ^ +, etc. is etched to form a contact hole. Θ Β ′, ^, and the second interlayer insulation 臈 contact conditions can suppress the semiconductor layer; the junction of the insulation = = dangerous flow At the same time of the semiconductor device: silver engraving of the semiconductor layer and the source electrode will not be fully maintained; = a material with a high selectivity ratio of / 朕 is etched 90102669.ptd page 11

d J V. Description of the invention (9) -------- 3 进行 /, * ¥ body device made of a material with a lower selection ratio than the nitride nitride film, using the selection ratio with the silicon nitride film Since the etching is performed on the substrate, the rim, and the second interlayer insulating film, a contact hole with good controllability k can be formed. [Embodiment of the present invention] (Embodiment 1) FIG. ^ Is a cross-sectional view of a semiconductor device of Embodiment 1, showing a semiconductor substrate at a ton t; 2 is a buried oxide film; 3 is a semiconductor layer; 81 Said: emulsified film; 5 is the gate insulation film; 6 is the gate; 7, 71, 8 and the edge 2 1 z and the pole 3 area; 7 2 and 8 2 are the sack-type implantation area; 9 is the side wall insulation, 'And 1 1 0 疋 wiring; 11 is an interlayer insulating film; 2 is a p-type impurity; 13 is a contact hole; 14 is a silicon nitride film. FIG. 2 is a plan view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the A-A cross section shown in FIG. 2. In FIG. 2, & And 111, nitride nitride film 14, wiring 10, 72 "] edge ^ 9, source, drain and drain regions 71 and 81, and pocket implantation region. Figure 1 On the surface of semiconductor substrate 1, The semi-conductor and layer 3 are formed by burying the oxide film 2 on both sides, and the substrate is called ", s〇 丨 substrate". The formation method is ^ adhesion method, s 〖M〇χ method and other methods, which one is used? Fang > Master = 卩 Yes. The thickness of the buried oxide film 2 is 100nm ~ 500nm, the thickness of the substrate is about 30nm ~ 400nm, and the content of the additive-containing impurities is about 1 X 1015 ~ J χ 1018 / cm-3. Isolation and insulation of p-type impurity region 12 and oxide oxide film formed by semiconductor layer 3 苐 Page 12 \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd 510055

The local isolation region formed by the film 4 (pt i) surrounds the activation region formed by the transistor to isolate them from each other, and the minimum isolation width is about 20 nm. The film thickness of the isolation insulating film 4 corresponds to 1/2 to 1/3 of the film thickness of the semiconductor layer 3, and the film thickness of the semiconductor layer 3 under the isolation oxide film 4 is set to about 10 to 200 [n]. It is preferable that the upper surface of the isolation insulating film 4 be micro-processed so as to have the same height as the surface of the semiconductor layer 3. When the semiconductor layer 3 is thin, if the thickness of the semiconductor layer 3 under the isolation insulating film 4 is desired to remain sufficiently,

The required film thickness of the isolation element 'is to make the upper surface of the isolation oxide film 4 higher than the surface of the semiconductor layer 3' to improve the element isolation characteristics. Between the f-conductor layer 3 and the isolation insulating film 4, a 5 to 30 mm thick dagger stone film * is formed as necessary (see Fig. ^). Here, as the isolation insulating film 4, a fossil film is used, and various other films such as a silicon nitride film, a silicon oxynitride film, a silicon oxide film containing a spoon, or a porous silicon oxide film may be used. Source. Drain region 7, 8, 71, 81, pocket implantation region 72, 8 formed by implanting impurities in the semiconductor layer 3, ρί Fortunately '£ 12 a has a range of 1x 10π ~ lx 1〇18 / cm3 range of B iso ^ The three-pocket implantation areas 72 and 82 contain a concentration of 1χ 1〇1? ~ ΐχι〇ΐ 9 / Μ3: 道 道; V The σ bag implantation areas 72 and 78 are In order to suppress

The tray is optimized by adjusting the depth of the gate insulation film and the source / drain: junction, and sometimes it is not necessary to form a mouth plant. Source and non-polar regions 7 and 8 contain a j with a concentration of j, etc. η-type impurities reach the buried area 7 丨 and 78 when they are formed. They contain stones with a concentration of 1 × γ X 1019 ~ 1 X 1021 / cm3 in the range of oxide film 2 and source · drain 1 〇2Q / cm3. Isotype

DESCRIPTION OF THE INVENTION (11) _ ::, the pole diode regions 7 and 8 are both LDD (lightly doped drain region) regions 7 and 8 which cannot be reached sometimes. Source.

Membrane ;, there is si. 2. si〇N barium acid gill) J :, a2 ° 5, Al2〇3, BST 臈 (BaxSri-xTi〇3 ·· titanium- ^ '; lf00 ^ 2 5 X 1 〇2〇 / Cm3 11 ® „t , rs ^

HfSi2 > PdSi P; S · v2c: 2 '^ 12' M〇Si ^ ', p 12 ZrSl2 and other metal silicide layers, or a metal layer with w, Mo metal structure il; can also be composed of W, On the surface of CU, CU, Ⅱ, they are jealous at the source. Drain regions 7 and 8 and P-type impurity region 12 are not shown. 2) 1 tSl2, ZΓδΐ2 and other metal silicides are also available (film 9 in the figure is made of oxide stone). Even film, TEGS film, SiA film, or SiA 2 or ® layer film, etc., siaN4 film or Si ^ / Si02 laminated film etch = film, even if the mask forming the contact hole 13 is misaligned, it will not work. Due to the superimposed effect with the nitride stone film 14, as a source region, the conductor sound 3 ", the pole and vine and the pole region 7 and 71, 8 and 81 are adjacent to each other and the half of the channel formation region must work in stress. The density of defects generated under the action increases, and the channel forming products (nM0S is a hole and PM0S is an electron) are absorbed by the source region, which can further suppress the floating effect of the substrate. The interlayer insulating films 11 and 111 are formed by plasma CVD method LPCVD (low pressure

90102669.ptd Page 14 510055 V. Description of the invention (12) Learn about vapor deposition) or atmospheric pressure CVD, etc. The thickness of the interlayer insulating film 11 is 10 ~ 30nm, and the interlayer insulating film丨 丨! '’Said 100 ~ 20 0 0 ·. And 'instead of the oxide stone film, use TE0s (yo x'), tetraethyl film, SOG (roller coating on glass plate) film, implanted impurities (phosphosilicate glass), BSG (borosilicate) Glass), BpSG / = ub salt glass) or BPTEOS (Boron Phosphate Tetraethyloxy Silicate) and other shapes & Cheng Hu also in addition to forming 0. 1 ~ 0. 5 // diameter of the contact hole 13 parts in eight faces A silicon nitride film 14 having a thickness of 50 to 100 nm is formed. Then, a defect is formed on the semiconductor layer 3 under the isolation insulating film 4 through the silicon nitride film 14 'FIG. 3 shows a semiconductor device according to an embodiment of the present invention. The cross-sectional view is an enlarged view of a portion surrounded by a dotted line B shown in FIG. 1. As shown in the figure, defects are formed under the insulating film 4. The network is often ': is the composition of the silicon nitride film' and is known to contain stress as "10 dyn / cm2 of _4,0 iSixNy in a ratio can control the film stress. If you further add 〇2, you can also control the film's stress by adjusting the 〇: N ratio. Therefore, instead of the nitride nitride film, it can be opened to form gas, melons, and u ^ to form a silicon nitride nitride film (Si ON). . / Next, the operation will be explained.去去 m Ί ,,; ^ said to identify 66 _ π ♦ 丄 Consider Figure 1 for example. For the nMOS case, the voltage applied to each electrode \ = 1.8V, .8v,: r :. VB = 0V forms a channel on the surface of the gate 5 and the lower semiconductor layer 3, [, and m and 71, or the source. The-side of the drain regions 8 and 81 is the source & 'the other side is > And the polar regions, Niu Yiyi, and work in writing. The semiconductor layer 3 under the isolation insulating film 4 is connected to the semiconductor 下 M ^ under the gate 6, and the r J dry conductor layer 3 is the same, including a p-type impurity.

90102669.ptd Page 15 510055 5. Description of the invention (13) Therefore, the semiconductor layer 3 under the gate 6 is applied with a voltage from the wiring 1 1 0 through the impurity region 12. The voltages listed above are just one example, and the voltage varies with the thickness of the gate insulation film and the gate length. In the first embodiment, a description is given of a case where an nMOS transistor is formed. When a pMOS transistor is formed, impurities contained in the semiconductor layer 3 are n-type impurities such as phosphorus and arsenic, and the source and drain regions 7 are formed. The impurities contained in 8, 8, 7 and 81 are P-type impurities such as boron, and the impurities contained in pocket implant regions 7 2 and 82 are n-type impurities such as As, P, or Sb. The contained impurities are p-type impurities such as boron. Instead of the p-type impurity region, an n-type impurity region may be formed. The voltages applied at this time are: voltage two 0V, VD = 0V, Vs = 1.8V, VB = 1.8V. In this embodiment, an example of the wiring 10 and 1 10 is given. The number of layers and the arrangement of the interlayer insulating film formed between the wiring and the transistor are changed according to the different configurations of the circuit. Although a semiconductor device in which an transistor is formed in an active region has been described, it is not limited to this. The first embodiment is described with reference to an example in which a silicon nitride film 14 is formed in its entirety. For a semiconductor device (not shown) in which PTI and FTI are used in combination, if silicon nitride is formed in a region where PT I is used as element isolation. The film 14 can improve the isolation characteristics. Fig. 4 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention, and 141 in the figure is a silicon nitride film. As shown in the figure, while the sidewall insulating film 9 is formed of a nitrogen-containing film such as a Si3N4 film or a laminated film of Si3N4 / Si 02, the

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I. V. Description of the Invention If a silicon nitride film 141 is formed on the surface of (14), the danger of connection to the wiring 10 is not to be considered. & Generating gate electrode 6 FIG. 5 shows another semiconductor device according to the embodiment of the present invention, and FIG. 6 shows another semiconductor device according to the embodiment of the present invention.

These figures from Lifi show that 'the gate electrode 6 and the source electrode and the drain region 7 ° are two: ΪΪ = the wiring 10' The contact hole diameter of this part is about twice the diameter of the other t = contact hole. A semiconductor having such a structure ^. The blade is a common contact structure. The gate 6 and the source. The drain region 7 is used to suspend memory cells and the like at the same potential, except that the semiconductor device shown in the wiring structure 2 = 1 has the same structure. And FIG. 7 shows another semiconductor according to the embodiment of the present invention, that is, an interlayer insulating film, 131 is a contact hole, and 21 is a wiring. ? According to the plan view, the gate electrode 6 is formed through the contact hole 131 formed in the interlayer insulating film 113, and the formation area of the contact hole 131 is the same as that of the figure except for the FTI of the isolation insulation phase: ... 2 1 and 2 are plan views of the semiconductor device shown by the semiconductor, and FIG. 7 is a cross-sectional view taken along a section D_D shown in FIG. 8. The part is m. In Fig. 8, for the sake of simplicity, consider the mask of [8 virtual trunk line 2]. In order to ensure that the clothes are not separated from each other, Γ Γ: When the contact hole 131 is formed, even if the cover screen is shifted to the insulation layer, the semiconductor layer 3 is reached. Page 17 90102669.ptd 510055 V. Description of the invention (15) According to the semiconductor device described in the first embodiment, the semiconductor substrate includes a semiconductor substrate, a buried insulating film disposed on the entire surface of the semiconductor substrate, i, and S0 formed by a semiconductor layer disposed on the surface. The main surface of the substrate is composed of an element. The silicon nitride film i formed on the surface of the device via the interlayer insulating film formed on the semiconductor device formed by the stress of the silicon nitride film under the isolation insulating film causes a defect of the life-controlling body, the carrier (nM. s is an electric hole and an electron). Therefore, even when the semiconductor layer under the insulating film is thin, the potential of the channel formation region under the gate can be stably fixed, the correlation between the delay time and the frequency can be suppressed, and the floating effect of the substrate can be suppressed. Reliability. According to public opinion, if hydrogen is invaded in the gate electrode, if the hydrogen terminal appears on the interface of the semiconductor layer and the interlayer, the ability to resist hot carriers will be reduced. However, since the silicon nitride film is formed, hydrogen can be prevented from invading the gate insulating film and buried in the oxide film, and the ability to resist hot carriers is improved. For the silicon nitride film control, the ratio of ^ to ^, or for the silicon oxynitride film to control the ratio of 0 to N, can increase the stress of the nitrogen-cut film and the oxygen-nitrogen cut film, and can improve the isolation and insulation of PTI. The degree of occurrence of defects in the semiconductor layer under the film can increase the effect of the life control body. Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. 9 to 13 are sectional views showing one step of the method for manufacturing a semiconductor device according to the first embodiment. In FIG. 9, 31 is a silicon oxide film, and 32 = a trench. Referring to FIG. 9, a silicon oxide film 31 having a thickness of 5 to 40 nm is formed on the surface of the semiconductor layer 3 of the 301 substrate with a buried oxide film 2 and a semiconductor layer 3 disposed on the surface of the semiconductor substrate. The formation method of "as a silicon oxide film"

90102669.ptd 510055

V. Description of the invention (17) i Oxygen: Surface-to-semiconductor layer 3 thickness difference in the thickness direction, 32 and ^ 1 films are etched with wet phosphoric acid to remove the silicon nitride film 1 + The silicon wafer 3 丨 forms an isolation insulating film 4. Fig. 11 is a cross-sectional view showing the final step of this step. ^ Γ 4 丨 Before the silicon oxide film is deposited, at a high temperature of 900 ~ 100 ° C and a low temperature, the corners of Shi Xi formed at the bottom and sides of the ditch 41, and the Han screen ¥ 41 Side and abundance guide turns φ arc band ^ ^ ¥ The corners of the silicon formed on the surface of layer 3 are rounded

The arc shape reduces the stress on the part. After the silicon oxide film has been fully formed by the chemical conversion method (not shown in the figure), an opening area is formed in the photoresistance: high-density region of the electronic wiring area. (Not shown), in the case of leaking S, implanted B, bf2, sound! Ions' formed with a concentration of impurities of lx 1017 ~ lx 1018 / ⑽3, as the shell area 12. In the case of pMos, ions of 11 i such as p, As, and sb are implanted to form an n-type impurity region. In the case of nM0S, the quality must be fully implanted with impurities such as butterflies and fluorinated decay. In the case of a cutoff, the impurity ions such as P and As are fully implanted. ^ The voltage of the ion is 1Q ~ 2QKeV, and the concentration is ΐχΐ () ΐ2 ~ 5χ ㈣ ′. Impurities are introduced by adjusting the threshold of the through-force formation region (not shown in the figure). The oxide film can be used to protect the surface of the semiconductor substrate during ion implantation. The oxide film is not removed after ion implantation. Figure 2 of A ^ 1 is used as the gate insulating film 5. For example, after forming a 7 to 10 nm-thick oxide oxide film on the semiconductor substrate, the front surface, and the front surface by a thermal oxidation method, use the LPCVD method Select 彳 ηη, λλ ^ 7 polycrystalline silicon layer, and then use a photoresist to cover the screen Η = especially cover (not shown in the figure) by means of RIE or

\\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 20 510055 5. Description of the invention (18) EC: Isotropic anisotropic drawing pattern, layer 6. At this time, on the surface of the polycrystalline silicon, after the laminated film of the sun and the sun and the silicon oxynitride film, use the film pattern of the film, and then use the drawn film to process many pairs of this; Membrane system. Α Evening silicon layer can also be used. In addition, f S i is deposited on the surface of the Xixi layer today, and it is also possible to draw a map after the Shixi material layer is formed (not shown in the figure). Then, when it is nMOSH, boron and fossil p-type impurities are implanted. When it is PMOS, ions of P, As # n-type impurities are implanted, and the degree of implantation is lx HF ~ lx 10H / cm2 to form a pocket.式 implantation zones 72 and 82. Then, in the case of nMOS, phosphorus and arsenic are implanted; in the case of pM0s, boron and boron fluoride are implanted, the implantation voltage is 20 ~ 40keV, and the implant density is 10h ~ 1x to form a pocket-type implantation area at 81 °. Second, a plasma CVD method was used to fully deposit a silicon oxide film with a thickness of 30 ~ 1001). After the sidewall insulation film 9 was formed by over-etching, it was nM0s. In the case of PM0S, boron and boron fluoride are implanted. The implanted electrical thickness is 10keV and the implanted ion density is lx 1014 ~ 1x 1016 / cm2. Original • Drain Regions 7 and 8. FIG. 12 is a cross-sectional view of a semiconductor device showing a step at the end of this step.

510055 V. Description of the invention (19) The source and non-electrode regions are made of LDD structure, so sometimes the source electrodes are not formed; and the electrode regions 7 and 8. The implanted impurities can be activated by annealing at 800 ~ 1150 ° C for 10 ~ 30min. When metal silicide layers such as COS i2 are formed on the surfaces of gate 6 and source drain regions 7 and 8, cobalt is fully deposited in this step, and RTA treatment (rapid annealing heat treatment) is performed to expose Shi Xi ’s The surface of the gate electrode 6 reacts with the surfaces of the source and non-electrode regions 7 and 8 to form a metal silicide layer in this region. Then, the remaining cobalt (not shown in the figure) that has not reacted is removed. In addition to CoS i2, metal silicides such as TiSi2, NiSi2, WSi2, TaSi2, MoSi2, HfSi2, PdSi, PtSi2, and ZrSi2 may be formed. In Fig. 13, '302 is a photoresist mask. Referring to FIG. 1 ', a stone oxide film as the interlayer insulating film 11 having a thickness of 10 to 300 nm is deposited by a plasma C V D method, a L P C V D method, or a normal pressure c V D method. Instead of the silicon oxide film, the interlayer insulating film 11 may be a film formed by a TE0S film, a SOG film, an impurity-implanted PSG, BSG, BPSG, or BPTEOS, or the like. The above-mentioned oxide film deposition step may be omitted if necessary. Then, it is formed by LPCVD method (600 ~ 800 ° C), plasma c VD method (300 ~ 500 ° C), or atmospheric pressure CVD method (300 ~ 500 °). Silicon nitride film 14 with a film thickness of ~ 50 ～ 100nm. Instead of a silicon nitride film, SiON may be used, and the composition of Si and N may be different from that of SiM. A film formed by the lpcvd method, film thickness It has good uniformity, has the advantages of good compactness and chemical stability. When the plasma CVD method and the atmospheric pressure CVD method are used to form a film at a low temperature, it is equal to _, so the TED of the impurities can be suppressed (immediate increase in diffusion). Behavior, it has the advantage of improving the current driving ability of the transistor.

510055

The CVD method is relatively easy to control the silicon nitride film and stress. The composition ratio of Si and N can therefore be compared with the formation of 11 ′ to form an interlayer insulating film with a thickness of 100 to 2000 nm, read and flatten it by CMP treatment, and then ^: eliminate surface roughness caused by CMP treatment, and form The interlayer insulating film is again deposited with a silicon oxide film with a thickness of 50˜200 nm (not shown in the figure).

. Its-person, on the surface of the interlayer insulating film 丨 丨 丨, forms a contact hole 13 connected to the source / drain region \, 8 and the p-type impurity region 12, and an area with an opening is formed in the area where the contact hole 13 is formed. Photoresist mask 302, and then on an RIE, magnetron RIE, or ECR device, an etching gas such as X = 4 ″ y = 5 with a high selection ratio to the silicon nitride film is used to interlayer The insulating film 1 1 1 is etched. In this case, H2 and CO may be used as the additive gas. FIG. 13 is a cross-sectional view of the semiconductor device showing the end of the step. Secondly, under the condition that the silicon nitride film and the silicon oxide film have a low selection ratio, the remaining silicon nitride film 14 and the interlayer insulating film 11 are etched to form a contact hole 13. Then, W is deposited by a cover CVD method. After the contact holes 13 are buried, they are flattened by engraving. Subsequently, aluminum is fully deposited, a pattern is drawn, and wirings 10 and 丨 formed by w and A 1 are formed to form a semiconductor device as shown in FIG. 1. Then, the interlayer insulating film and wiring (not shown in the figure) are deposited in the same steps as the steps of forming the interlayer insulating film 111 and the wirings 10 and 110. As a method for depositing the wires 10 and 110, a CVD method may be selected. Instead of W, aluminum may be deposited by a high-temperature sputtering method and a reflow sputtering method (ReflOw sputter), and T i and doping may be deposited by a LPCVD method. Polycrystalline eve

90102669.ptd

V. Description of the invention (21) __ Instead of aluminum, deposit A〗 Cusi y as the wiring material, when using the second person > heteropolycrystalline silicon can also be used. A barrier layer metal such as TiN is formed, and Meng Bahua's inner wall of each contact hole is formed in this embodiment, and the diffusion into the semiconductor layer 3 is performed by the intermetallic / square method (the contact hole and the distribution of the p-type impurity region). Steps to form the contact with the source and drain regions are based on the circuit configuration. The formation of the contact holes and wirings can be changed if necessary. Alternatively, the order of formation can be changed at the source and drain regions as required. At s, 'the metal dream material layer can be used as a table' to increase the etching range. For the etching when the interlayer insulating film is etched, the conductor substrate and the semiconductor λ stroke 66 shown in this embodiment 1 are used. Method 'On the main surface of the semi-substrate and the semiconductor substrate, the buried insulating film, which is fully arranged on the surface of the # 1 and μa soil surface, is formed on the main surface of the S0 substrate consisting of a semiconductor layer. The lukoku 1 on the surface of the device forms a silicon nitride film, so the silicon nitride film is trapped by the silicon nitride film. The semiconductor layer under the edge film has a life-span defect. Is the hole, pM0S is the life of the electron). = Semiconductor under the insulating film Even if the layer is very thin, 纟 can stably close the second 辇: the electric ⑯ of the Γ channel formation area, suppress the floating effect of the phase soil plate with the delay time and frequency, and can manufacture highly reliable semiconductor devices. Hydrogen is intruded into the electrode insulating film, and the semiconductor; and the termination of hydrogen appears on the interface of the gate insulating film, the ability of resisting hot carriers is reduced. However, since the silicon nitride film is formed, hydrogen can be prevented from invading. 90102669.ptd Page 24

510055 V. Description of the invention (22) Manufacturing method of semiconductor device with electrode insulation film and buried oxide film ^ The ability to withstand hot carriers is formed on the sen substrate. = = Buried oxide film) The effect of ra ^ τ is even greater. Using a silicon nitride film,

Film thickness under the silicon nitride film _ 1 ^ 庶 ′, interlayer insulating film of the sub-car, 、 2 thin interlayer insulating films are etched separately for H contact holes, so by controlling the excess of the semiconductor layer: avoiding junctions Semiconductor device with leakage current. "Bad to pay for the implementation of Xingxiong 2, Fig. 14 and Fig. 15 show that the present invention will be able to swim # 0 and. Ym 1 The semiconductor device of Dn is not hairy moon shell yoke 2 The section of the semiconductor device is η: / '' And decay, 井 P well, 34 is n-well, 73 and 74 and 83 and 84 and 77 and 86 and 87 疋 P-type source. Infinity region, 78 and 88 heart-type ion implantation region, 121 is p The n-type impurity region 122 is an n-type impurity region. In this embodiment, an nM0S transistor formed by implanting ions in the semiconductor layer is formed, and a PM0S transistor PTT, ΛPF structure is formed in the n-well 34. The transistor and the transistor are separated by PTI, and the p-type impurity region 121 or the n-type impurity region 122 'is fixed to each other through a semiconductor layer under ρτ in the transistor channel formation region. The P-well 33 contains Impurities such as b, osmium 2, and In at a concentration of lx 1015 to 1019 / cm3, and p well 34 contains impurities such as P, As, and osmium at a concentration of x1015 to 1019 / cm3. N-type When the gate 6 of the M 0s transistor has a polycrystalline silicon layer, the concentration of apricots is 2 to 15 ″. Impurities contained in the polycrystalline silicon of the gate 6 of the bipolar body, sometimes p-type impurities such as boron

90102669.ptd Page 25 V. Description of the Invention (23) (Double-gate structure), other semiconductor devices are the same. According to this embodiment, the semiconductor insulating film of the semiconductor element provided on the surface of the semiconductor substrate forms nitrided insulation. The semiconductors under the film (nMOS is the potential floating effect of the semiconductor layer path formation area under the hole film. When using a CMOS junction, the effect of the reliability of the isolated P-well 33 and η-well 34 can be used. It is well known that, And gate insulation film is low. However, due to the effect of the electrode insulation film and the embedding. As shown in Figure 15, the manufacturing steps sometimes contain η-type impurities (single gate structure). Since the film thickness and The impurity concentration is the same as that of the semiconductor device shown in 0-state 2 shown in Embodiment 1. A semiconductor substrate, a buried insulating film disposed on the surface, and a semiconducting semiconductor are formed on the main surface of the SOI substrate. On the device, since the interlayer stone film is interposed on the surface of the device, the stress of the silicon nitride film causes the defect of the life control body to occur in the spacer layer, and the load can be shortened (PM0S is an electron) Life. Therefore, even if the insulation is thin, it is possible to stably fix the on-gate under gate and suppress the dependence of the delay time and frequency on the manufacture of a semiconductor device with high reliability. In the case where PTI is adjacent to the reverse conductivity type transistor, defects occurring in the semiconductor layer under the edge film increase the voltage resistance between the adjacent layers, which can improve the possibility of semiconductor devices invading hydrogen in the gate insulating film, The termination of hydrogen on the interface of the semiconductor layer results in the ability to resist hot carriers. 4 A nitride nitride film is formed. Therefore, hydrogen can be prevented from entering the gate oxide film. The ability to improve the resistance to hot carriers can be obtained. The M0S region and the p-rib region 8 are complicated, but can improve the blocking resistance.

510055 V. Description of Invention (24) Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described. FIG. 16 is a cross-sectional view showing one step of the method of manufacturing a semiconductor device shown in Embodiment 2. In FIG. 16, 303 is a photoresist mask. First, as in the first embodiment, an isolation insulating film 4 is formed on the surface of the SO I substrate on which the semiconductor layer 3 is arranged on the surface of the semiconductor substrate 1 via a buried insulating film. Then, a photoresist mask 303 with an opening in the nMOS region is formed, and impurity ions such as B, BF2, and In are implanted on the entire surface to form a p-well 33 having a concentration of 1 × 15-151019 / cm3. Fig. 16 is a cross-sectional view showing the components of the semiconductor device at the end of this step. Then, the photoresist mask 30 is removed. As with the formation of the P well 33, a photoresist mask with an opening in the pMOS region is formed, and ion implantation of n-type impurities such as P, As, and Sb is performed on the entire surface thereof to form an impurity concentration of 1 X 1 〇15 ~ 1 〇 19 / cm3 n-well 34 (not shown in the figure). Ran, 丄 Remove the photoresist mask. By the same method as that described in the first embodiment, P-type impurity 121 and 1! -Type impurity region 122 are formed. In addition, the impurity is implanted, and the conductive portions different from the nMOS region and the pMOS region are separated by a photoresist mask opened in each region. Impurities are introduced in the same manner as in the first embodiment. y According to the method for manufacturing a semiconductor device according to the second embodiment, a semiconductor substrate, a buried insulating film provided on the entire surface of the semiconductor substrate, and a SiO substrate formed of a semiconductor layer provided on the surface are provided. On a semiconductor device in which a semiconductor element is formed on the main surface,

510055

The formation of nitrogen stress through the interlayer insulating film and the depression under the insulating insulating film can shorten the carrier (nMOS is the reason, the correlation of the channel formation region under the semiconductive fixed gate under the insulating insulating film, etc. The floating effect, the fossil evening film 'therefore uses the silicon nitride film + conductor layer to generate a life-span failure of the lifetime control body. Electricity: Even if it is thin, it can stably suppress the delay time and frequency to make highly reliable semiconductor devices. When the CMOS structure is adopted and the PTI is adjacent to the inferior channel +

The effect of improving the reliability of the semiconductor device in the semiconductor layer between adjacent p-wells 3 3 and n-wells 3 4 is improved. ^ Pressure resistance 纟 has been improved a little. It is well known that if a terminal terminal of hydrogen appears in the gate insulating film ^ and the gate insulating film, chlorine gas is low in the semiconductor layer. However, since a silicon nitride film is formed, the capability of the hot carrier is reduced, and the insulating film and the buried oxide film can be discharged to a manufacturing method of a semiconductor device to prevent hydrogen from entering the gate. X-transfer network resistance to hot carriers

Using an atmosphere fossil film, the interlayer insulation film and contact hole of the thinner film thickness of the silicon nitride film on the silicon nitride film is lower than the interlayer insulation film. The control of the semiconductor layer is controlled by: 2 Etching forms a semiconductor device that prevents junction leakage current. Figure 17 shows a semiconductor according to a third embodiment of the present invention. In the figure, 132 is a contact hole, and 31 is a wiring. A cross-sectional view of the clothing. In this embodiment, the interlayer insulating film η, η silicon film 14

510055 5. Description of the invention (26) The contact hole 132 formed is formed across the surfaces of the source drain regions 7 and 8 and the sea bass. The wiring 310 connected to the source electrode 8 through the contact hole 132 is formed on the isolation insulating film. 4 on the surface. Except for this, the two structures are the same as those of the first embodiment. Fig. 18 is a cross-sectional view showing a semi-guide π of the third embodiment of the present invention as shown in Fig. 4F. For the sake of illustration, the interlayer insulating film is made of tritium and nitrogen, and the side wall insulating film 9 and the source and drain electrodes 4 and 4 are implanted regions 72 and 82. Next, the semiconductor device shown in the pocket type according to the third embodiment has a semiconducting μ Γ across the insulating film at the source / drain R phase and the Chara phase. Boundaryless contact structure B: Shi Xi film 'so it reaches the source. The contact hole 4 without the electrode can inhibit the insulation layer from holding the semiconductor layer and the source. Knife, y, thumb,-from a, and the Pn junction formed by the polar region and the distance between the device μ selection, at the same time can obtain highly reliable semiconductor production, semi-conductor substrate surface Embedded S > S7 1 * # β Ϊ On the semiconductor device of S0 1 substrate = conductor element composed of a semiconductor layer arranged on the surface, a silicon nitride film is formed by an interlayer insulating film Therefore, the semiconductor layer under the insulating film with the aid of yttrium nitride, the lifetime of the control body, °, the life of the 钿 button carrier (nM0S is a hole, pM0S is an electron): the semiconductor under the two insulating film Even if the layer is very thin, it can stabilize the electricity in the channel forming area under the gate. Bit, suppress delay time and frequency

510055 V. Description of the invention (27) = Correlation of substrates and other floating effects can improve the reliability of semiconductor devices. It is well known that if hydrogen is intruded into the gate insulating film, and hydrogen termination occurs at the interface between the semiconductor layer and the gate insulating film, the ability to resist hot carriers is reduced m 'because of the formation of a nitride nitride film', hydrogen can be avoided The effect of invading the ice film and burying the oxide film in the sapphire island has the effect of improving the resistance to heat carriers. FIG. 19 is a cross-sectional view showing a semiconductor device according to the third embodiment, and a 23 疋 η-type impurity region. Referring to the figure, impurities such as P, As, and Sb of the n-type impurity 123 are connected to the region 123 and are formed by expanding the contact hole 132 & domain formed in the insulating insulating film 4 toward the center region of the insulating insulating film 4. After the n-type impurity is formed in the contact hole 132, the structure is the same as it is separated from the obliquely upward direction. The semiconductor structure of the + conductor device that is in contact with the 5 boundary of the stomach m is not separated from the insulation film exposed at the time of formation, which can eliminate the leakage current at the junction of the part, and a silicon nitride film is formed on the surface. 'For this embodiment, but for the half use of PTI and FTI combined Chengming ^^. PTI ^ 4, ^ improved. 1 to make the isolation feature

90102669.ptd Page 30 V. Description of the invention (28) The dagger spans the source #. The drain regions 7 and 8 and the surface of the isolation insulating film 4 form a nitride 310 on the surface of the wiring 310 portion to form a shape of the insulating film 4. The structure with no boundary contact in the 1m path is also suitable for semiconductor devices other than those in Embodiments 1 and 2, and has the same effect. f ^, a description will be given of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Fig. 21 is a cross-sectional view showing one step of the method of manufacturing a semiconductor device according to the third embodiment. In Fig. 21, 304 is a photoresist mask. f First, as in the first embodiment, an insulating insulating film 4 and a p-type impurity f region are formed on the surface Φ of the semiconductor = board 1 through a buried insulating film (in the case of deleting $, an n-type impurity region is formed) , Gate insulating film 5, gate 6, pockets and 82, source and drain regions 71 and 81, side wall insulating film 9, and pole regions 7 and 8. * The skin electrode and the embodiment are similar to the following example: after the interlayer insulation mi 1 and the inter-layer insulation film 111 are formed, the CMP treatment is used to eliminate the maggots caused by the CMP treatment, and then the Bayi are used to remove WI. The surface is rough, and it is insulated with interlayers-sub-deposited 50 ～ 20_thick oxide stone film (not shown in the figure), and then, on the surface of interlayer insulating film, the surface of i and 8 and p-type impurities 菡 9 # 拉 识 旧 n 你 ”Lu pole · drain region 7 A pi u μ = = 0 The area formed by the junctions 13 and 132, P &, the first blocking mask 304 after opening ^, forming an insulation At this time, the contact hole 132 is not only 7 in ”, the interlayer and δ are formed, and the money contact hole is formed in the isolation + 疋 in the source · drain region 7. Figure 21 shows the end of this step :, The clothing pattern is also 510055. V. The cross-sectional view of the element of the invention description (29). Its-human 'is nitriding; the selection ratio between the 5th film and the oxide stone film residuals the interlayer insulating film η to form a contact engraved half and The guide body is placed in the installation state. Then, it is separated from the implementation] _ 掸 出). M'1 # 'to form a multilayer wiring structure (not shown in the figure according to this implementation In the semiconductor device shown in state 3, the adjacent isolation insulating film is made to the source. The drain method is used in a semiconductor device with a cross-border contact structure. The edge of the tap wiring is m JM BB ^ knife.] On the weathered stone film The thick and thin layers of the film, the edge film, and the "nitride stone Xixia, the film" control etching strip #, imitating [· (· "T r, the thinner interlayer insulation waist" fj The contact box component can thereby suppress the semiconductor to obtain a semiconducting semiconductor which does not cause a shallow leakage current at the interface. It can be fully maintained to suppress the distance between the insulating film and the line, which can improve the device density of the semiconductor device and May 4 halves = 矣 全面 embedded semiconductors that are fully arranged on the surface of the semiconductor substrate, semiconductor devices with semiconductor elements formed on the main surface of the SOI beauty pole composed of a semiconductor layer with an ice film on its surface, ", An interlayer insulating film is formed on the surface to form a nitride nitride film. Therefore, the stress of the film can isolate the semiconductor layer under the insulating film, which can shorten the carrier (nM0S is a hole, pM: two u: missing, so the insulating film is isolated). Under semiconductor layer 5 ":叩. W 1 is very stingy, and can also be stable 90102669.ptd page 32 510055 V. Description of the invention (30) Correlation between the channel formation area under the fixed gate and other substrate floating effects, such as electrical value, suppression of delay It is well known that high-reliability semiconductor devices can be manufactured at time and frequency. If lice are invaded in the gate insulating film and the hydrogen terminal appears on the interface of the gate insulating film, the ability to resist hot carriers is two. However, due to the formation of Since the nitride stone film is used, a method for manufacturing a conductor device can be obtained by using a cowl insulating film and an embedded oxide film towel. [Effects of the present invention] Since the present invention has the structure described above, it has the following effects. According to the present invention, a semiconductor substrate or a semiconductor substrate is disposed on the surface of the semiconductor substrate. Insulation film, main film made of B, and semi-conductor layer on the surface of the semiconductor layer. The semiconductor device that forms a semiconductor element on the main surface of the soil plate is used to interlayer insulation on the surface of the element. The film forms a silicon nitride film, which contributes to the stress of the silicon nitride film and causes defects in the semiconductor layer under the isolation insulating film to shorten the life of the carrier (for holes, ⑽⑽, and ions). . Therefore, even if the semiconductor layer under the insulation film is complex or thin, the potential of the channel formation region under the gate can be stably fixed, and the floating effect of the substrate such as the dependence of the delay time and frequency can be improved, which can improve the reliability of the conductor device. High sex. When a CMOS structure is used to adjoin the reverse-conduction transistor through PTI, the defects occurring in the semiconductor layer under the insulating film are used to improve the withstand voltage characteristics between adjacent PM0S transistors * nM0S transistors. Raise half

V. Explanation of the invention (31) The effect of the reliability of the conductor device. Therefore, the two adjacent mitochondriving transistors and nM are made into a house. The property 1 improves the reliability of the semiconductor device / effect resistance Adjacent isolation and insulation films in the source: the centerline of a semiconductor device with a borderless contact structure == the ㈣ of the film, which can fully maintain the semiconductivity;: = = and ... can also obtain a semiconductor device with improved reliability. It is possible to be exposed when ㈣2: ΐ. The insulating insulation film = there is an impurity region of the same conductivity type as the ㈣.drain region to prevent the junction between the junction and the leakage current t conductor layer, can be: A :: Swollen, if invading hydrogen in the gate insulation film, the semiconductor sound: Gate edge :: Medium: Out: Terminal of hydrogen, the ability to resist thermal carriers' = insulation film and buried oxide film towel, can Obtain the effect of improving the anti-hot carrier ability. If a metal silicide is formed on the surface of the source region and the drain region, the huminite layer will act as a barrier layer when the first interlayer insulating film is left. ί: The wiring is formed with good controllability, so a highly reliable semiconductor device can be obtained. 510055 V. Description of the Invention (32) A semiconductor element is formed on the main surface of a semiconductor substrate, a buried insulating film disposed on the surface of the semiconductor substrate, and a main surface of a soi substrate composed of a semiconductor layer disposed on the surface. In a semiconductor device, a silicon nitride film is formed on the surface of an element through an interlayer insulating film. Therefore, by using the stress of a nitride nitride film, the semiconductor layer under the insulating film has a defect of a life control body, which can shorten the carrier ( n ^ 〇S is a hole, pMOS is an electron). Therefore, even if the semiconductor layer under the insulation film is very thin, the potential of the channel formation region under the gate can be stably fixed, and the floating effect of the substrate such as the correlation between the delay time and frequency can be suppressed, and a highly reliable semiconductor device can be manufactured. . * When a CMOS structure is used to adjacent a reverse-conduction transistor through a PTI, a silicon nitride film is formed between the interlayer insulating films, so a depression occurs in the semiconductor layer, and the adjacent PM0S transistor and nM0S transistor are improved. The second resistance is ^ J, and the latch-up resistance is improved. It has the effect of improving the reliability of the semiconductor device. The outer 2 S Ϊ1 upper interlayer insulating film and the second interlayer insulating film form a dagger. This controls the interlayer insulating film. The etching conditions under control the over-etching of the semiconductor layer to obtain a bulk device. There are 1T semiconducting interface leakage currents that are semiconducting across adjacent isolation insulation films at the source. Semiconductor devices with no-border contact structure for the drain / etching of the first interlayer insulation film and the second interlayer insulation film ： 2 Semiconductor devices that perform leakage current according to Wang Y

510055 5. Description of the invention (33) At the same time, the formation of contact holes reaching the source and drain regions can suppress the etching of the isolation insulating film, and can sufficiently maintain the pn junction and wiring formed by the semiconductor layer and the source and drain regions. The distance between them can improve the element density and reliability of the semiconductor device. The first interlayer insulating film and the second interlayer insulating film are etched by using a selection ratio with the silicon nitride film π formed between the first interlayer insulating film and the second interlayer insulating film, so that a highly controllable film can be formed. The contact hole can manufacture a highly reliable semiconductor device. [Explanation of component number] 1 semiconductor substrate 2 buried oxide film 3 semiconductor layer 4 isolation insulating film 5 gate insulating film 6 gate 7 ~ 71, 8, 81 source / drain region 72 ~ 82 pocket implantation region 9 sidewall insulation film 10, 110 wires 11, 111 interlayer insulation film 12 P-type impurity region 13 contact hole 14 silicon nitride film 31 silicon oxide film

\\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 36 510055 V. Description of the invention (34) 32 Silicon nitride film 33 P well 34 η well 41, 42 Ditch 113 Interlayer insulation film 131 Contact hole 210 Wiring 301 Photoresist curtain 303, 304 Photoresist curtain 310 Wiring 121 ρ-type impurity region 122 η-type impurity region 101 Semiconductor substrate 102 Buried oxide film 103 P-type semiconductor layer 104 Isolation oxide film 105 Gate insulating film 106 Gate 107, 108 η-type source and electrodeless region 109 sidewall insulating film 1010 wiring 1011 interlayer insulating film 1012 ρ-type impurity region 1013 contact hole

90102669.ptd Page 37 510055 Brief Description of Drawings Fig. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a semiconductor device according to the first embodiment of the present invention. 3 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. 4 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. 5 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. FIG. 6 is a plan view showing a semiconductor device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. 8 is a plan view showing a semiconductor device according to the first embodiment of the present invention. Fig. 9 is a sectional view showing a step of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 10 is a sectional view showing one step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 11 is a sectional view showing one step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 12 is a sectional view showing one step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 13 is a sectional view showing a step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 14 are cross-sectional views showing a semiconductor device according to a second embodiment of the present invention. 15 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. Fig. 16 is a sectional view showing one step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. 17 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. 18 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

\\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 38 510055 Brief Description of Drawings Fig. 19 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. FIG. 20 is a plan view showing a semiconductor device according to a third embodiment of the present invention. Fig. 21 is a sectional view showing one step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 22 is a cross-sectional view showing a conventional semiconductor device. FIG. 23 is a cross-sectional view showing a conventional semiconductor device. 24 are cross-sectional views showing a conventional semiconductor device. 〇

\\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 39

Claims (1)

510055 6. Scope of patent application1. A semiconductor device comprising at least a watch plate and a semiconductor hibiscus arranged on the surface of the substrate, and a marginal base. S0 I substrate composed of Shouban Zeng, the upper layer has an active area and a first conductive type second active area configured on the main surface, and includes. V 电 孓 弟 1 isolation insulation film, with A semiconductor layer is formed between the first and second activations and the surface of the substrate, and a semiconductor region is formed on the main surface of the semiconductor layer. The first interlayer insulating film of the conductor layer is formed on the first 1 away from the insulating film; the silicon nitride film formed on the above-mentioned first layer > insulating film between the chemical region and the above-mentioned spacer <1; and the above-mentioned nitride nitride film 2. If the scope of patent application: wide: / 20% of the second interlayer insulating film. Board, including semiconductor = 1 to △ semi-t conductors, a fully equipped buried insulating film, the above-mentioned semiconductor device on the main surface of the V soil plate | Yes. In the above-mentioned first activation region of Φ 矣 the second conductive type The first source region and the first gate electrode formed at a predetermined interval of the polar region are formed on the first source electrode region with the first gate insulating film on top of the first source region. The first impurity region of the first conductivity type on the main surface is opposed to each other; the first semiconductor region is formed in the region i or the region i separated by the above-mentioned one source region and the drain region under the isolation f edge film; : The contact holes formed by connecting the first, second, and third wirings with electrical holes through the upper film and the silicon nitride film @ 6 处 弟 _ 弟 2 interlayer insulation 臈 are respectively connected with the first Source \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 40 510055 VI. Patent application area, drain region and the first impurity region are connected. 3. The semiconductor device according to item 2 of the scope of patent application, wherein the semiconductor layer has a third activation region of the second conductivity type and a fourth activation region of the second conductivity type disposed on the main surface thereof, and the above-mentioned isolation insulation The film is further disposed between the third activation region, the first activation region and the fourth activation region, and the isolation insulating film disposed between the third and fourth activation regions is embedded with the above. A part of the second semiconductor region of the semiconductor layer remains between the insulating films, is formed on the main surface of the semiconductor layer, and the isolation insulating film arranged in the first and fourth activation sections is connected with the buried insulation. A portion of the third semiconductor region of the semiconductor layer remains between the films, and is formed on the main surface of the semiconductor layer. The semiconductor device further includes: formed on the main surface of the semiconductor layer in the fourth activation region at a certain interval. And a second gate region of the first conductivity type and a gate region and a second gate are formed on the main surface of the semiconductor layer through the second gate insulating film to form the second source region and the second gate region. Polarized The second impurity region of the second conductivity type is formed on the main surface of the semiconductor layer of the third active region through the second semiconductor region under the isolation insulating film and is opposite to the second source region It is electrically connected to the area separated from the drain region. The first interlayer insulating film, the silicon nitride film, and the second interlayer insulating film are respectively formed on the surfaces of the semiconductor layers in the third and fourth active regions. , \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd page 41 510055 ~, patent application scope is also equipped with 4th, 5th and 6th wiring, through the first and second interlayer insulation film and the above The contact holes formed by the silicon nitride film are respectively connected to the second source region and the drain region and the second impurity region. 4. The semiconductor device according to item 2 of the patent application range, wherein the semiconductor layer further has a third activation region of the second conductivity type and a fourth activation region of the second conductivity type disposed on the main surface thereof, and the above-mentioned isolation and insulation The film system is further disposed between the third activation region and the first activation region and the fourth activation region, and the isolation insulating film system disposed between the third and fourth activation regions is embedded with the above. A part of the second semiconductor region of the semiconductor layer is left between the insulating films and is formed on the main surface of the semiconductor layer. The isolation insulating film system disposed between the first activation region and the fourth activation region is formed to reach the embedment. The insulating film further includes: the second source region and the drain region of the first conductivity type, which are formed on the main surface of the semiconductor layer of the fourth active region at a constant distance; and a second gate electrode. A region separated from the second source region and the drain region is formed on the main surface of the semiconductor layer via the second gate insulating film, and a second impurity region of a second conductivity type is interposed between the second gate insulating film and the second impurity region. Under the insulation film The second semiconductor region is electrically connected to a region formed on the main surface of the semiconductor layer of the third active region and separated from the second source region and the drain region; the first interlayer insulating film and the silicon nitride And the second interlayer insulating film are formed on the surfaces of the semiconductor layers of the third and fourth active regions, respectively. \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd page 42 6. Scope of patent application = connection: connection: page]: two edge film and upper electrode region and the above-mentioned second impurity region. 2. The source of the second source area and the second half of the second range of the patent scope of the second patent, the above-mentioned magic and installation of the first source area and the non-polar area ^, the middle connection is adjacent to the above source N and = of the region and the non-polar region include respective wirings. A. The above-mentioned isolation system is a 6-sided semi-conductor on the surface of the lamina membrane. The region of the isolation source Γ :: = has the same conductivity type as the local conductive layer: miscellaneous ^ 7 :, a semiconductor of any one of the items i to 6 of the monthly patent range. The above-mentioned silicon nitride film includes a silicon nitride film that is fully formed. The semiconductor device according to any one of items 2 to 6 in the 8, _ΪΠ2 range, 1 / is further provided with a surface /, a metal silicide layer in the first source region and the drain region described above. 9. A method for manufacturing a semiconductor device, comprising: a step of obtaining a SOI substrate having a semiconductor layer through a substrate having at least a surface as an insulation, and the first surface of the semiconductor layer 2 having first conductivity The first and second active regions of the type are: ζ The main table contains: The μ method further includes (b) the first and second active regions surrounding the first and second active regions, and the first semiconductor region of the semiconductor layer remaining in the lower region is formed. Step of isolating an insulating film '. [Part (f) Steps of forming a first interlayer insulating film on the semiconductor layer of the first and second active regions and above / mentioned < \ film surface; L mesh insulation \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 43 510055 6. Application scope (g) The step of forming a nitrided nitride film on the first interlayer insulating film; and (h) the nitrogen And a step of forming a second interlayer insulating film on the surface of the silicon film. 10. The method for manufacturing a semiconductor device according to item 9 of the scope of patent application, wherein the substrate includes a semiconductor substrate and a buried oxide film formed on the semiconductor substrate, and the method for manufacturing the semiconductor device further includes: (c) a A step of forming a first impurity region of a first conductivity type on the main surface of the semiconductor layer of the second activation region; (d) forming a first gate insulating film on the main surface of the semiconductor layer of the first activation region via a first gate insulating film; 1 gate step; (e) forming the first source region of the second conductivity type at regular intervals on the main surface of the region facing the first gate across the semiconductor layer of the first activation region; and And the step of the electrode region, (i) forming contact holes that reach the first source region and the drain region and the first impurity region on the first and second interlayer insulating films and the silicon nitride film, respectively; Step; and (j) a step of forming first, second, and third wirings connected to the first source region and the drain region and the first impurity region through the contact holes, respectively. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor layer further includes a third activation region of the second conductivity type and a fourth activation region of the second conductivity type on the main surface thereof. The 4 activation area is disposed adjacent to the first activation area, and the third activation area is adjacent to the fourth activation area. \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 44 510055 6. It is set up in the scope of patent application, including: guide package half} cover 1 i The above description is obtained; > Description 7 Miscellaneous La spoon J: c White type table ί The upper part of the main layer and the upper layer / i Living in the body guide semi-narrative section, you can get the heterogeneous type table and the upper layer to be activated The upper part of the description includes the step-by-step conductance Γ1 conductance I ............. **-the first inductive ground and conductance 2 the first inductive ground and _ the first layer Introducing the upper part (part b describes the steps in the upper part of the remaining part of the upper part of the lower part of the formation and union type, the square area of the living area of the guide membrane: margin (C abrupt step step separation step The first type conductance is described in the above step, the second type is conductance, the second is the forming area, and the third is the cover. The first edge of the film is separated from the top edge by the barrier. The second cover is> (d 成 (e Step-shaped step-by-step step-by-step step-by-step step-by-step description of the upper layer of the P body is described by the semi-introduction. The main polarization zone of the zone is activated to determine the interval between the first forming distance, the main zone of the step meter of the upper station surface, and the second phase of the phase pole source gate. (The above steps and steps are based on the silicidation of the film and the interlayer surface coating system, and the semi-zero zone is activated on the r film (i. The first and the upper membranes form an absolute interstitial extension layer 1 in the fourth series, and the upper shaped membranes are formed as described above. The upper i-plane has, < the polar membrane draws the margins and the absolute source 2 2 The above mentioned ΓχΙ #, rLJ} on the above-mentioned hole formed by stepwise contact with the hole; the contact region of the contact region is connected to the plasmic region of the prime, k, w, Above 2) * Step cj and step above and step above and above and above the source and source and area I \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 45 510055 Sixth, the scope of patent application Steps 5 and 6 wiring. 1 2. The method for manufacturing a semiconductor device according to item 10 or 11 of the scope of patent application, wherein the step (i) includes: (i -1) a step of etching the second interlayer insulating film; (i-2) and The above step (i-1) is a step of independently etching the first interlayer insulating film. < 1 1 3 · The method for manufacturing a semiconductor device according to item 12 of the patent application range, wherein the contact hole obtained in the above step (j) includes the above-mentioned isolation adjacent to the source region and the drain region, respectively. A contact hole formed on the insulating film. 14. The method for manufacturing a semiconductor device according to item 12 of the scope of patent application, wherein the above step (i-1) includes #etching the above-mentioned interlayers according to the first substance having a certain ratio with the selection ratio of the silicon nitride film. Step of insulating film; The step (i-2) includes a step of etching the interlayer insulating film in accordance with a second substance having a selectivity ratio lower than the first substance to the silicon nitride film. Φ \\ 312 \ 2d-code \ 90-05 \ 90102669.ptd Page 46