TW552681B - Phase change memory and manufacturing method thereof - Google Patents

Abstract

The present invention provides a manufacturing method of phase change memory, which is applied in a semiconductor substrate. The method comprises firstly forming an N+ epitaxial layer and an N- epitaxial layer on the semiconductor substrate; next forming a first shallow trench isolation structure in the N+ epitaxial layer and an N- epitaxial layer to isolate the predetermined word line region, and forming a second shallow trench isolation structure in the said N- epitaxial layer to isolate the predetermined P+ doped region; then forming and defining an insulative layer and applying an N+ doping on part of the N- epitaxial layer to form an N+ epitaxial layer electrically connected to the N+ epitaxial layer, and applying P+ doping to the N+ epitaxial layer to form a P+ doped region; forming a contact plug on the N+ epitaxial layer and P+ doped region through the insulative region; forming an electrode having an upper electrode, a phase change layer and a lower electrode on each of the contact plugs.

Description

552681 V. Description of the invention (1) Field of the invention The present invention relates to a memory, in particular to a phase change memory and a manufacturing method thereof. ° Heart Related Technology Description

Figure 1 shows the structure of a conventional phase change memory. The modified memory structure includes a semiconductor substrate 10, an N + doped layer 12 formed on the semiconductor substrate 10, an N-doped layer 14 formed on the N + doped layer 12, and an N + doped layer. The region 16 is formed in the N-doped layer 14, a P + doped region 18 is formed in the N-doped layer 14, and an insulating layer 20 is formed on the semiconductor substrate 10. The insulating layer 20 may be an oxide layer. The contact plug 22 includes a barrier layer 24 and a metal layer 26. Electrodes 28 are formed on the contact plugs 22, respectively. The electrodes 28 include an upper electrode 34, a phase change layer 32, and a lower electrode 30. The thickness and doping concentration of the N + doped region and the Bu doped region in the conventional phase change memory structure are difficult to control, so that the breakdown voltage (BDV) cannot be adjusted. And the adjacent P + / P + interval and the adjacent character line / character line are prone to breakdown. Therefore, the component size cannot be easily reduced. SUMMARY AND OBJECTS OF THE INVENTION As semiconductor devices are moving toward larger integrated circuit devices, it is necessary to reduce feature line widths and multilayers. In view of this, an object of the present invention is to provide a phase and a manufacturing method thereof, which replace the traditional ion implantation by using an epitaxial layer and a shallow trench isolation structure (STI). The use of an epitaxial layer can increase the thickness of the N + doped region and the N-doped region and control the uniform doping concentration to adjust the breakdown voltage (BDV). Use STI $ trench

552681

The separation structure prevents adjacent P + / P + regions | from punching. Therefore, the method can be greatly reduced. According to the above purpose, the method of the present invention is suitable for forming a first shallow trench region in a semiconductor substrate into an N + solar layer and an -n-stupid layer epitaxial layer and in the above-mentioned N-epitaxial layer. A predetermined P + doped region is formed in the layer. Secondly, an N + doped region of an N + doped layer is applied to the above N-telecrystalline layer and the N + P + doped region is performed. Then, an upper electrode is formed on the above N + forming a plug through the insulating layer. The present invention also provides a phase change bottom; an N + epitaxial layer is formed on the N + insect crystal layer. A partition is formed in the N + epitaxial layer and the N + epitaxial layer; the P + epitaxial layer is isolated from the p + Sexually connect the device and the adjacent character line / character line, and the component size. To provide a method for manufacturing a phase change memory is first formed on the semiconductor substrate. Next, a predetermined shallow word-line isolation structure is isolated on the above N + shading layer and N-isolation structure to isolate and define an insulating layer, and for the part to form an electrical connection to the above N + epitaxial The crystal layer performs a P + doping to form a doped region and a contact plug on the P + doped region. Finally, the electrodes of each of the contact change layers and the lower electrode are used. Memory, including: a semiconductor-based semiconductor substrate; an N-epitaxial layer; a shallow trench isolation structure formed in the predetermined zigzag line region; a P + doped second shallow trench isolation structure , Forming a doped region; an N + doped region formed in the M + epitaxial layer; contact plugs, respectively

Formed on the N + doped region and the P + doped region; and electrodes are formed on each of the contact plugs', respectively, having an upper electrode, a phase change layer, and a lower electrode. The first shallow trench isolation structure may also be formed in the N + epitaxial layer, the N- epitaxial layer, and the semiconductor substrate.

0389-7381twf (n); IDF200111334; P900527; YCCHEN > ptd Page 6 552681 Five 'invention description (3) Examples ▲ First, referring to Figure 2, it shows the phase change according to the embodiment of the present invention. Structure top view. The phase change memory structure includes a semi-conductive substrate 100; an insulating layer 111 is formed on the semiconductor substrate 100, and the insulating layer 111 may be an oxide layer. This phase change memory structure still includes a P + doped region 11 7, a word line 200, a bit line 300, a first shallow trench isolation structure 106, and a second shallow trench isolation structure 11. . Even

Figures 3 to 4 are cross-sectional views of AA 'according to Figure 2, and Figures 5 to 8 are cross-sectional views of BB according to Figure 2. Referring to FIG. 3, an embodiment of the present invention first provides a semiconductor substrate 100, an N + epitaxial layer 102 and an N-epitaxial layer 104 are successively formed on the semiconductor substrate 100. The n + epitaxial layer 102 and the N-stupid layer 104 may be formed by selective epitaxy. The thickness of the N + epitaxial layer 102 is preferably 400 to 600 Angstroms, and the thickness of the N-stupid layer 104 is smaller than Preferably it is from 800 to 12,000 Angstroms. Referring to FIG. 4, a first shallow trench isolation structure 10 is formed in the semiconductor substrate 100, the N + epitaxial layer 102 and the epitaxial layer 104 to isolate a predetermined word line region 1 08. The manufacturing method of a shallow trench isolation structure usually first selectively etches a semiconductor substrate to form a shallow trench, and then uses chemical vapor deposition (CVD) of the insulating material, such as atmospheric pressure chemical vapor deposition (atmospheric) pressure chemical vapor deposition (APCVD) or sub-atmospheric pressure chemical vapor deposition (SAC VD) or high density plasma chemical vapor deposition (HDP-CVD) Stone dioxide and other materials

552681 5. Description of the invention (4) Fill the above shallow trench, and then apply chemical mechanical polishing (CMP) to flatten the above silicon dioxide material, leaving a shallow trench isolation structure. Referring to FIG. 5, a second shallow trench isolation structure 110 is formed in the N-epitaxial layer 104 to isolate a predetermined P + doped region 109. The second shallow trench isolation trench structure 110 can be fabricated using the method described above. &Quot; Referring to FIG. 6, an insulating layer is formed on the N-epitaxial layer 104, and then the insulating layer 111 is defined by using a photoresist 112. The insulating layer 111 is preferably deposited by using a low-pressure chemical vapor deposition method.

(tetra-ethyl-ortho-silicate; TEOS). The thickness of the insulating layer Hi is preferably 2000 to 3000 Angstroms. Then, anisotropic reactive ions are used to leave the insulating layer 111 to form a first opening 11 3, and then an N + doping is performed on the N-stupid crystal layer 104 through the first opening 1 13 to form a The N + doped region 114 of the n + telecrystal layer 102 is electrically connected. The N + doping is preferably performed by arsenic or phosphorus ion implantation. The concentration is preferably 1015 to 2 X 1 (P atoms / cm2, and the energy is preferably 10 to 30 keV.... Please refer to FIG. 7 and use the photoresist 11 5 define the insulating layer, and then use anisotropic reactive ion etching to etch the insulating layer. 1 to form a second opening 116 'and then to the N-epitaxial layer through the second opening 116. Doped to form a P + doped region 117! ≫ + doping is preferably performed with boron ion implantation, and the concentration is preferably 1015 to 1 X 1 〇i6 atomc: / 2 from Tiandong at 0ms / cm2, energy It is preferably 1 to 3 keV. Please refer to FIG. 8 to show a rn U 1 1 D PJ at the first opening. A contact plug 118 is formed, and the contact plug 118 includes a metal layer 120. The barrier layer 119 is preferred In order to use the chemical wind > s ~ disaster chemical deposition method for deposition

552681 V. Description of the invention (5) Titanium nitride. The metal layer 120 is preferably deposited using physical vapor deposition. An electrode 128 having an upper electrode 126, a phase change layer 124, and a lower electrode 122 is formed on the contact plug 118. FIG. 8 shows a phase change memory structure according to an embodiment of the present invention. The phase change memory structure includes a semiconductor substrate 10 (Γ, an N + epitaxial layer 102, an N-epitaxial layer 104, a first Shallow trench isolation structure 106 (shown in FIG. 4), a second shallow trench isolation structure 110, an N + doped region 114, a P + doped region 117, a contact plug 118, and an electrode 128. A shallow trench isolation structure 106 is formed in the semiconductor substrate 100, N + epitaxial layer 102, and N- epitaxial layer 104 to isolate a predetermined zigzag line region 108 (shown in FIG. 4) ° P + doped region 117 Formed in the N-epitaxial layer 104. A second shallow trench isolation structure 110 is formed in the N-epitaxial layer 104 to isolate the P + doped region 117. The material doped region 114 is formed in the N-epitaxial layer. The N + worm crystal layer 102 is electrically connected within 104, and the contact plugs 118 are formed on the N + doped regions Π4 and P + doped regions 11 7. The electrodes 1 28 are formed on the contact plugs 18 and 18, respectively. The electrode 128 has an upper electrode 126, a phase change layer 124, and a lower electrode 122. The thickness of the N + stupid crystal layer 102 is preferably from 4,000 to 600 angstroms, and the thickness of the epitaxial layer 104 is preferably from 8000 to 6,000. 1200 Angstroms The first shallow trench isolation structure and the second shallow trench isolation structure 11 can be fabricated by using the above method. The present invention can increase the "doped region-the thickness of the doped region and control the uniform doping by using an epitaxial layer". The impurity concentration is used to adjust the breakdown voltage (BDV). The use of shallow trench isolation structure can prevent punching between adjacent p + / p + sections and adjacent word lines / word lines. Therefore, the component size can be greatly reduced. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to

552681 V. Description of the invention (6) The invention is limited. Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention shall be regarded as the attached patent. The scope defined shall prevail.

0389-7381twf (n); IDF200111334; P900527; YCCHEN.ptd Page 10 552681 Simple explanation of the diagram Simple explanation of the diagram Figure 1 is a sectional view showing the structure of a conventional phase change memory. Fig. 2 is a top view showing a phase change memory structure according to an embodiment of the present invention. Figures 3 to 8 are cross-sectional views of the fabrication process of the body according to the phase change in the embodiment of the present invention. Symbol description 100 ~ semiconductor substrate; 102 ~ N + stupid layer; 104 ~ N- epitaxial layer; I 0 6 ~ A shallow trench isolation structure; II 0 to a second shallow trench isolation structure; 114 to N + doped regions; 117 to P + doped regions; 11 8 to contact plugs; 1 2 8 to electrodes, 108 to a predetermined word Yuan line area; 1 2 6 ~ upper electrode; 124 ~ phase change layer; ¥ I 2 2 ~ lower electrode; II 9 ~ barrier layer; 1 2 0 ~ metal layer; 111 ~ insulating layer; 2 0 word line;

0389-7381twf (n); IDF200111334; P900527; YCCHEN.ptd page 11 552681 The diagram briefly explains 3 0 0 ~ bit lines. 0389-7381twf (n); IDF200111334; P900527; YCCHEN.ptd page 12

Claims (1)

552681 VI. Application Patent Scope 1. A method for manufacturing a phase change memory suitable for a semiconductor substrate, including the following steps: ι forming an N + stupid crystal layer on the semiconductor substrate; forming an N + epitaxial layer on the semiconductor substrate n- epitaxial layer; forming a first-shallow 'trench isolation structure in the N + epitaxial layer and the N- epitaxial layer to isolate a predetermined word line region; A second shallow trench isolation structure to isolate a predetermined P + doped region; An insulating layer is formed on the N-worm crystal layer; the insulating layer is defined to form a first opening and an N + doping is performed on the N- epitaxial layer through the first opening to form an electrical connection to the epitaxial layer. N + doped region of the crystal layer; define the insulating layer to form a second opening through the second opening and perform a p + doping on the N-epitaxial layer to form a p + doping through the second opening A contact plug is formed in each of the A-th opening and the second opening; and an electrode having an upper electrode, a phase change layer, and a lower electrode is formed on each of the contact plugs. 2. The method for manufacturing a phase change memory according to item 丨 in the scope of the patent application, wherein the thickness of the N + stupid crystal layer is 400 to 60 Å. 3. The method for manufacturing a phase change memory as described in item 1 of the Shenjing patent range, wherein the thickness of the N-epitaxial layer is 800 to 12,000 Angstroms. 4. The method for manufacturing a phase change memory as described in item 1 of the scope of the patent application, wherein the first shallow trench isolation structure is formed on the pallite layer 552681 6. Scope of patent application; a " — and the N + epitaxial layer. 5. The method for manufacturing a phase change memory as described in item 1 of the scope of patent application, wherein the first shallow trench isolation structure is formed by performing dry or thirst etching. ^ 6 The method for manufacturing a phase-change memory slave as described in item 1 of the scope of the patent application, wherein the second shallow trench isolation structure is formed by performing a dry process or an etching process. ^ 7. The method for manufacturing a phase change memory as described in item 1 of the scope of the patent application, wherein 'the N + doping is performed by arsenic or phosphorus ion implantation. 8. The method for manufacturing a phase change memory as described in item 丨 of the patent application scope, wherein the concentration of the N + doping is 1015 to 2 X 10u atoms / cm2 and the energy is 10 to 30 keV . 9. The method for manufacturing a phase change memory according to item 1 of the scope of patent application, wherein the P + doping is performed by implanting boron ions. I 0 · The method for manufacturing a phase change memory as described in item 1 of the scope of patent application, wherein the concentration of the N + doping is 1015 to 1 X 1016 atoms / cm2 and the energy is 1 to 3 keV. II · Method for manufacturing phase change memory as described in item 1 of the scope of patent application 'wherein' the insulating layer is tetra-ethyl-ortho-silicate (TEOS) 〇1 2 · as patent application The method for manufacturing a phase change memory according to the first item, wherein the thickness of the insulating layer is 2000 to 3000 Angstroms. 1 3 · — a phase change memory, including: a semiconductor substrate; 0389-7381twf (n); IDF200111334; P900527; YOCHEN.ptd page 14 552681 VI. Patent application scope N + stupid crystal layer 'is formed on the semiconductor substrate; stupid crystal layer is formed on the N + epitaxial layer; A first shallow trench isolation structure formed in the N + epitaxial layer and the N- epitaxial layer to isolate a predetermined word line region; a P + doped region formed in the N_ epitaxial layer; A second shallow trench isolation structure formed in the N- epitaxial layer to isolate the P + doped region; an N + doped region formed in the N_ epitaxial layer and electrically connected to the N + epitaxial layer Crystal layer Contact plugs are formed on the N + doped region and P + doped region, respectively; and electrodes are formed on the contact plugs, respectively, and have an upper electrode, a phase change layer, and a lower electrode. 14. The phase change memory according to item 13 of the scope of the patent application, wherein the thickness of the N + epitaxial layer is 400 to 600 Angstroms. 15. The phase change memory as described in item 3 of the patent application scope, wherein the thickness of the N-epitaxial layer is 800 to 12,000 Angstroms. 16. The phase change memory as described in item 13 of the scope of the patent application, wherein the first shallow trench isolation structure is formed in the N-stupid crystal layer and the N + insect layer. 1 7. The phase change memory according to item 13 of the scope of the patent application, wherein the first shallow trench isolation structure is formed by performing dry or wet etching. 1 8 · The phase change memory described in item 13 of the scope of patent application ’ 552681 6. In the scope of patent application, the second shallow trench isolation structure is formed by dry or wet etching. 19. The phase change memory according to item 13 of the scope of the patent application, wherein the N + epitaxial layer is formed by a selective epitaxy method. 20. The phase change record as described in item 13 of the scope of patent application: hidden body, in which the N-epitaxial layer is formed by a selective epitaxial method. 0389-73811wf (η); IDF200111334; P900527; YCCHEN.ptd page 16