CN1259762A - 增强无机介质与铜的粘附性的等离子体处理 - Google Patents

增强无机介质与铜的粘附性的等离子体处理 Download PDF

Info

Publication number
CN1259762A
CN1259762A CN99126150A CN99126150A CN1259762A CN 1259762 A CN1259762 A CN 1259762A CN 99126150 A CN99126150 A CN 99126150A CN 99126150 A CN99126150 A CN 99126150A CN 1259762 A CN1259762 A CN 1259762A
Authority
CN
China
Prior art keywords
copper
method described
plasma
inorganic barrier
barrier film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN99126150A
Other languages
English (en)
Other versions
CN1134049C (zh
Inventor
P·D·阿涅洛
L·P·布赫瓦特
J·胡梅尔
B·卢瑟
A·K·斯塔帕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1259762A publication Critical patent/CN1259762A/zh
Application granted granted Critical
Publication of CN1134049C publication Critical patent/CN1134049C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明采用还原性等离子体处理步骤来增强其后被淀积的无机阻挡膜与存在于诸如双重镶嵌结构的半导体互连结构中的铜线或通路的粘附性。

Description

增强无机介质与铜的粘附性的等离子体处理
本发明涉及互连半导体结构，特别是涉及一种改善这种互连结构的诸如Si3N4的无机阻挡膜与铜线或通路的粘附性的方法。在本文中，该术语“互连结构”用得很多，它包括包含铜互连金属的任何半导体结构。因此，本发明可应用于镶嵌结构(单个和双重的)、存储单元电容器和其它用于逻辑电路的布线应用、存储器和输入/输出应用。
在半导体工业中，已将铝和铝合金用作传统的互连金属。尽管在过去铝基金属一直是被选作金属互连的材料，但目前人们关注的是，在半导体器件的电路密度和速度增加的情况下铝是否能满足所需要的要求。由于这种日益增长的关注，已研究了其它材料来作为铝基金属的可能的替代物。一种具有较大优点的、目前正在考虑作为铝金属的可能的替代物是铜。这是因为，除了铜的电阻率较低外，铜与铝相比，它对于电子迁移(electromigration)失效的敏感性较低。
尽管铜有上述优点，但铜容易在后续的工艺步骤中扩散到周围的介质材料中。为了抑制铜的扩散，往往用一层保护性阻挡层来覆盖铜互连结构。一种覆盖方法涉及沿铜互连结构的侧壁和底部使用纯的或合金形态的钽或钛的导电性保护层。为了覆盖铜互连结构的上表面，一般使用诸如氮化硅、Si3N4的介质材料。
由于在铜淀积后需要低温工艺，故在低于450℃的温度下淀积氮化硅层。因此，氮化硅淀积一般是使用等离子增强化学气相淀积(PECVD)或高密度等离子化学气相淀积(HDPCVD)来进行的，其中，淀积温度一般在约200℃至约500℃的范围内。
PECVD和HDPCVD氮化硅已用于半导体器件制造的许多其它的应用中。但是，在对于铜互连结构使用氮化硅顶盖的情况下，常规的PECVD或HDPCVD氮化硅产生可靠性的问题。特别是，使用常规的PECVD或HDPCVD淀积的氮化硅膜一般显示出较差的与铜表面的粘附性。例如，一些氮化膜发生剥离并在已构图的铜线上形成气泡，特别是在后续的介质淀积、金属化和化学机械抛光的工艺中。
这些结果表示在实际的制造工艺中氮化硅怎样能粘附于铜上。附加的绝缘层在被淀积到铜金属上后，一般将淀积在氮化硅膜上。但是，后续的绝缘层在氮化膜上的淀积将产生应力，该应力将使氮化硅膜从铜表面剥离下来。该剥离导致下述几种灾难性的失效机构，其中包括：金属间介质的翘起、铜线的翘起和铜从未覆盖的铜线的扩散。一般在双镶嵌工艺中看到这种结果，其中，一般在铜化学机械抛光(CMP)时发生氮化硅RIE中止层的剥离。
现有技术的氮化硅与铜的粘附性需要通过使铜与硅反应来对铜表面进行硅化。该现有技术的方法存在两个缺点：由于硅与铜的反应并扩散进铜而导致铜薄层电阻的增加，由于不完全的或部分的硅化铜的形成导致临界性的氮化物与铜的粘附性。
鉴于已提到的现有技术的铜互连结构的缺点，很需要发展一种新的利于无机阻挡膜与存在于互连半导体结构上的铜表面的粘附性的工艺。
本发明的一个目的在于提供一种改善被淀积的无机阻挡膜与互连结构的铜表面的粘附性的方法。
本发明的另一个目的在于提供这样一种方法，使用该方法在后续的互连工艺步骤中被淀积的无机阻挡膜不会从互连结构的铜表面剥离下来。
本发明的又一个目的在于提供这样一种方法，该方法能被用于双镶嵌工艺，以改善Si3N4刻蚀中止层与铜布线或铜通路的粘附性。
通过采用包括在铜互连结构上形成无机阻挡膜之前将互连半导体结构的铜层暴露于还原性等离子体中的方法，可在本发明中实现这些和其它的目的和优点。更具体地说，本发明的改善被淀积的无机阻挡膜与互连结构的铜表面的粘附性的方法包括下述步骤：
(a)将至少包含一层铜的互连半导体结构暴露于还原性等离子体中；以及
(b)在已被暴露于所述等离子体的铜互连结构上形成无机阻挡膜。
按照本发明的方法，该暴露步骤、步骤(a)在下述的等离子体中进行，该等离子体包括至少一种从由H2、N2、NH3、诸如He、Ne、Ar、Kr、和Xe的稀有气体及其混合物组成的一组中选出的非氧化性气体。要注意，氧化性气氛被排除在本发明之外，这是因为，这样的气氛会使存在于互连结构中的铜氧化并削弱在铜界面处的氮化物的接合。
在本发明中考虑的合适的互连结构包括，但不限于：存储单元电容器，其中包括平板电容器、冠状电容器、层叠电容器和其它类似的电容器；镶嵌结构，其中包括单个的和双重的；包含多个通路和金属线的多重布线层；以及其它类似的互连结构。
本发明的唯一的图是典型的双重镶嵌结构的剖面图，该双重镶嵌结构可用于本发明并在淀积无机阻挡层之前暴露于等离子体中。
本发明涉及一种改善在互连半导体结构的铜表面上的被淀积的无机阻挡膜的粘附性的方法，以下，将参照附于本发明书之后的唯一的图详细地描述本发明。要强调的是，尽管本发明只说明双重镶嵌结构，但它适用于所有包含铜金属并使用诸如SiC、Si3N4的被淀积的无机阻挡膜作为保护阻挡层或作为刻蚀中止层的互连半导体结构。
参照本申请书中的唯一的图，该唯一的图示出典型的经本发明的方法处理的双重镶嵌结构，具体地说，该双重镶嵌结构包括下互连层10和上互连层12。各层包括通路区14和金属线或布线区16。下互连层10包括具有其中被铜20充填的开口或槽的介质18。在下互连层10的顶部是上互连层12，该上互连层12包括介质22，其槽区将下互连层的铜布线暴露出来。上互连层12的该槽区被铜20充填。在各个互连层之间是起到RIE中止层作用、保护性阻挡层作用或起两个作用的无机阻挡层24。
在图中示出的双重镶嵌结构是利用本领域的专业人员熟知的常规的镶嵌工艺步骤来制造的。其不同点是在形成阻挡层24之前将互连结构暴露于本发明的方法的等离子体中，以下将详细地描述该方法。
介质层18和22可以是相同的或不同的绝缘性无机或有机材料。合适的介质包括，但不限于：SiO2、氟化的SiO2、Si3N4、聚酰亚胺、金刚石、类似于金刚石的碳、硅聚合物、paralyne聚合物、经氟化的类似于金刚石的碳和其它类似的介质化合物。在这些介质材料中，层18和22最好由SiO2构成。该介质层可以被掺杂或不被掺杂。当掺杂时，该掺杂剂可以是硼、氟、磷、重氢(deutrium)、硅、锗或另一种类似的掺杂剂。
阻挡层24是无机材料，该无机材料对于通路起到RIE中止层的作用或在作为结构的最外层存在时起到保护性阻挡层的作用。作为阻挡层24时合适的材料包括，但不限于：SiC、Si3N4、加氢的Si3N4和加氢的SiC。在这些材料中，最好在本发明中使用Si3N4或SiC的加氢的形态作为阻挡层。也可在金属线16与通路14之间插入可选择的RIE中止层(在图中未示出该实施例)。
使用常规的汽相淀积技术来形成阻挡层24，该技术包括，但不限于：化学汽相淀积、低压化学汽相淀积、高压化学汽相淀积、高密度等离子化学汽相淀积、等离子增强化学汽相淀积和其它类似的汽相淀积技术。在这些淀积技术中，对于淀积阻挡层来说，等离子增强化学汽相淀积(PECVD)和高密度等离子化学汽相淀积(HDPCVD)是优选的方法。
再次要强调的是，在图中示出的双重镶嵌结构和任何其它所考虑的铜互连结构是采用本领域的专业人员熟知的技术来制造的。由于这些技术是熟知的，并对于了解本发明不是关键性的，故在此不给出这些方面的详细的讨论。在制造本发明的互连结构和现有技术的互连结构中的唯一的不同是，在淀积无机阻挡层24之前，在下面定义的条件下对铜互连结构进行还原性等离子体的处理。
具体地说，在本发明中使用的还原性等离子体是任何非氧化性的、即不包含氧原子的等离子气氛。可在本发明中被使用的合适的还原性等离子体包括，但不限于：H2、N2、NH3和稀有气体。其中也考虑这些诸如H2和N2的还原性等离子体的两种或多种的组合。在这些还原性等离子体中，H2和NH3是本发明优选的还原性等离子体。
本发明的还原性等离子体暴露步骤是在常规的能产生等离子体气体的等离子淀积装置中进行的。具体地说，本发明的暴露步骤是在从约20℃至约600℃的温度下进行的，处理时间从约1秒至约3600秒。其中也考虑大于3600秒的暴露时间。更具体地说，本发明的暴露步骤是在从约360℃至约400℃的温度下进行的，处理时间从约5秒至约30秒。加热最好在还原性等离子体的存在下进行。
再者，本发明的暴露步骤是以从约1mTorr至约20Torr的气压、以从约50至约10,000瓦的功率和以从约1至10,000sccm的气体流速来进行的。精确的条件依赖于在形成阻挡层中所使用的淀积工艺的类型。例如，当使用高密度等离子化学汽相淀积(HDPCVD)时，本发明的暴露步骤是以从约3至约6mTorr的气压、以从约1500至约3000瓦的功率和以从约10至50sccm的气体流速来进行的。另一方面，当使用等离子增强化学汽相淀积(PECVD)时，本发明的暴露步骤是以从约2至约8Torr的气压、以从约150至约400瓦的功率和以从约100至2000sccm的气体流速来进行的。
要注意，在暴露步骤刚结束后且在不破坏真空的情况下，使用任何上述的淀积技术在其上形成无机阻挡层。本发明的方法，特别是双重镶嵌结构暴露步骤提供这样一种铜互连结构，其中，无机阻挡层具有经改善的与铜线或通路的粘附性，与迄今用现有工艺得到的结构相比，电阻没有增加。这样，由于采用本发明的方法改善了粘附性，故这样得到的铜互连结构不显示出任何剥离的问题，而现有技术的互连结构在后续的诸如化学机械抛光的工艺步骤中通常遇到这样的问题。再有，使用本发明的方法制造的互连结构很少或没有显示出电阻的增加。
给出下述的实施例以说明本发明的范围。因为该实施例只是为了说明性的目的，故本发明不应只限于该实施例。
实施例
为了显示在采用本发明的方法得到的被汽相淀积的无机阻挡层与铜布线之间的被改善的粘附性，在200mm的硅片上进行了一系列的实验，该硅片包含镶嵌在SiO2中的铜线。具体地说，使用标准的镶嵌工艺条件制备了双重镶嵌结构，与标准的镶嵌工艺条件的不同点是，在双重镶嵌结构的铜线上淀积Si3N4之前，采用不同的技术对表面进行处理，这些技术包括：不处理(CE1)；在氧化性等离子气体气氛中的处理(CE2)；或按照本发明的方法在还原性等离子体中的处理。在处理、Si3N4淀积、金属间淀积和双重镶嵌铜线/通路制造后，对各个结构进行光学检验，检验其分层情况。在下面的表1中总结了这些实验的结果，其中，“好”表示基本上很少或没有剥离，即，粘附性得到改善，“差”表示基本上没有粘附性。也观察到，因为氮化物的粘附性得到改善，故铜表面的反射率提高了。
上述的结果清楚地说明通过采用本发明的还原性等离子体暴露步骤可使Si3N4阻挡层与铜的粘附性得到改善。在比较例中(CE1和CE2)，粘附性差，并观察到被淀积的Si3N4膜的剥离。
                                                        表1
   在淀积Si3N4前的处理     气压  高频功率(W)     电极     温度(℃)     Si3N4刚淀积后的粘附性    Si3N4在CMP之后的粘附性     434nm反射率
  未处理(cE1)     -     -     -     -     差     差     0.50
  PECvD NH3     5Torr     300     1cm平行板     250     好 勉强合格至好之间     0.58
  PECVD NH3     5Torr     300     1cm平行板     400     好 勉强合格至好之间 0.58
  PECVD N2     5Torr     300     1cm平行板     250     好     差     未测量
  PECVD N2O+N2(1∶1) (CE2)     5Torr     300     1cm平行板     250     差     差     未测量
  HDPCVD N2+H2     5mTorr     2000     电感性耦合     375     好     好     0.55
  HDPCVD H2     5mTorr     2000     电感性耦合     375     好     好     0.63
  HDPCVD N2     5mTorr     2000     电感性耦合     375     好     好     0.59
  HDPCVD NH3     5mTorr     2000     电感性耦合     375     好     差     0.53
尽管已对本发明就优选实施例进行了特别的说明和描述，但本领域的专业人员应了解，在不偏离本发明的精神和范围的情况下，可在形式和细节方面进行上述的和其它的变更。

Claims (18)

1.一种有利于在铜互连结构上形成的无机阻挡膜的粘附性的方法，其特征在于，所述方法包括下述步骤：
(a)将至少包含一层铜的互连半导体结构暴露于还原性等离子体中；以及
(b)在所述被暴露的铜互连结构上形成无机阻挡膜。
2.如权利要求1中所述的方法，其特征在于：
所述暴露步骤在从由H2、N2、NH3、稀有气体、及其混合物组成的一组中选出的非氧化性等离子体气氛中进行。
3.如权利要求2中所述的方法，其特征在于：
所述非氧化性等离子体气氛是H2。
4.如权利要求2中所述的方法，其特征在于：
所述非氧化性等离子体气氛是NH3。
5.如权利要求1中所述的方法，其特征在于：
所述暴露步骤在从约20℃至约600℃的温度下进行，处理时间从约1秒至约3600秒或更高。
6.如权利要求5中所述的方法，其特征在于：
所述暴露步骤在从约360℃至约400℃的温度下进行，处理时间从约5秒至约30秒。
7.如权利要求1中所述的方法，其特征在于：
所述暴露步骤是以从约1mTorr至约20Torr的气压、以从约50至约10,000瓦的功率和以从约1至10,000sccm的气体流速来进行的。
8.如权利要求1中所述的方法，其特征在于：
所述暴露步骤是用高密度等离子化学汽相淀积法、以从约3至约6mTorr的气压、以从约1500至约3000瓦的功率和以从约10至50sccm的气体流速来进行的。
9.如权利要求1中所述的方法，其特征在于：
所述暴露步骤是用等离子增强化学汽相淀积法、以从约2至约8Torr的气压、以从约150至约400瓦的功率和以从约100至2000sccm的气体流速来进行的。
10.如权利要求1中所述的方法，其特征在于：
所述铜互连结构是电容器结构、包含多个通路和金属线的镶嵌结构或多重布线层。
11.如权利要求10中所述的方法，其特征在于：
所述铜互连结构是包含铜线和通路的单个的或双重的镶嵌结构。
12.如权利要求1中所述的方法，其特征在于：
所述无机阻挡膜是利用从由化学汽相淀积、低压化学汽相淀积、等离子增强化学汽相淀积、高密度等离子化学汽相淀积组成的一组中选出的一种淀积工艺在原处形成的。
13.如权利要求12中所述的方法，其特征在于：
所述无机阻挡膜是由等离子增强化学汽相淀积或高密度等离子化学汽相淀积法在原处形成的。
14.如权利要求1中所述的方法，其特征在于：
所述无机阻挡膜由Si3N4、SiC、加氢的Si3N4或加氢的SiC构成。
15.如权利要求14中所述的方法，其特征在于：
所述无机阻挡膜是加氢的Si3N4或加氢的SiC。
16.如权利要求1中所述的方法，其特征在于：
所述互连结构包括从由SiO2、氟化的SiO2、Si3N4、聚酰亚胺、金刚石、类似于金刚石的碳、硅聚合物、paralyne聚合物和经氟化的类似于金刚石的碳组成的一组中选出的一种介质材料。
17.如权利要求16中所述的方法，其特征在于：
所述介质材料是SiO2。
18.如权利要求1中所述的方法，其特征在于：
在槽内形成所述铜层。
CNB99126150XA 1999-01-04 1999-12-13 增强无机介质与铜的粘附性的等离子体处理 Expired - Lifetime CN1134049C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/225,530 1999-01-04
US09/225,530 US6255217B1 (en) 1999-01-04 1999-01-04 Plasma treatment to enhance inorganic dielectric adhesion to copper
US09/225530 1999-01-04

Publications (2)

Publication Number Publication Date
CN1259762A true CN1259762A (zh) 2000-07-12
CN1134049C CN1134049C (zh) 2004-01-07

Family

ID=22845248

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB99126150XA Expired - Lifetime CN1134049C (zh) 1999-01-04 1999-12-13 增强无机介质与铜的粘附性的等离子体处理

Country Status (7)

Country Link
US (3) US6255217B1 (zh)
JP (1) JP3398635B2 (zh)
KR (1) KR100347743B1 (zh)
CN (1) CN1134049C (zh)
DE (1) DE19963864A1 (zh)
SG (1) SG82045A1 (zh)
TW (1) TW430867B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1295776C (zh) * 2003-12-24 2007-01-17 上海宏力半导体制造有限公司 可分别对双镶嵌工艺的中介窗与沟槽进行表面处理的方法
CN100452385C (zh) * 2004-08-03 2009-01-14 台湾积体电路制造股份有限公司 半导体元件及其制造方法
CN100464417C (zh) * 2002-05-08 2009-02-25 日本电气株式会社 具有含硅铜布线层的半导体器件及其制造方法

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
JP2001160558A (ja) * 1999-12-02 2001-06-12 Nec Corp 半導体装置の製造方法及び製造装置
SG125881A1 (en) * 1999-12-03 2006-10-30 Lytle Steven Alan Define via in dual damascene process
US6352938B2 (en) * 1999-12-09 2002-03-05 United Microelectronics Corp. Method of removing photoresist and reducing native oxide in dual damascene copper process
US6420262B1 (en) * 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6376370B1 (en) 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US6492267B1 (en) * 2000-02-11 2002-12-10 Micron Technology, Inc. Low temperature nitride used as Cu barrier layer
JP2001298028A (ja) * 2000-04-17 2001-10-26 Tokyo Electron Ltd 半導体デバイス製造方法
JP3440057B2 (ja) * 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US6846737B1 (en) * 2000-08-15 2005-01-25 Intel Corporation Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials
WO2002029892A2 (en) 2000-10-03 2002-04-11 Broadcom Corporation High-density metal capacitor using dual-damascene copper interconnect
US6348410B1 (en) * 2000-11-02 2002-02-19 Advanced Micro Devices, Inc. Low temperature hillock suppression method in integrated circuit interconnects
DE10059143B4 (de) * 2000-11-29 2006-12-28 Advanced Micro Devices, Inc., Sunnyvale Oberflächenbehandlungs- und Deckschichtverfahren zur Herstellung einer Kupfergrenzfläche in einem Halbleiterbauteil
KR100399909B1 (ko) * 2000-12-29 2003-09-29 주식회사 하이닉스반도체 반도체 소자의 층간 절연막 형성 방법
JP4535629B2 (ja) 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6387775B1 (en) * 2001-04-16 2002-05-14 Taiwan Semiconductor Manufacturing Company Fabrication of MIM capacitor in copper damascene process
JP2003017564A (ja) * 2001-07-04 2003-01-17 Fujitsu Ltd 半導体装置およびその製造方法
US6849389B2 (en) * 2001-07-12 2005-02-01 International Business Machines Corporation Method to prevent pattern collapse in features etched in sulfur dioxide-containing plasmas
US6461914B1 (en) * 2001-08-29 2002-10-08 Motorola, Inc. Process for making a MIM capacitor
DE10150822B4 (de) * 2001-10-15 2007-01-25 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Entfernen oxidierter Bereiche auf einer Grenzfläche einer Metalloberfläche
US6737747B2 (en) * 2002-01-15 2004-05-18 International Business Machines Corporation Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof
US20030134499A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
JP3716218B2 (ja) * 2002-03-06 2005-11-16 富士通株式会社 配線構造及びその形成方法
US6797652B1 (en) * 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US6847077B2 (en) * 2002-06-25 2005-01-25 Agere Systems, Inc. Capacitor for a semiconductor device and method for fabrication therefor
JP3874268B2 (ja) * 2002-07-24 2007-01-31 Ｔｄｋ株式会社 パターン化薄膜およびその形成方法
US6831008B2 (en) * 2002-09-30 2004-12-14 Texas Instruments Incorporated Nickel silicide—silicon nitride adhesion through surface passivation
CN100352036C (zh) * 2002-10-17 2007-11-28 株式会社瑞萨科技 半导体器件及其制造方法
JP4606713B2 (ja) * 2002-10-17 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR20040051304A (ko) * 2002-12-12 2004-06-18 주식회사 하이닉스반도체 반도체 소자의 베리어 절연막 형성방법 및 금속 배선형성방법
KR100483290B1 (ko) * 2002-12-14 2005-04-15 동부아남반도체 주식회사 반도체 소자의 제조 방법
KR100482180B1 (ko) * 2002-12-16 2005-04-14 동부아남반도체 주식회사 반도체 소자 제조방법
CN100399520C (zh) * 2002-12-26 2008-07-02 富士通株式会社 具有多层配线结构的半导体装置及其制造方法
US20040124420A1 (en) * 2002-12-31 2004-07-01 Lin Simon S.H. Etch stop layer
JP4454242B2 (ja) * 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
DE10335099B4 (de) * 2003-07-31 2006-06-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Verbessern der Dickengleichförmigkeit von Siliziumnitridschichten für mehrere Halbleiterscheiben
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
DE10345453B4 (de) * 2003-09-30 2009-08-20 Infineon Technologies Ag Verfahren zum Herstellen eines optischen Sensors mit einer integrierten Schichtstapel-Anordnung
US7094705B2 (en) * 2004-01-20 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-step plasma treatment method to improve CU interconnect electrical performance
US7223692B2 (en) * 2004-04-30 2007-05-29 Taiwan Semiconductor Manufacturing Co., Ltd Multi-level semiconductor device with capping layer for improved adhesion
US20060046502A1 (en) * 2004-08-27 2006-03-02 Ngo Minh V Deposition of hard-mask with minimized hillocks and bubbles
US7138717B2 (en) * 2004-12-01 2006-11-21 International Business Machines Corporation HDP-based ILD capping layer
US7192855B2 (en) * 2005-04-15 2007-03-20 Freescale Semiconductor, Inc. PECVD nitride film
WO2007034377A2 (en) * 2005-09-19 2007-03-29 Koninklijke Philips Electronics N.V. Composite layer having improved adhesion, and fluid focus lens incorporating same
JP5060037B2 (ja) 2005-10-07 2012-10-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2007180420A (ja) 2005-12-28 2007-07-12 Fujitsu Ltd 半導体装置の製造方法及び磁気ヘッドの製造方法
US7691736B2 (en) * 2006-02-10 2010-04-06 Infineon Technologies Ag Minimizing low-k dielectric damage during plasma processing
US7604871B2 (en) * 2006-06-07 2009-10-20 Honeywell International Inc. Electrical components including abrasive powder coatings for inhibiting tin whisker growth
US7642653B2 (en) * 2006-10-24 2010-01-05 Denso Corporation Semiconductor device, wiring of semiconductor device, and method of forming wiring
US20080258304A1 (en) * 2007-04-23 2008-10-23 Denso Corporation Semiconductor device having multiple wiring layers
US7709400B2 (en) * 2007-05-08 2010-05-04 Lam Research Corporation Thermal methods for cleaning post-CMP wafers
KR101315880B1 (ko) 2008-07-23 2013-10-08 삼성전자주식회사 금속 배선 구조물 및 그 제조 방법
JP2009088548A (ja) * 2008-12-01 2009-04-23 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US8039920B1 (en) 2010-11-17 2011-10-18 Intel Corporation Methods for forming planarized hermetic barrier layers and structures formed thereby
US8758638B2 (en) * 2011-05-10 2014-06-24 Applied Materials, Inc. Copper oxide removal techniques
JP2013089650A (ja) * 2011-10-14 2013-05-13 Mitsubishi Heavy Ind Ltd プラズマ処理方法
WO2013171235A1 (en) * 2012-05-14 2013-11-21 Imec Method for manufacturing germanide interconnect structures and corresponding interconnect structures
JP6579953B2 (ja) 2012-07-16 2019-09-25 マットソン テクノロジー インコーポレイテッドＭａｔｔｓｏｎ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 純還元性プラズマ中で高アスペクト比のフォトレジストを除去する方法
US9865501B2 (en) * 2013-03-06 2018-01-09 Lam Research Corporation Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
US10443146B2 (en) 2017-03-30 2019-10-15 Lam Research Corporation Monitoring surface oxide on seed layers during electroplating
DE102017212272A1 (de) 2017-07-18 2019-01-24 Meyer Burger (Germany) Gmbh Verfahren zur Erzeugung einer Haft- und Barriereschicht auf einem Substrat und zugehöriges Substrat
US11195748B2 (en) * 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207699A (ja) * 1982-05-28 1983-12-03 株式会社日立製作所 配線回路基板の製造方法
JPS59123226A (ja) 1982-12-28 1984-07-17 Fujitsu Ltd 半導体装置の製造装置
JPH05144811A (ja) 1991-11-22 1993-06-11 Hitachi Ltd 薄膜半導体装置及びその製造方法
EP0551117A2 (en) * 1992-01-08 1993-07-14 Mitsubishi Denki Kabushiki Kaisha Large scale integrated circuit device and thin film forming method and apparatus for the same
CA2089791C (en) * 1992-04-24 1998-11-24 Michael J. Brady Electronic devices having metallurgies containing copper-semiconductor compounds
US5273920A (en) 1992-09-02 1993-12-28 General Electric Company Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
JP3297220B2 (ja) 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
US5447887A (en) 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
US5624868A (en) 1994-04-15 1997-04-29 Micron Technology, Inc. Techniques for improving adhesion of silicon dioxide to titanium
US5818071A (en) 1995-02-02 1998-10-06 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
US5659201A (en) 1995-06-05 1997-08-19 Advanced Micro Devices, Inc. High conductivity interconnection line
US5614765A (en) * 1995-06-07 1997-03-25 Advanced Micro Devices, Inc. Self aligned via dual damascene
US5659868A (en) 1995-12-11 1997-08-19 Xerox Corporation Pressure roll having a flat shaft for use in a heat and pressure fuser apparatus
EP0793271A3 (en) * 1996-02-22 1998-12-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a metal silicide film and method of fabricating the same
US5885896A (en) * 1996-07-08 1999-03-23 Micron Technology, Inc. Using implants to lower anneal temperatures
JP3463979B2 (ja) 1997-07-08 2003-11-05 富士通株式会社 半導体装置の製造方法
US6249055B1 (en) * 1998-02-03 2001-06-19 Advanced Micro Devices, Inc. Self-encapsulated copper metallization
US6111301A (en) * 1998-04-24 2000-08-29 International Business Machines Corporation Interconnection with integrated corrosion stop
JP4044236B2 (ja) * 1999-03-11 2008-02-06 株式会社東芝 半導体装置の製造方法
US20030008493A1 (en) * 2001-07-03 2003-01-09 Shyh-Dar Lee Interconnect structure manufacturing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100464417C (zh) * 2002-05-08 2009-02-25 日本电气株式会社 具有含硅铜布线层的半导体器件及其制造方法
CN1295776C (zh) * 2003-12-24 2007-01-17 上海宏力半导体制造有限公司 可分别对双镶嵌工艺的中介窗与沟槽进行表面处理的方法
CN100452385C (zh) * 2004-08-03 2009-01-14 台湾积体电路制造股份有限公司 半导体元件及其制造方法

Also Published As

Publication number Publication date
JP3398635B2 (ja) 2003-04-21
US6255217B1 (en) 2001-07-03
CN1134049C (zh) 2004-01-07
KR20000052450A (ko) 2000-08-25
US6261951B1 (en) 2001-07-17
TW430867B (en) 2001-04-21
KR100347743B1 (ko) 2002-08-09
SG82045A1 (en) 2001-07-24
DE19963864A1 (de) 2000-08-10
JP2000200832A (ja) 2000-07-18
US6593660B2 (en) 2003-07-15
US20010053591A1 (en) 2001-12-20

Similar Documents

Publication Publication Date Title
CN1134049C (zh) 增强无机介质与铜的粘附性的等离子体处理
CN1518075B (zh) 有机绝缘膜、其制造方法、使用该有机绝缘膜的半导体器件及其制造方法
US8035230B2 (en) Semiconductor device and method for manufacturing same
US6242808B1 (en) Semiconductor device with copper wiring and semiconductor device manufacturing method
US20040004288A1 (en) Semiconductor device and manufacturing method of the same
JP4746829B2 (ja) 半導体装置およびその製造方法
US6958524B2 (en) Insulating layer having graded densification
JP2809196B2 (ja) 半導体装置の製造方法
JP3244058B2 (ja) 半導体装置の製造方法
JP2005527098A (ja) 高アスペクト比の半導体デバイス用のボロンドープ窒化チタン層
JP2002203899A (ja) 銅相互接続構造の形成方法
JPH0922907A (ja) 埋め込み導電層の形成方法
JP2000174019A (ja) 半導体装置及びその製造方法
JP2001053151A (ja) 半導体集積回路装置およびその製造方法
JPH10247686A (ja) 多層配線形成法
US20040222525A1 (en) Advanced VLSI metallization
US7067917B2 (en) Gradient barrier layer for copper back-end-of-line technology
JP3164152B2 (ja) 半導体装置の製造方法
TWI321826B (en) Structure for improving interlevel conductor connections
JP3269490B2 (ja) 半導体集積回路装置およびその製造方法
JP2002134610A (ja) 半導体装置の製造方法
US20040155348A1 (en) Barrier structure for copper metallization and method for the manufacture thereof
TW451412B (en) Manufacturing method for metal interconnection preventing the formation of void
JP2003124216A (ja) 配線用シード膜および半導体装置の配線方法
JP2002141303A (ja) 向上した濡れ性、障壁効率、デバイス信頼性を有する拡散障壁材料におけるＳｉの現場同時堆積

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20040107

CX01 Expiry of patent term