TW451412B - Manufacturing method for metal interconnection preventing the formation of void - Google Patents
Manufacturing method for metal interconnection preventing the formation of void Download PDFInfo
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¢51412 五、發明說明(1) 發明領域: 本發明與一種半導體製程中之金屬連線(inter_ connection)製程有關’特別是一種在進行高密度電漿沉 積(high density plasma; HDP)程序製作金屬間介電層 (IMD)時,有效降低空洞形成機率之銘金屬連線製程。 發明背景: 在超大型積體電路 合局密度積體電路之設計 微米以下。並且由於元件 半導體製程時,往往遭遇 程度亦不斷提高。一般而 定區域中’形成數以百萬 件的電子連結結構,以& 電路的性能’除了依靠所 要無數精密細微的金屬内 電子號。特別是隨著積 積體電路設計,已朝著多¢ 51412 V. Description of the invention (1) Field of the invention: The present invention relates to an inter_connection process in a semiconductor process, and particularly to a process in which metal is produced by a high density plasma (HDP) process. In the case of an inter-dielectric layer (IMD), the metal connection process can effectively reduce the probability of void formation. Background of the invention: The design of integrated density integrated circuits in very large integrated circuits is less than micron. And because of the semiconductor manufacturing process, the level of encounters is constantly increasing. In general, millions of pieces of electronic connection structures are formed in a certain area, and the performance of the circuit is in addition to relying on the innumerable precise and delicate metal electronic numbers. Especially with the design of integrated circuit,
Q 隨考半導體工業持續的進展 (ULSI)的開發與設計中,為了符 趨勢’各式元件之尺寸皆降至次 不斷的縮小,也導致在進行相關 了前所未有之難題,且製程複雜 言’積體電路包括在晶圓上某特 計的元件’以及用來連接這^元 執行所需之特定功能。因此&體 含元件之性能及可靠度外,更需 連線,以便能有效傳遞元件間: 體電路尺寸持續的縮小,當前的 重金屬内連線發屐。 極 此外’對傳統的半導體製 佳的導電性與便宜的造價 程而言,鋁金屬材料由於其 ’並且可任意的進行沉積與蚀Q In the development and design of the continuous progress of the semiconductor industry (ULSI), in order to comply with the trend, 'the size of various components has been reduced to a continuous reduction, which has also led to unprecedented difficulties related to the process, and the process is complicated. The body circuit includes a special component on the wafer 'and the specific function used to connect this element to perform. Therefore, in addition to the performance and reliability of the body components, wiring is needed in order to effectively transfer between components: the size of the body circuit continues to shrink, and the current heavy metal interconnects have been developed. In addition, for the good conductivity and cheap manufacturing cost of traditional semiconductors, aluminum metal materials can be deposited and etched arbitrarily due to their
第4頁 451412 五、發明說明(2) 刻’是以往往成為業界優先考慮的導線材料。然而,隨著 半導體元件的積集度不斷上昇,使用金屬鋁來作為連線接 觸結構,亦遭遇了極多的困難《例如,在高溫環境中,銘 原子容易與矽底材發生交互擴散(inter_diffusi〇n),而 產生尖峰現象”,並導致鋁線接觸不良。此外,當鋁線的 尺寸隨著元件縮小時,由於"電致遷移”所導致的鋁原子移 動’很容易使所製作的鋁連線結構發生短路。 請參照第一圖’該圖顯示了鋁金屬連線之製作方法。 其中,首先提供一半導體底材10,且在半導體底材Η上, 具有所需之各種功能層與各式元件。接著,形成鋁金屬層 1 2於半導體底材1 〇上,並使用微影蝕刻製程定義連線圖案 於其上。然後,再形成金屬間介電層14以覆蓋於半導體^ 材10與鋁金屬層12上,並填充於鋁金屬層12間的空隙丨^ -中。 一般而言,在沉積金屬間介電層14時,為了兼顧良 的填縫能力(good gap fill capability)與較佳的防 (passivation)效果,往往是使用高密度電毁(high ° density PlaSina;HDP)沉積程序’來製作材質 屬間介電層U…是當半導體元件的尺寸質不較斷敏二 如第一圖中所示的空隙16將具有更精細的維度, :’ 化學氣相沉法(CVD),並無法有效的沉積姑知 至這些空隙16中。因此,當積體電路製程//降至=5料 4 514 1 ^ 五、發明說明(3) --- m以下後,往往需使用HDP沉積程序,來進行金屬間介電層 1 4的製作。 值付注意的是,局密度電漿沉積程序是對半導體底材 10持續進行藏擊(sputtering)與沉積(dep〇siting)來製作 金屬間介電層14。其中,藉著濺擊效應可將製程中造成填 洞障礙的聚合物加以清除,而確保可沉積介電材料至空隙 16中。但是當使用過強的錢擊效應時,往往會造成金屬層 12產生切角(clipping)。即使在較輕微的濺擊效應下,亦 會造成金屬層12產生裂缝(seam),而導致金屬連線〗2的結 構應力(stress)失去均衡。特別是當所製作的金屬連線^ 有高縱橫比(aspect ratio)時’為了使金屬間介電層14保 持良好的填洞能力’將造成金屬連線〗2的應力失衡情況更 加嚴重。並導致金屬連線12產生如第一圖中所示之空洞 (v 〇 i d)缺陷 1 8。 請參照第二圖,此圖顯示使用HDP程序進行金屬間介電 層沉積後,於鋁金屬連線中產生空洞之情況。其中,含有 銅原子的鋁金屬連線,分別具有4K、6K、8K與9K埃的厚 度’且於整個半導體底材上,金屬連線圖案的密度超過 35%_。如此一來’當紹金屬連線的截距由減少至〇 6 β m ’其縱橫比將呈現上昇的趨勢。另外,在圖中之"〇 „顯 示在使用HDP程序沉積金屬間介電層後,鋁金屬連線中並 未發生空洞缺陷;相對的,圖中符號"X"則表示所製作的銘Page 4 451412 V. Description of the invention (2) Carving is a wire material that often becomes the industry's priority. However, with the increasing accumulation of semiconductor components, the use of metal aluminum as the contact structure of the connection has also encountered many difficulties. For example, in high-temperature environments, Ming atom is easy to interact with silicon substrates (inter_diffusi 〇n), resulting in a spike phenomenon ", and lead to poor contact of the aluminum wire. In addition, when the size of the aluminum wire is reduced with the element, the aluminum atom movement caused by " electromigration " Short circuit in the aluminum wiring structure. Please refer to the first figure ', which shows the method of making the aluminum metal connection. Among them, a semiconductor substrate 10 is first provided, and on the semiconductor substrate 具有, it has various functional layers and various elements required. Next, an aluminum metal layer 12 is formed on the semiconductor substrate 10, and a lithographic etching process is used to define a wiring pattern thereon. Then, an intermetal dielectric layer 14 is formed to cover the semiconductor material 10 and the aluminum metal layer 12 and fill the gap between the aluminum metal layer 12 and the metal layer 12. In general, when depositing the intermetal dielectric layer 14, in order to take into account good gap fill capability and better passivation effect, high density electrical destruction (High ° density PlaSina) is often used; HDP) deposition process to make the intermetallic dielectric layer U ... is when the size and quality of the semiconductor element is not less sensitive. The gap 16 shown in the first figure will have a finer dimension,: 'Chemical vapor deposition The method (CVD) cannot effectively deposit into these voids 16. Therefore, when the integrated circuit manufacturing process // falls to 5 materials 4 514 1 ^ V. Description of the invention (3) --- m below, often need to use the HDP deposition process to make the intermetal dielectric layer 14 . It is worth noting that the local density plasma deposition process is to continuously perform sputtering and depotting on the semiconductor substrate 10 to produce the intermetal dielectric layer 14. Among them, the polymer that causes the hole filling obstacle during the process can be removed by the splash effect, so as to ensure that a dielectric material can be deposited into the void 16. However, when an excessively strong coin strike effect is used, the metal layer 12 often causes clipping. Even under a slight splashing effect, the metal layer 12 will cause a crack (seam), and the structural stress of the metal wiring 2 will be unbalanced. Especially when the metal connection ^ has a high aspect ratio, 'in order to maintain a good hole filling ability of the intermetal dielectric layer 14', the stress imbalance of the metal connection 2 will become more serious. As a result, the metal wiring 12 has a void (v o i d) defect 18 as shown in the first figure. Please refer to the second figure. This figure shows the formation of voids in the aluminum metal connection after HDP process is used to deposit the intermetal dielectric layer. Among them, the aluminum metal wires containing copper atoms have thicknesses of 4K, 6K, 8K, and 9K, respectively, and the density of the metal wire patterns on the entire semiconductor substrate exceeds 35%. As a result, the 'Dangshao metal wire's intercept decreases from 0 to 6 β m', and its aspect ratio will show an upward trend. In addition, "" 〇" in the figure shows that after the HDP process is used to deposit the intermetal dielectric layer, no void defect has occurred in the aluminum-metal connection. In contrast, the symbol "X" in the figure indicates the inscription
15m 1 2 五、發明說明(4) 金屬連線有空洞缺陷,而不符合良率的要求。因此,根據 第二圖可知,當鋁金屬連線之厚度增加或截距減少時,皆 會導致空洞缺陷的發生11換言之,當金屬連線的縱橫比愈 大時,其發生空洞缺陷的機會亦會增加。 接著,請再參照第三圖,此圖顯示分別使ΑΜΑΤ與 Novellus的HDP機台,來進行金屬間介電層沉積程序,隨 著金屬連線截距的不同,所造成的空洞缺陷情況。其中, 鋁金屬線圖案的密度亦超過35%,而厚度則控制在9K埃。 此時,可發現對AMAT機台而言,當金屬連線截距低於1, 2 # m後’其HDP程序將造成金屬空洞的產生。相對的,在使 用Novell us機台時,即使金屬連線截距低至0· 8 Ajn時,仍 可有效的抑制空洞的產生。值得注意的是,在HDp程序 中’AMAT機台的溫度約控制在左右;而 Novel lus機台的溫度則控制在33〇。〇左右,顯然過高的溫 度亦會促使金屬連線產生空洞。 115m 1 2 V. Description of the invention (4) The metal connection has void defects, which does not meet the requirements for yield. Therefore, according to the second figure, it can be seen that when the thickness of the aluminum metal connection increases or the intercept decreases, it will cause the occurrence of void defects.11 In other words, as the aspect ratio of the metal connection becomes larger, the chance of the occurrence of void defects also increases. Will increase. Next, please refer to the third figure again. This figure shows the HDP machines of AMAT and Novellus to perform the intermetal dielectric layer deposition process, and the void defects caused by the interception of the metal wires. Among them, the density of the aluminum metal wire pattern is more than 35%, and the thickness is controlled at 9K Angstroms. At this time, it can be found that for the AMAT machine, when the intercept of the metal connection is lower than 1, 2 # m, its HDP program will cause the generation of metal voids. In contrast, when using the Novell us machine, even when the intercept of the metal connection is as low as 0.8 Ajn, the generation of voids can be effectively suppressed. It is worth noting that in the HDp program, the temperature of the 'AMAT machine is controlled at about the left and right; the temperature of the Novel lus machine is controlled at 33. It is obvious that excessively high temperatures will also cause voids in metal connections. 1
進積第機 灭租序後,於金屬連線中產生空洞的情形。 屬ΐΐ圖案之比例控制在35%以下,而厚度仍保 m仍盈法VV二發現即使金屬連線的截距上昇至1.6 金層連後Λ 抑制空洞的形成。要特別說明的是’ 愈高時’可提高散熱的效率… °果可知,金屬連線圖案比例低於35%以下After the productive lease sequence, a hole is created in the metal connection. The ratio of the perylene pattern is controlled below 35%, and the thickness remains the same. The method of VV2 finds that even if the intercept of the metal line rises to 1.6, Λ suppresses the formation of voids after gold lamination. It ’s important to note that ‘when it ’s higher,’ the heat dissipation efficiency can be improved ... ° It can be seen that the proportion of metal wiring patterns is less than 35%
五、發明說明(5) 會造成散熱效能唪低,而使得空洞缺陷產生。顯然,當溫 度過高或散熱效能不佳時,皆容易在金屬連線中產生空 洞。 發明目的及概述: 本發明之主要目的在提供一種可降低金屬連線產生空 洞缺陷之相關製程。V. Description of the invention (5) The heat dissipation efficiency will be low, which will cause void defects. Obviously, when the temperature is too high or the heat dissipation performance is not good, it is easy to create holes in the metal connections. OBJECTS AND SUMMARY OF THE INVENTION: The main object of the present invention is to provide a related process which can reduce void defects caused by metal connections.
本發明之另一目的在提供一種在進行高密度電漿沉積 程序中降低形成空洞缺陷於金屬連線内之方法β 一種在半導體底材上製作金屬連線之方法。首先,形 成一黏著層於半導體底材上,且形成鋁金屬層於此黏著層 上。接著,再形成遮蓋層於鋁金屬層上表面,並對鋁金屬 層進行微影製程,以定義連線圖案於金屬層中。接著,對 金屬層進行電漿處理以降低空洞形成機率,其中電藥處理 是在流量約800至1 600 seem之Ν20氣體環境下,以射頻功 率約100至300W,進行約30至90秒所形成。如此,可在此 金屬層表面形成一硬式罩殼而達到提昇金屬層應力均衡之 效果β接著,再進行高密度電漿(HDP)沉積程序,以形成 金屬間介電層(IMD)於半導體底材與金屬層上。 發明詳細說明:Another object of the present invention is to provide a method for reducing the formation of void defects in metal wires during a high-density plasma deposition process. Β A method for making metal wires on a semiconductor substrate. First, an adhesive layer is formed on the semiconductor substrate, and an aluminum metal layer is formed on the adhesive layer. Then, a cover layer is formed on the upper surface of the aluminum metal layer, and a lithography process is performed on the aluminum metal layer to define a connection pattern in the metal layer. Next, plasma treatment is performed on the metal layer to reduce the probability of void formation. The electro-chemical treatment is performed in an N20 gas environment with a flow rate of about 800 to 1 600 seem and a RF power of about 100 to 300 W for about 30 to 90 seconds. . In this way, a hard cover can be formed on the surface of the metal layer to improve the stress balance of the metal layer. Β Then, a high density plasma (HDP) deposition process is performed to form an intermetal dielectric layer (IMD) on the semiconductor substrate. Wood and metal layers. Detailed description of the invention:
第8頁 45ί 4 1 2Page 8 45 ί 4 1 2
五、發明說明(6) 本發明提供一個新方法,用來形成金屬連線於半導體 底材上。其中’藉著在使用微影蝕刻定義金屬線圖案後, 進行一包含Νζ0氣體之電漿處理程序,可有效的提高金屬’ 詹之應.力均衡。從而達到降低在後續進行高密度電货广 程序(HDP)時,金屬層中發生空洞之機會β有關本^明· 詳細說明如下所述、 請參照第五圖,首先提供一具<100>晶向之單晶矽底 1〇〇。一般而言,其它種類之半導體材料,諸如砂化嫁- (gallium arsenide)、鍺(germanium)或是位於絕緣層上 之石夕底材(silicon on insulator,SOI)皆可作為半導體 f材使用。另外’由於半導體底材表面的特性對本發明而 言’並不會造成特別的影晌’是以其晶向亦可選擇〈1丨〇> 或 < 111 ;>。 接著,可在半導體底材100上製作積體電路所需之各式 主動心牛、被動元件、與週圍電路等等(未顯示於圖中)。 ϊΐί 進行後續程序前,此半導體底材1〇〇表面上, 已具有各式所需的功能層與材料層。接著,形成一黏著層 (glue layer)102於半導體底材1〇〇上,以提昇 製 i 呂金屬連線與上述功能層'材料層間之附著能力:一般而 吕,此黏著層102可由氮化鈦(TiN)或鈦(η)層來 外’此黏著廣102並可產生阻障作用,而防止後續形成之 l5141 3 ---------- 五、發明說明(γ) t金屬連線與半導體底材100間發生擴散現象,而造成尖 效應(spiking effect)。 在車交佳實施例中’可使用氮化反應(N i t r i d a t i ο η)製程 來形成所需之氮化鈦層。首先進行濺鍍程瘁,以沉積一鈦 f於半導體底材1〇〇上表面,再於&或^113的環境中,經由 同屋處理而形成所需的氮化鈦層;此外,也可利用反應性 減鍛程序來形成氮化鈦層。藉著利用電漿離子轟擊鈦金 屬’且通入氩氣與氮氣,以便經轟擊所濺出的鈦原子,可 與經由解離反應(dissociatiori reaction)所形成的氮原 子’反應並形成氮化鈦而沉積於半導體底材丨〇〇表面。 然後’形成金屬層104於黏著層102之上。一般而言, 可藉由熟知之技術,如物理氣相沈積法(PVD)、濺鍍等類 似製程在黏著層1〇2上沈積含銅之鋁金屬,來作為此金屬 層1 0 4。此外其它金屬材料如鈦、鎢、銅、金、鉑或任意 組成的合金等等,亦可用來作為本發明中之金屬層1〇4使 用。在形成金屬層1〇4後’再形成一遮蓋層(cap layer)105於此金屬層1〇4上表面,以防止沾染及避免氧氣 與所沈積金屬層1 04發生作用,而降低了導電性能。其 中,所製作遮蓋層105之材質,亦可選擇上述TiN或Ti材 料。 隨後’請參照第六圖,可對遮蓋層1 05、金屬層1 〇4與5. Description of the invention (6) The present invention provides a new method for forming a metal wire on a semiconductor substrate. ‘By using lithographic etching to define a metal line pattern, a plasma treatment program containing Nζ0 gas is performed to effectively improve the metal’ Zhan Yingying. Force balance. In order to reduce the chance of voids in the metal layer during the subsequent high-density electricity distribution process (HDP), the relevant details are described below, please refer to the fifth figure, first provide a < 100 > Crystal orientation of single crystal silicon substrate 100. Generally speaking, other types of semiconductor materials, such as gallium arsenide, germanium, or silicon on insulator (SOI) on the insulating layer, can be used as semiconductor f materials. In addition, 'due to the characteristics of the surface of the semiconductor substrate to the present invention' does not cause a special influence ', it is possible to select <1 丨 0> or <111; > depending on its crystal orientation. Then, various active cores, passive components, peripheral circuits, and the like required for the integrated circuit can be fabricated on the semiconductor substrate 100 (not shown in the figure). Before carrying out subsequent procedures, the surface of this semiconductor substrate 100 already has various functional layers and material layers required. Next, a glue layer 102 is formed on the semiconductor substrate 100 to improve the adhesion between the metal wiring and the functional layer 'material layer: Generally, the adhesive layer 102 can be nitrided. Titanium (TiN) or titanium (η) layers come from outside. This adhesion can be 102 and can have a barrier effect, and prevent the subsequent formation of l5141 3 ---------- V. Description of the invention (γ) t metal A diffusion phenomenon occurs between the wiring and the semiconductor substrate 100, resulting in a spiking effect. In the preferred embodiment, a nitriding (N i t r i d a t i ο η) process can be used to form the desired titanium nitride layer. First, a sputtering process is performed to deposit a titanium f on the upper surface of the semiconductor substrate 100, and then the same titanium nitride layer is formed through the same room treatment in an & or ^ 113 environment; in addition, Reactive forging procedures can be used to form the titanium nitride layer. By bombarding titanium metal with plasma ions and passing in argon and nitrogen, the titanium atoms splashed by the bombardment can react with nitrogen atoms formed through a dissociatiori reaction and form titanium nitride. Deposited on the surface of the semiconductor substrate. Then, a metal layer 104 is formed on the adhesive layer 102. Generally, a copper-containing aluminum metal can be deposited on the adhesive layer 102 as a metal layer 104 by well-known techniques such as physical vapor deposition (PVD), sputtering and the like. In addition, other metal materials such as titanium, tungsten, copper, gold, platinum, or alloys of any composition can also be used as the metal layer 104 in the present invention. After the metal layer 104 is formed, a cap layer 105 is formed on the upper surface of the metal layer 104 to prevent contamination and prevent oxygen from interacting with the deposited metal layer 104, thereby reducing the conductivity. . Among them, the material of the cover layer 105 can also be selected from the aforementioned TiN or Ti materials. Subsequently, please refer to the sixth figure. The covering layer 105, the metal layer 104, and
第10頁 45】412 五、發明說明(8) 黏著層102 ’進行微影製程以定義連線圖案於其中a —般 而言,可使用諸如反應離子蝕刻術之乾蝕刻法,來對遮蓋 層105、金屬層104與黏著層1〇2進行蝕刻程序,而定義出 連線圖案。其中,用來定義鋁金屬連線圖案與蝕刻氮化鈦 層之银刻劑,可選擇SiCl4、BC13、BB.r3、CC14等氣體與Ci2 加以混合。至於’當黏著層1 〇 2是由鈦層所構成時,則可 選擇C2C12F4、CF4、CC1F3、CBrF3 + He + 〇2 來作為巍刻配方。Page 10 45] 412 5. Description of the invention (8) Adhesive layer 102 'is subjected to a lithography process to define a wiring pattern in which a. Generally, a dry etching method such as reactive ion etching can be used to cover the cover layer. 105. The metal layer 104 and the adhesive layer 102 are etched to define a connection pattern. Among them, the silver etchant used to define the aluminum metal connection pattern and the titanium nitride layer can be mixed with Ci2, SiCl4, BC13, BB.r3, CC14 and other gases. As for 'when the adhesive layer 102 is composed of a titanium layer, C2C12F4, CF4, CC1F3, CBrF3 + He + 〇2 can be selected as the formula for the engraving.
接著’可對此金屬層104進行電漿處理(Piasma treatment)106以降低空洞形成機率。其中,此電漿處理 106是在流量約800至1 600 seem之乂0氣體環境下,以射頻 功率約100至300W,進行約30至90秒所形成。如此,當所 使用之金屬層104為Is金屬材料時’則可形成厚度約1〇〇至 300埃的氧化鋁層108於金屬層104外表面,而降低金屬層 104中的空洞开;^成機率。一般而言,由於氧化紹層丨,可 均勻的包覆於金屬層104外表面’是以可產生硬式罩殼的 保護效果。如此一來,在進行HDP沉積程序時,此氧化鋁 層108可保護其下的金屬層1〇4,並維持其應力均衡’而有 效的避免由於應力不均’所導致發生空洞缺陷之問題。在 較佳實施例中’可調整射頻功率約20 0w,且進行約45秒的 電漿處理,而形成所需的氧化鋁層1 〇 8 ^此外,除了通入 %〇氣體進行電漿處理外,也可同時通入流量約8〇〇至16〇〇 seem之〇2氣體,而降低金屬層1〇4發生空洞之機會。Next, the metal layer 104 may be subjected to a Piasma treatment 106 to reduce the probability of void formation. Among them, the plasma treatment 106 is formed in a 乂 0 gas environment with a flow rate of about 800 to 1 600 seem, and is performed at a radio frequency power of about 100 to 300 W for about 30 to 90 seconds. In this way, when the metal layer 104 used is an Is metal material, an aluminum oxide layer 108 having a thickness of about 100 to 300 angstroms can be formed on the outer surface of the metal layer 104, thereby reducing the void opening in the metal layer 104; Chance. Generally speaking, due to the oxide layer 丨, the outer surface of the metal layer 104 can be uniformly covered, so that a protective effect of a hard cover can be produced. In this way, during the HDP deposition process, the alumina layer 108 can protect the underlying metal layer 104 and maintain its stress balance ', thereby effectively avoiding the problem of void defects caused by uneven stress'. In the preferred embodiment, 'the RF power can be adjusted to about 200 W, and the plasma treatment is performed for about 45 seconds to form the required alumina layer 108. In addition, in addition to the plasma treatment with% 0 gas It is also possible to simultaneously pass in a gas with a flow rate of about 8000 to 1600 seem, and reduce the chance of voids in the metal layer 104.
^51412 五、發明說明(9) 隨後,請參照第七圖,進行高密度電漿(HDp)沉積程 序’以形成金屬間介電層(IMD)llO於半導體底材1〇〇、勒 著層102與金屬層1〇4上,且填充於金屬層104間之空隙 中。在較佳實施例中,所使用的射頻偏壓(bias_RF)約控 制在2 5 0 0 W以下’而通入的η e氣體流量,則控制在9托耳以 上°如此’藉著提高H e氣流量’可使溫度維持在較低的情 況,而有益於防止空洞的產生。 請參照第八圖,此圖顯示使用本發明方法在進行高密 度電漿沉積程序前,先通入%〇氣體對半導體底材進行電 聚處理之結果。其中,鋁金屬連線之厚度約9K埃,而截距 則控制在0. 8 # m至1. 6 y m間。如此,由圖中可知,不論是 使用AMAT或Novellus機台,皆可有效的避免空洞產生於鋁 金屬連線之中。 本發明雖以一較佳實例闡明如上,然其並非用以限定 本發明精神與發明實體,僅止於此一實施例爾β對熟悉此 領域技藝者,在不脫離本發明之精神與範圍内所作之修 ? ’均應包含在下述之申請專利範圍内。^ 51412 V. Description of the invention (9) Subsequently, referring to the seventh figure, a high-density plasma (HDp) deposition process is performed to form an intermetal dielectric layer (IMD) 110 on a semiconductor substrate 100, and a cladding layer 102 and the metal layer 104 are filled in the gap between the metal layer 104. In the preferred embodiment, the radio frequency bias (bias_RF) used is controlled below about 2500 W, and the flow of η e gas is controlled above 9 Torr. Thus, by increasing He Airflow 'can keep the temperature low, which is beneficial to prevent the generation of voids. Please refer to the eighth figure. This figure shows the result of conducting the polymerization treatment on the semiconductor substrate by passing in a gas of% 0 before performing the high-density plasma deposition process using the method of the present invention. Among them, the thickness of the aluminum metal connection is about 9K Angstroms, and the intercept is controlled between 0.8 # m to 1.6 y m. In this way, it can be seen from the figure that no matter whether the AMAT or Novellus machine is used, voids can be effectively avoided in the aluminum metal connection. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. For those skilled in the art, it is within the spirit and scope of the present invention. The repairs made shall be included in the scope of patent application described below.
第12頁 451412 囷式簡單說明 藉由以下詳細之描述結合所附圖示,將可輕易,的了 上述内容及此項發明之諸多優點,其中: 第一亂為半導體晶.片之截面圖,顯示根據傳統技術在 +導體底材上形成鋁金屬連線所產生之空洞缺陷. 金Λ二Λ為結金屬連線其空洞缺陷之數據圖、,顯示隨著 厚度上昇與截距下而使空洞缺陷產生機率增 第三圖為鋁金屬連線其空洞缺陷之數據圖, =厚度控制在9Κ埃’且金屬線圖案密度>35%時,空洞 缺陷隨著截距不同而改變之情形; 第四圖為鋁金屬連線其空洞缺陷之數據 =厚度控娜埃,且金屬線圖案密度<35二不二 缺^隨者截距不同而改變之情形; 形為半導體晶片之截面圖,顯示根據本發明依序 形成黏者層、金屬層與遮蓋層於半導體底材上之 電第六圖為半導體晶片之截面圖,顯示根 明進 電襞處理以形成硬式罩殼於金屬連線外表面之步驟·盯 〜第七圖為半導體晶片之截面圖’顯示根據本發明進 積及程序’以形成金屬間介電層覆蓋於半導體 本二八方圖Λ铭Λ屬Λ線Λ空洞缺陷之數據圖,顯示根據 *月方法進仃高揹度電漿沉積程序時,當金 ::在9Κ埃,即使金屬線截距降低至〇8" 不】 生空洞缺陷。 、it个賞座Page 12 451412 Simple description By combining the following detailed description with the attached drawings, the above content and the many advantages of this invention can be easily implemented, among which: The first chaos is a cross-sectional view of a semiconductor wafer. Shows the hole defects caused by the formation of aluminum metal connections on the + conductor substrate according to the traditional technology. Gold Λ 二 Λ is a data chart of the hole defects of the junction metal connection, showing the voids as the thickness increases and the intercept Increasing the probability of defect generation. The third graph is a data graph of void defects in aluminum metal wires. = When the thickness is controlled at 9K 'and the metal line pattern density is> 35%, the void defect changes with different intercepts. The figure 4 shows the data of the void defect of the aluminum-metal connection = thickness control, and the density of the metal line pattern < 35 is not missing ^ It varies with different intercepts; it is a cross-sectional view of a semiconductor wafer, showing According to the present invention, the adhesive layer, the metal layer, and the cover layer are sequentially formed on the semiconductor substrate. The sixth figure is a cross-sectional view of a semiconductor wafer, which shows that the substrate is electrically processed to form a hard cover on the surface of the metal connection. Steps · Staring ~ The seventh figure is a cross-sectional view of a semiconductor wafer 'shows the advancement and procedures according to the present invention' to form an intermetallic dielectric layer to cover the semiconductor substrate. The figure shows that when the high back plasma deposition process is carried out according to the method, when gold :: at 9K angstroms, even if the intercept of the metal wire is reduced to 〇8 " No] void defects are generated. It's a reward
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