TW451412B - Manufacturing method for metal interconnection preventing the formation of void - Google Patents

Abstract

A manufacturing method for metal interconnection on the semiconductor substrate which includes the following steps: first, forming the metal layer on the semiconductor substrate and conducting lithography process on the metal layer to define the interconnection pattern in the metal layer; next, conducting plasma processing on the metal layer to reduce the probability of the formation of void, in which the plasma processing is under N2O gas environment with flow rate at 800 to 1600 sccm and with RF power at about 100 to 300 W for 30 to 90 seconds; then, conducting high density plasma (HDP) deposition process to form the inter-metal dielectric (IMD) on the semiconductor substrate and the metal layer.

Description

¢ 51412 V. Description of the invention (1) Field of the invention: The present invention relates to an inter_connection process in a semiconductor process, and particularly to a process in which metal is produced by a high density plasma (HDP) process. In the case of an inter-dielectric layer (IMD), the metal connection process can effectively reduce the probability of void formation. Background of the invention: The design of integrated density integrated circuits in very large integrated circuits is less than micron. And because of the semiconductor manufacturing process, the level of encounters is constantly increasing. In general, millions of pieces of electronic connection structures are formed in a certain area, and the performance of the circuit is in addition to relying on the innumerable precise and delicate metal electronic numbers. Especially with the design of integrated circuit,

Q In the development and design of the continuous progress of the semiconductor industry (ULSI), in order to comply with the trend, 'the size of various components has been reduced to a continuous reduction, which has also led to unprecedented difficulties related to the process, and the process is complicated. The body circuit includes a special component on the wafer 'and the specific function used to connect this element to perform. Therefore, in addition to the performance and reliability of the body components, wiring is needed in order to effectively transfer between components: the size of the body circuit continues to shrink, and the current heavy metal interconnects have been developed. In addition, for the good conductivity and cheap manufacturing cost of traditional semiconductors, aluminum metal materials can be deposited and etched arbitrarily due to their

Page 4 451412 V. Description of the invention (2) Carving is a wire material that often becomes the industry's priority. However, with the increasing accumulation of semiconductor components, the use of metal aluminum as the contact structure of the connection has also encountered many difficulties. For example, in high-temperature environments, Ming atom is easy to interact with silicon substrates (inter_diffusi 〇n), resulting in a spike phenomenon ", and lead to poor contact of the aluminum wire. In addition, when the size of the aluminum wire is reduced with the element, the aluminum atom movement caused by " electromigration " Short circuit in the aluminum wiring structure. Please refer to the first figure ', which shows the method of making the aluminum metal connection. Among them, a semiconductor substrate 10 is first provided, and on the semiconductor substrate 具有, it has various functional layers and various elements required. Next, an aluminum metal layer 12 is formed on the semiconductor substrate 10, and a lithographic etching process is used to define a wiring pattern thereon. Then, an intermetal dielectric layer 14 is formed to cover the semiconductor material 10 and the aluminum metal layer 12 and fill the gap between the aluminum metal layer 12 and the metal layer 12. In general, when depositing the intermetal dielectric layer 14, in order to take into account good gap fill capability and better passivation effect, high density electrical destruction (High ° density PlaSina) is often used; HDP) deposition process to make the intermetallic dielectric layer U ... is when the size and quality of the semiconductor element is not less sensitive. The gap 16 shown in the first figure will have a finer dimension,: 'Chemical vapor deposition The method (CVD) cannot effectively deposit into these voids 16. Therefore, when the integrated circuit manufacturing process // falls to 5 materials 4 514 1 ^ V. Description of the invention (3) --- m below, often need to use the HDP deposition process to make the intermetal dielectric layer 14 . It is worth noting that the local density plasma deposition process is to continuously perform sputtering and depotting on the semiconductor substrate 10 to produce the intermetal dielectric layer 14. Among them, the polymer that causes the hole filling obstacle during the process can be removed by the splash effect, so as to ensure that a dielectric material can be deposited into the void 16. However, when an excessively strong coin strike effect is used, the metal layer 12 often causes clipping. Even under a slight splashing effect, the metal layer 12 will cause a crack (seam), and the structural stress of the metal wiring 2 will be unbalanced. Especially when the metal connection ^ has a high aspect ratio, 'in order to maintain a good hole filling ability of the intermetal dielectric layer 14', the stress imbalance of the metal connection 2 will become more serious. As a result, the metal wiring 12 has a void (v o i d) defect 18 as shown in the first figure. Please refer to the second figure. This figure shows the formation of voids in the aluminum metal connection after HDP process is used to deposit the intermetal dielectric layer. Among them, the aluminum metal wires containing copper atoms have thicknesses of 4K, 6K, 8K, and 9K, respectively, and the density of the metal wire patterns on the entire semiconductor substrate exceeds 35%. As a result, the 'Dangshao metal wire's intercept decreases from 0 to 6 β m', and its aspect ratio will show an upward trend. In addition, "" 〇" in the figure shows that after the HDP process is used to deposit the intermetal dielectric layer, no void defect has occurred in the aluminum-metal connection. In contrast, the symbol "X" in the figure indicates the inscription

15m 1 2 V. Description of the invention (4) The metal connection has void defects, which does not meet the requirements for yield. Therefore, according to the second figure, it can be seen that when the thickness of the aluminum metal connection increases or the intercept decreases, it will cause the occurrence of void defects.11 In other words, as the aspect ratio of the metal connection becomes larger, the chance of the occurrence of void defects also increases. Will increase. Next, please refer to the third figure again. This figure shows the HDP machines of AMAT and Novellus to perform the intermetal dielectric layer deposition process, and the void defects caused by the interception of the metal wires. Among them, the density of the aluminum metal wire pattern is more than 35%, and the thickness is controlled at 9K Angstroms. At this time, it can be found that for the AMAT machine, when the intercept of the metal connection is lower than 1, 2 # m, its HDP program will cause the generation of metal voids. In contrast, when using the Novell us machine, even when the intercept of the metal connection is as low as 0.8 Ajn, the generation of voids can be effectively suppressed. It is worth noting that in the HDp program, the temperature of the 'AMAT machine is controlled at about the left and right; the temperature of the Novel lus machine is controlled at 33. It is obvious that excessively high temperatures will also cause voids in metal connections. 1

After the productive lease sequence, a hole is created in the metal connection. The ratio of the perylene pattern is controlled below 35%, and the thickness remains the same. The method of VV2 finds that even if the intercept of the metal line rises to 1.6, Λ suppresses the formation of voids after gold lamination. It ’s important to note that ‘when it ’s higher,’ the heat dissipation efficiency can be improved ... ° It can be seen that the proportion of metal wiring patterns is less than 35%

V. Description of the invention (5) The heat dissipation efficiency will be low, which will cause void defects. Obviously, when the temperature is too high or the heat dissipation performance is not good, it is easy to create holes in the metal connections. OBJECTS AND SUMMARY OF THE INVENTION: The main object of the present invention is to provide a related process which can reduce void defects caused by metal connections.

Another object of the present invention is to provide a method for reducing the formation of void defects in metal wires during a high-density plasma deposition process. Β A method for making metal wires on a semiconductor substrate. First, an adhesive layer is formed on the semiconductor substrate, and an aluminum metal layer is formed on the adhesive layer. Then, a cover layer is formed on the upper surface of the aluminum metal layer, and a lithography process is performed on the aluminum metal layer to define a connection pattern in the metal layer. Next, plasma treatment is performed on the metal layer to reduce the probability of void formation. The electro-chemical treatment is performed in an N20 gas environment with a flow rate of about 800 to 1 600 seem and a RF power of about 100 to 300 W for about 30 to 90 seconds. . In this way, a hard cover can be formed on the surface of the metal layer to improve the stress balance of the metal layer. Β Then, a high density plasma (HDP) deposition process is performed to form an intermetal dielectric layer (IMD) on the semiconductor substrate. Wood and metal layers. Detailed description of the invention:

Page 8 45 ί 4 1 2

5. Description of the invention (6) The present invention provides a new method for forming a metal wire on a semiconductor substrate. ‘By using lithographic etching to define a metal line pattern, a plasma treatment program containing Nζ0 gas is performed to effectively improve the metal’ Zhan Yingying. Force balance. In order to reduce the chance of voids in the metal layer during the subsequent high-density electricity distribution process (HDP), the relevant details are described below, please refer to the fifth figure, first provide a &lt; 100 &gt; Crystal orientation of single crystal silicon substrate 100. Generally speaking, other types of semiconductor materials, such as gallium arsenide, germanium, or silicon on insulator (SOI) on the insulating layer, can be used as semiconductor f materials. In addition, 'due to the characteristics of the surface of the semiconductor substrate to the present invention' does not cause a special influence ', it is possible to select <1 丨 0> or &lt;111; &gt; depending on its crystal orientation. Then, various active cores, passive components, peripheral circuits, and the like required for the integrated circuit can be fabricated on the semiconductor substrate 100 (not shown in the figure). Before carrying out subsequent procedures, the surface of this semiconductor substrate 100 already has various functional layers and material layers required. Next, a glue layer 102 is formed on the semiconductor substrate 100 to improve the adhesion between the metal wiring and the functional layer 'material layer: Generally, the adhesive layer 102 can be nitrided. Titanium (TiN) or titanium (η) layers come from outside. This adhesion can be 102 and can have a barrier effect, and prevent the subsequent formation of l5141 3 ---------- V. Description of the invention (γ) t metal A diffusion phenomenon occurs between the wiring and the semiconductor substrate 100, resulting in a spiking effect. In the preferred embodiment, a nitriding (N i t r i d a t i ο η) process can be used to form the desired titanium nitride layer. First, a sputtering process is performed to deposit a titanium f on the upper surface of the semiconductor substrate 100, and then the same titanium nitride layer is formed through the same room treatment in an &amp; or ^ 113 environment; in addition, Reactive forging procedures can be used to form the titanium nitride layer. By bombarding titanium metal with plasma ions and passing in argon and nitrogen, the titanium atoms splashed by the bombardment can react with nitrogen atoms formed through a dissociatiori reaction and form titanium nitride. Deposited on the surface of the semiconductor substrate. Then, a metal layer 104 is formed on the adhesive layer 102. Generally, a copper-containing aluminum metal can be deposited on the adhesive layer 102 as a metal layer 104 by well-known techniques such as physical vapor deposition (PVD), sputtering and the like. In addition, other metal materials such as titanium, tungsten, copper, gold, platinum, or alloys of any composition can also be used as the metal layer 104 in the present invention. After the metal layer 104 is formed, a cap layer 105 is formed on the upper surface of the metal layer 104 to prevent contamination and prevent oxygen from interacting with the deposited metal layer 104, thereby reducing the conductivity. . Among them, the material of the cover layer 105 can also be selected from the aforementioned TiN or Ti materials. Subsequently, please refer to the sixth figure. The covering layer 105, the metal layer 104, and

Page 10 45] 412 5. Description of the invention (8) Adhesive layer 102 'is subjected to a lithography process to define a wiring pattern in which a. Generally, a dry etching method such as reactive ion etching can be used to cover the cover layer. 105. The metal layer 104 and the adhesive layer 102 are etched to define a connection pattern. Among them, the silver etchant used to define the aluminum metal connection pattern and the titanium nitride layer can be mixed with Ci2, SiCl4, BC13, BB.r3, CC14 and other gases. As for 'when the adhesive layer 102 is composed of a titanium layer, C2C12F4, CF4, CC1F3, CBrF3 + He + 〇2 can be selected as the formula for the engraving.

Next, the metal layer 104 may be subjected to a Piasma treatment 106 to reduce the probability of void formation. Among them, the plasma treatment 106 is formed in a 乂 0 gas environment with a flow rate of about 800 to 1 600 seem, and is performed at a radio frequency power of about 100 to 300 W for about 30 to 90 seconds. In this way, when the metal layer 104 used is an Is metal material, an aluminum oxide layer 108 having a thickness of about 100 to 300 angstroms can be formed on the outer surface of the metal layer 104, thereby reducing the void opening in the metal layer 104; Chance. Generally speaking, due to the oxide layer 丨, the outer surface of the metal layer 104 can be uniformly covered, so that a protective effect of a hard cover can be produced. In this way, during the HDP deposition process, the alumina layer 108 can protect the underlying metal layer 104 and maintain its stress balance ', thereby effectively avoiding the problem of void defects caused by uneven stress'. In the preferred embodiment, 'the RF power can be adjusted to about 200 W, and the plasma treatment is performed for about 45 seconds to form the required alumina layer 108. In addition, in addition to the plasma treatment with% 0 gas It is also possible to simultaneously pass in a gas with a flow rate of about 8000 to 1600 seem, and reduce the chance of voids in the metal layer 104.

^ 51412 V. Description of the invention (9) Subsequently, referring to the seventh figure, a high-density plasma (HDp) deposition process is performed to form an intermetal dielectric layer (IMD) 110 on a semiconductor substrate 100, and a cladding layer 102 and the metal layer 104 are filled in the gap between the metal layer 104. In the preferred embodiment, the radio frequency bias (bias_RF) used is controlled below about 2500 W, and the flow of η e gas is controlled above 9 Torr. Thus, by increasing He Airflow 'can keep the temperature low, which is beneficial to prevent the generation of voids. Please refer to the eighth figure. This figure shows the result of conducting the polymerization treatment on the semiconductor substrate by passing in a gas of% 0 before performing the high-density plasma deposition process using the method of the present invention. Among them, the thickness of the aluminum metal connection is about 9K Angstroms, and the intercept is controlled between 0.8 # m to 1.6 y m. In this way, it can be seen from the figure that no matter whether the AMAT or Novellus machine is used, voids can be effectively avoided in the aluminum metal connection. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. For those skilled in the art, it is within the spirit and scope of the present invention. The repairs made shall be included in the scope of patent application described below.

Page 12 451412 Simple description By combining the following detailed description with the attached drawings, the above content and the many advantages of this invention can be easily implemented, among which: The first chaos is a cross-sectional view of a semiconductor wafer. Shows the hole defects caused by the formation of aluminum metal connections on the + conductor substrate according to the traditional technology. Gold Λ 二 Λ is a data chart of the hole defects of the junction metal connection, showing the voids as the thickness increases and the intercept Increasing the probability of defect generation. The third graph is a data graph of void defects in aluminum metal wires. = When the thickness is controlled at 9K 'and the metal line pattern density is> 35%, the void defect changes with different intercepts. The figure 4 shows the data of the void defect of the aluminum-metal connection = thickness control, and the density of the metal line pattern &lt; 35 is not missing ^ It varies with different intercepts; it is a cross-sectional view of a semiconductor wafer, showing According to the present invention, the adhesive layer, the metal layer, and the cover layer are sequentially formed on the semiconductor substrate. The sixth figure is a cross-sectional view of a semiconductor wafer, which shows that the substrate is electrically processed to form a hard cover on the surface of the metal connection. Steps · Staring ~ The seventh figure is a cross-sectional view of a semiconductor wafer 'shows the advancement and procedures according to the present invention' to form an intermetallic dielectric layer to cover the semiconductor substrate. The figure shows that when the high back plasma deposition process is carried out according to the method, when gold :: at 9K angstroms, even if the intercept of the metal wire is reduced to 〇8 &quot; No] void defects are generated. It's a reward

Claims (1)

A method for making a metal connection on a semiconductor substrate, the method includes at least the following steps: forming a metal layer on the semiconductor substrate; performing a lithography process on the metal layer to define a connection pattern in the metal layer; The metal layer is plasma-treated to reduce the probability of void formation. The electro-chemical treatment is performed at a flow rate of about 800 to 160 sccm in a gaseous environment. Formed in 90 seconds; and a high-density plasma (HDP) deposition process is performed to form an intermetal dielectric layer (IMD) on the semiconductor substrate and the metal layer. The layer is on the gold description of the French method of the project. It is about 4py. Please apply for aluminum. If you choose, you can choose 2 materials, or platinum, gold, copper, tungsten, and titanium. The above item of its legal method ο the Cheng Chengwei model is specialized in requesting the application of oxygen, such as layer 3 dielectric 4. The method of item 1 in the scope of patent application, in which the above-mentioned plasma processing procedure includes access 80 0 to 1 60 0 seem oxygen. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned high-density electrodeposition process is performed in an environment with a radio frequency bias (bias-RF) of about 2500W or less and a pressure of He gas of 9 Torr or more. Page 14 451 4 彳 2 6. Application for Patent Scope 6. The method of applying for the item 1 of the patent scope, in which the above plasma process can form a hard type on the outer surface of the metal layer with a thickness of about 100 to 300 Angstroms. The cover improves the stress balance of the metal layer. 7. The method of claim 1 in which the above-mentioned metal layer is composed of aluminum metal, and the plasma process can form an aluminum oxide layer on the outer surface of the metal layer, thereby improving the stress balance of the metal layer. . 8. The method according to item 1 of the scope of patent application, wherein before forming the above-mentioned metal layer ', it further comprises forming an adhesive layer on the semiconductor substrate to improve the adhesion between the metal layer and the semiconductor substrate. 9. For the method according to item 8 of the patent application, in which the material of the above adhesive layer can be randomized, laminated, or any combination thereof. 10. The method according to item 1 of the scope of patent application, wherein after the formation of the above-mentioned metal layer 'further comprises forming a covering layer on the upper surface of the metal layer to prevent contamination and prevent oxygen from reacting with the metal layer. 11. The method of claim 10, wherein the material of the cover layer can be selected from titanium nitride, a titanium layer, or any combination thereof. θ Page 15 6. Application scope: Forming an aluminum metal layer on the semiconductor substrate; etching the aluminum metal layer to define a wiring pattern therein; forming an aluminum oxide layer having a thickness of about 100 to 300 angstroms on the surface of the aluminum metal layer Reduce the probability of void formation; and coat the surface to perform a high-density plasma (HDP) deposition process to cover the intermetal dielectric layer (IMD) on the semiconductor substrate and the aluminum metal layer. s 13. The method according to item 12 of the scope of patent application, wherein the material of the metal layer is an aluminum-steel alloy. 14. The method of claim 12 in which the above-mentioned intermetal dielectric layer is composed of silicon oxide. 15. The method according to item 12 of the scope of patent application, wherein the above-mentioned oxide layer is formed by a plasma treatment process. 16. The method according to item 15 of the scope of patent application, wherein the above-mentioned plasma treatment procedure is carried out at a flow rate of about 800 to 1 600 sccmiN20 gas environment with a radio frequency power of about 100 to 300w for about 30 minutes. Formed to 90 seconds. Π · The method of item 16 in the scope of patent application, wherein the above-mentioned plasma treatment procedure further includes the passage of gas from 800 to 1603 (: (: 111, 02). 18, such as the scope of patent application in scope 1 2 Method of the above item, wherein the high density Page 16 6. Scope of patent application The plasma deposition process is performed in an environment where the radio frequency bias (bias-RF) is less than about 250 0W and the pressure of He gas is 9 Torr or more. 19. The method according to item 12 of the patent application, wherein before the forming of the above-mentioned metal layer, the method further includes forming an adhesive layer on the semiconductor substrate to improve the adhesion between the aluminum metal layer and the semiconductor substrate. . 20. The method according to item 19 of the patent application range, wherein the material of the adhesive layer is selected from titanium nitride, a titanium layer, or any combination thereof. 21. The method according to item 12 of the patent application, wherein after forming the above-mentioned metal layer, the method further includes forming a covering layer on the upper surface of the aluminum metal layer to prevent contamination and prevent oxygen from reacting with the aluminum metal layer. 22. The method according to item 21 of the patent application range, wherein the material of the above cover layer can be selected from titanium nitride, a titanium layer, or any combination thereof. Page 17