TW468262B - Copper damascene process to enhance the reliability of electrical characteristics - Google Patents

Abstract

A copper damascene process to enhance the reliability of electrical characteristics is hereby disclosed. The present patent describes the method to enhance the reliability of electrical characteristics effectively during the fabrication of the metal interconnect of single damascene or dual damascene structure. Firstly, there are formed a dielectric layer on the semiconductor substrate, and a first stop layer on the surface of the dielectric layer. Then the first stop layer and the dielectric layer are etched to form an opening inside for exposing the upper surface of the semiconductor substrate. Then there is formed a copper layer on the semiconductor substrate by proceeding electrical chemical plating (ECP) and filling the opening. Thereafter, the chemical mechanical polishing process is proceeded to the semiconductor substrate to remove part of the copper layer on the upper surface of the first stop layer, and part of the first stop layer is removed, and the copper damascene structure is defined in the opening. A second stop layer is formed on the upper surface of the remaining first stop layer and the copper damascene structure, wherein the second stop layer and the first stop layer are formed of the same material, and the copper process is improved by utilizing two characteristics: using part of the residue of the stop layer and using the same material. The dielectric material can be completely sealed at the junction no matter it has the single damascene or dual damascene structure, so that the electrical characteristics and the reliability can be improved.

Description

4 6 8 26 2 V. Description of the invention (l) Field of the invention: The present invention relates to a copper damascene structure in a semiconductor process, particularly a homogenous structure stack using the same material in the process of manufacturing a copper damascene structure. Layer to improve the adhesion characteristics of the insulation material around the copper mosaic structure and reduce the related transition method of copper atom electro-induced transition. Background of the Invention: In accordance with the (ULSI) trend, the former mentioned above, the component wiring of the cumulative implementation of the elements, the development of heavy metals and semiconductors in the body circuit are shrinking, and there is no such body circuit component as necessary. The special performance in order to be able to maintain the size of the interconnect industry. In the industrial continuity and design, the size of the components has also led to difficulties, and manufacturing includes wafers and used to connect fixed functions. Due to the continuous reduction and development of effective transmission beyond reliability. In order to reduce the complexity of the related process to a certain special element, the current needs to be more than one micrometer in the super large-scale integrated high-density product. In the semiconductor manufacturing process, the performance of the electronic connection circuits of the components in the area is constantly being specified. Countless precise electronic signals are required. Special product circuit design The design of the body circuit circuit and the components often encounter millions of structures, so that in addition to relying on the metal inside, but also with the product, it has been moving toward the multi-layer and in order to solve the problem in multiple layers Difficulties in making metal interconnects

Page 5 468262 5. Description of the invention (2) The related technology of the damascene process has been extensively researched and developed in order to effectively overcome the limitations of lithographic resolution, the error of the focus and the image transmission. Insufficient accuracy and resolution. Among them, through the use of single damascene or duai damascene technology, multiple metal interconnects can be accurately defined on semiconductor substrates. Please refer to the first figure, which shows the current method of making copper wiring structures. Among them, a semiconductor substrate 10 is provided first, and various material layers and various functional elements have been previously prepared on the semiconductor substrate 10 (not shown in the figure). Next, an oxide layer 12 is formed on the semiconductor substrate 10, and a thin silicon nitride layer 14 is formed on the upper surface of the oxide layer 12. Then, a photolithographic etching process is used to sequentially form openings in the silicon nitride layer 14 and the dielectric layer 12 to expose the connection area (not shown in the figure) on the semiconductor substrate 10. Then, by using chemical bonding (Electrical chemical plating; ECP) process can deposit a copper layer 16 on the semiconductor substrate 10, the oxide layer 12, and the silicon nitride layer 14 and fill the openings. Subsequently, as shown in the second figure, a chemical mechanical polishing (CMP) process is used to remove a portion of the copper layer 16 above the oxide layer 12 to define a copper damascene structure 18 in the opening. During the polishing process, the silicon nitride layer 14 'on the upper surface of the oxide layer i 2 can be used as a polishing stop layer so that the steel layer 16 above it can be completely removed. But it is worth noting that in the current grinding

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In the procedure, except for removing the unnecessary copper layer, the silicon nitride layer 14 is removed. Then it will be re-^^ ', and will continue to grind to drop by i —) 2. For the copper mosaic structure 18 and "= = say 'because this cap layer 20 is on the upper surface of subsequent processes .: Generally used, it is based on the selection of its material and the material for the ㈣stop layer to make it more selective. : It is used as the cap layer 20 compared with the oxide. For example, nitriding can be selected. 'Special mention' is made because the cap layer 20 and the oxide layer 12 are made of different materials. The characteristics of the joint surface are often poor. Furthermore, due to the extremely strong ability of copper atoms to invade and diffuse in the oxide, the copper atoms in the copper ballasting structure 18 are often caused along the cap layer 20 and the oxide layer 12 Diffusion occurs at the bonding surface 22. Please refer to the third figure, which shows the relevant configuration β during the BTS test procedure. Among them, by connecting a voltage source to the fabricated copper mosaic structure 18, different levels of voltage can be applied to it In order to observe the operating characteristics of these copper damascene structures 18. At this time, it can be found that when the applied voltage is too high, or when it is performed in a reverse bias manner, the copper damascene structure 18 tends to produce severe electrical transitions (EM). ). And the 'diffused copper atoms' will intrude into the interface between the capping layer 20 and the oxide layer 12 in the direction of the arrow. Please refer to the fourth figure, which shows the above-mentioned electro-transition situation. 30 is formed in an intermetal dielectric layer (IMD) 32. Moreover, after conducting electrical tests on these copper damascene structures 30, it can be found that copper atoms will indeed follow the cap layer 34 and the intermetal dielectric layer 32. Interface

4 6 8 26 2 V. Explanation of the invention (4) Invasion and proliferation caused by the explosion 'cause the protrusion 36 in the figure. At the same time, void-like defects 38 may also be generated in the copper mosaic structure 30 in which some steel atoms are lost. In this way, in addition to possibly causing short circuits in the defined integrated circuit, too many voids will also seriously affect the conductive properties of the copper damascene structure 30. Object and Summary of the Invention: Semiconductor Probability The main object of the present invention is to provide a method for making a copper mosaic structure on a body substrate. Another object of the present invention is to provide a related process for effectively encapsulating and sealing the copper mosaic structure in the copper mosaic process, thereby reducing the electrical transition. To make a copper damascene junction on a semiconductor substrate, follow these steps. First, a dielectric layer is formed on the semiconductor package; a layer is formed on the surface of the dielectric layer. Among them, the third-stop layer and the third one are: the remaining time selection ratio. Then, in the rest of the first stop layer and the dielectric, U forms an opening in the first stop layer and the dielectric layer. Its; layers, valve ports and exhaust

Page 8 4 6 8 26 2 V. Description of the invention (5) Exposing the upper surface of the semiconductor substrate. Then, a barrier layer is formed on the sidewall of the opening and the upper surface of the exposed semiconductor substrate. Then, a copper seed layer is formed on the surface of the barrier layer and a chemical plating (Ecp) reaction is performed to form a copper layer on the surface of the copper seed layer and fill the opening. Then, a CMP process can be performed on the semiconductor substrate to remove a portion of the copper layer on the upper surface of the first stop layer and remove a portion of the first stop layer to define a copper damascene structure in the opening. Then, a second stop layer is formed on the remaining first stop layer and the upper surface of the copper damascene structure. The second stop layer and the first stop layer are made of the same material. In this way, by virtue of the homogeneity between the second stop layer and the first stop layer, the purpose of covering and sealing the underlying copper mosaic structure can be achieved. Detailed description of the invention: Materials are provided first-single crystal with crystalline orientation (gaU-arSenide), germanium (germanium such as two ... siliC0 " "aator, semiconductor substrate 50 is used. In addition As the hair here ..., it does not cause the special body === to choose < 110> or < 111 >. The ruler can also be selected from its crystal orientation and then can act on the semiconductor substrate 50. It should be explained here that before the integrated circuit required to form the integrated circuit 52 has been fabricated on the shape 50 to produce insulation into the dielectric layer 52, various active components, passive components,

Page 9 468262 V. Description of the invention (6) and surrounding circuits and so on. In other words, on the surface of the semiconductor substrate 50, there are already various functional layers and material layers required. As for the above-mentioned dielectric layer 52 ', in a preferred embodiment, an oxide crushing material may be selected for construction. For example, using chemical vapor deposition (C VD) with tetraethyl oxalate (τEO S) at a temperature of about 800. c. The pressure is about 0.01 to 10 torr to form silicon oxide. Or: It is also possible to use tetraethyl silicate (TEOS) as a reaction material and add fluorine atoms to form fluorosilicon glass (FSG) by chemical vapor deposition (LPCVD) as the above-mentioned dielectric layer 52. In addition, when the overall process requirements, materials such as BD, copal, Siu, FUre, HSQ, tns〇 ^ aSS and other materials with low dielectric value (K value) can be used to constitute the above-mentioned dielectric gen 5 2 . Then, a first stop layer 54 may be formed on the upper surface of the dielectric layer 52. The first stop layer 54 may be formed by selecting a material having an etching selectivity ratio with the dielectric layer 52. For example, when the material of the dielectric layer 52 is a material, the first stop layer 54 may be formed of silicon nitride (SU) or carbon (a). When silicon nitride material is selected, low pressure phase deposition (LPCVD) or electro-enhanced chemical vapor deposition (ECVD) can be used, and the temperature is about 400 ~ s00t. j, M or SiH2Cl2, NH3, N2, N2O and other reaction gases, and the shape: the required first-stop layer 54. In a preferred embodiment, the thickness of the first stop threat 54 can be controlled between 200 and 50 angstroms. Then, the first stop layer 54 and the dielectric can be

mm

Page 10 4 6 8 26 2 5 'Explanation (7) " The layer 52 is subjected to an etching process, and an opening pattern 56 is defined therein. Among them, the opening pattern 56 will expose the upper surface of the semiconductor substrate 50. In general, when defining the opening pattern 56 described above, a photoresist layer 'may be formed on the first stop layer 54 and the opening pattern on the photomask may be transferred to the photoresist layer. Next, the photoresist layer is used as an etching mask to perform an etching process on the first stop layer 54 and the dielectric layer 52 to define an opening pattern therein. In addition, after the pattern is defined on the first stop layer 54, the first stop layer 54 can also be used as an etching mask to perform an etching process on the dielectric layer 52 to form an opening pattern therein. In a preferred embodiment, when the first stop layer 54 is made of silicon nitride, the etch agent can be selected from CF ^ H2, CHF3, or CH3CHF2. In addition, when the dielectric layer is made of a silicon oxide material, cc 1 2 F2, CHF3 / CF4, CHF3 / 02, CH3CHF2, cf4 / o2 can be selected as an etchant. Then 'refer to the sixth figure' to form a barrier layer 5 8 on the opening pattern 5 6 side wall and the upper surface of the exposed semiconductor substrate 50 to prevent the subsequent manufacturing of the steel layer and the dielectric layer 52 and the semiconductor substrate 50 Diffusion occurs, resulting in a spike effect. In a preferred embodiment, the temperature at which the barrier layer 58 is formed is about 250 to 400 ° C, so as to effectively reduce its structural stress. As for the material of the barrier layer 58, titanium (π), button (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable material combinations can be selected. In addition, the barrier layer 58 is preferably formed to a thickness of about 100 to 500 angstroms. After the barrier layer 58 is formed, a copper seeding layer (Cu seeding 1 a y e r) 60 may be formed on the surface of the barrier layer 58. In a preferred embodiment, the copper seed layer

468 26 2 V. Description of the invention (8) Subhead deposition method (Physical method and other similar processes), and then, the semiconductor substrate chemical plating (ECP) can be reacted and filled in the opening pattern 5 6 A cathode of a power source undergoes a reduction reaction and is deposited to perform a plating process, so that the copper can be formed into the required copper layer 62. Generally, after the opening pattern 56, the first stop layer 5 4 is still used. 60 can be used Well-known techniques, such as physical gas vapor deposition (PVD), reduce the thickness between about 500 and 1500 angstroms, and immerse 50 in a copper sulfate solution to form a copper layer 62 on the surface of the copper seed layer 60. Among them, the surface of the copper ion copper seed layer 60 which is located in the copper sulfate solution is electrically charged with the copper seed layer 60. That is, the copper layer 62 is deposited on the surface of the copper seed layer 60, and the produced copper layer 62 is filled with a complete sinker to cover the dielectric layer 52 and then, as shown in FIG. 7, The semiconductor substrate 5 {) can be subjected to a chemical machine = grinding process (CMP) 'to remove the damaged copper layer 62 on the upper surface of the first stop layer, and define a copper drum structure 64 in the opening pattern 56. Important It is emphasized that, as mentioned above, in the traditional manufacturing process, it is often: to stop the migration to make the capping layer directly on the surface of the dielectric layer in the subsequent process. However, in the embodiment of the present invention, -After the stop layer 54, stop the chemical mechanical polishing process β, that is, after removing the copper layer 62 on the upper surface of the first stop layer 54, remove a part of the first stop layer n at the same time. 'The thickness of the remaining -stop layer 54 is about 200 angstroms. In addition, the formed copper damascene structure 64 can be used not only as a dielectric interlayer copper connection (via), but also as a copper conductive plug (plug). use.

46 8 26 2 V. Description of the invention (9) Subsequently, the shaped mosaic structure 64 can be used as the first stop layer 66 and the second stop layer 66 in the steel sequence as the last stop layer 66 by the same material. 6 6 The material of the first stop stop layer 66 is made of the second stop layer 66 on the surface. In particular, the cover stop layer of the mosaic structure 64 is used. And the homogeneity of the material with the first stop (homog stop layer 6 to 6), a stop layer 54 is produced by nitrogen 'and also chooses to use a nitride stop layer 5 4 because the dream material should also be the same. Remaining The first stop layer 54 of copper and the “outside of the second stop layer 66 here” of copper may also be used in the subsequent etching process. In the method of the present invention, this second layer 54 is the same. In this way, it can be eneous) ' First stop with good bonding characteristics. In other words, when it is composed of silicon, it is constituted by the second stop. Similarly, when all or other suitable materials are used, the second and when the silicon nitride material is in contact with the same silicon nitride film, the adhesion between the film layers can be as high as 43.2 Mpa. In contrast, when the silicon nitride material is bonded to the silicon oxynitride layer, the adhesion force between them is only about 32 MPa. When the silicon nitride material is bonded to the silicon oxide film layer, the adhesion between them is only about 12 Mpa. Obviously, when the film layers of the same material are used for bonding, the adhesion characteristics of the contact surfaces will be better. Therefore, after the second stop layer 66 of the same material is formed on the surface of the first stop layer 54, a better sealing effect can be produced on the copper damascene structure 64 thereunder. In other words, since the upper corners of the copper damascene structure 64 are exactly covered by the second stop layer 66 and the first stop layer 54, the invasion and diffusion of the copper damascene structure 64 in the dielectric layer 52 can be effectively reduced. Opportunity. In this way, when performing a BTS test on the copper damascene structure 64, even if a reverse bias voltage or a high voltage is applied to the copper,

Page 13 4 6 8 26 2 V. Description of the invention (ίο) None of the mosaic structures 64 will cause the diffusion of copper atoms. Therefore, it is possible to effectively prevent the copper mosaic structure 64 from generating an electro-transition effect, which can cause protrusions into the junction surface of the dielectric layer 52. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. For those skilled in the art, modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Page 14 4 6 8 26 2 Schematic description By combining the following detailed description with the above-mentioned contents and the many advantages of this invention, it will be easy to understand the first semiconductor substrate, the second semiconductor substrate, and the third copper. The inlaying step; the fourth copper inlay produces a copper original fifth opening in the sixth copper layer and opens the seventh part of the copper layer ® as a semiconductor wafer cutting material, and Shen ® is a semiconductor wafer cutting material The copper mosaic structure diagram is formed on the semiconductor wafer wearing structure to apply high voltage or reverse face circle, showing the steps of & 々 not according to the traditional technology; the copper layer in it; f, showing the steps according to the traditional technology ;: 'Shows the step diagram of the bias voltage to test its operating characteristics according to the traditional technology. The figure is a semi-embedded structure. The figure is a half stop. The figure is a half stop. The figure is a half and a step on the stop layer. The first stop layer step of the conductor wafer and the dielectric wafer; and the first stop step of the conductor wafer. A plan view showing the diffusion process according to the conventional technology, which results in the junction of the dielectric layer. The plan view shows the steps of forming according to the present invention, and the plan view shows the formation of the plan view according to the present invention. The second stop is at the

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Claims (1)

4 6 8 26 2 Six, the method of patent application, the two methods of manufacturing a mosaic structure on a two-conductor Λ material, the method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; forming a first The stop layer is on the surface of the dielectric layer. The first stop layer and the dielectric stopper are sculpted. ® ® 帝 八 八 八 J J 屡 ¥ 'to form an opening in the first stop layer and the dielectric layer. In which, the upper surface is opened;] and the semiconductor substrate is exposed to perform a chemical plating (ECP) reaction to form, fill, and fill the opening; a steel layer is formed on the semiconductor substrate to perform the semiconductor substrate Chemical machinery: part of the upper surface of the first stop layer, the 2 grinding process to remove the stop layer, in order to define the copper embedded structure , Forming an upper surface, wherein the second stop layer is formed by the stop layer and the copper inlaid junction material. The layer and the -stop layer use the same layer two halves as the method of the first item in the scope, where in the formation of the dielectric: == the first 1 includes the formation of various components or material layers on the + conductor bottom Steps on the wood. 3 temples? No. of patent application scope! The method of item 1, wherein the chemical plating reaction is performed, further comprises the following steps: forming a barrier layer on the side wall of the opening and the upper surface of the semiconductor substrate; and forming a copper seed layer on the surface of the barrier layer. 1 page 16 4 d 2 6 2 4. The method according to item 3 of the patent application, wherein the above-mentioned chemical electrode is immersed in the semiconductor substrate in a copper sulfate solution, and is electrically connected to the cathode wire by a layer of the next day so as to be located at The s ions in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer. θ, 5. The method according to item 1 of the scope of the patent application, wherein the above-mentioned dielectric layer 疋 is composed of a silicon oxide material. The method for stopping the exhibition is the method of applying for the first item of the patent scope, wherein the first stop and the second stop are made of silicon nitride material. The method of No. 7 Office is the method of applying for the first item of the patent scope, wherein the first stop and the second stop are made of carbon cutting material. The method described in item 1 of the patent scope of the company, wherein the above-mentioned copper inlay ′, ° constitutes a dielectric interlayer copper connection (via). ^ ^ The method according to item 1 of the scope of patent application, wherein the copper inlaid m structure is a steel conductive plug. A method for manufacturing a copper damascene junction on a semiconductor substrate is provided. The method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; Page 17 α 〇d 26 2 Sixth, the scope of the patent application forms the first stop with the dielectric layer to etch the stop layer and the upper surface; the formation of the upper surface of the resistance; the formation of copper for chemical electricity and filling the first stop of the half A stop layer is formed to form the upper surface of the first structure. A stop layer composed of the material has a difference in etching selectivity ratio from the dielectric layer, where the first stop layer and the dielectric layer are dielectric layers. The second step is to form an opening in the first layer and expose the phase of the semiconductor substrate barrier layer in the opening, and also react with the exposed ECP of the semiconductor substrate seed layer on the barrier layer. In order to form a steel ^ opening. The war fantasy layer is on the surface of the steel seed layer, and the conductive substrate is subjected to chemical mechanical wire = Λ 靥 eight-machine grinding process' to remove a portion of the copper on the upper surface. μ 城 山 ”layer, and removed a portion of the first copper inlay structure in the opening; and a stop layer in the remaining first stop layer and the copper inlay of the first stop waste insect Xi · .j. Layer Xing 4 The first stop layer is used Wherein the square formed with the dielectric substrate 11 in the semiconductor before patentable scope of the method of the first 0, if the application layer, further comprising l > into a variety of elements or steps on the material layer. 12. The method according to item 10 of the patent application scope, wherein the above-mentioned chemical-electricity-red-sequence method immerses the semiconductor substrate in a copper sulfate solution, and electrically connects the 4 copper seed layer to the cathode wire so that Copper sulfate solution Page 18 468262 6. The copper ions in the patent application Fan Gu can be reduced and deposited on the surface of the copper seed layer. 13. The method of claim 10, wherein the above-mentioned dielectric layer is made of a silicon oxide material. 14. The method according to item 10 of the scope of patent application, wherein the first stop layer and the second stop layer are made of a silicon nitride material.俾 丄 If the method of applying for the item 10 of the patent scope, the above-mentioned… and the second stop layer are made of carbonized carbide material. Method, wherein the above-mentioned self-structure is a dielectric interlayer copper connection (v i a). 17. According to the method of applying for item 10 of the patent scope, the Ganshi embedding structure is a copper conductive plug. , On the copper inlay