KR100546940B1 - Method of forming copper wiring in semiconductor device - Google Patents

Method of forming copper wiring in semiconductor device Download PDF

Info

Publication number
KR100546940B1
KR100546940B1 KR1020030046292A KR20030046292A KR100546940B1 KR 100546940 B1 KR100546940 B1 KR 100546940B1 KR 1020030046292 A KR1020030046292 A KR 1020030046292A KR 20030046292 A KR20030046292 A KR 20030046292A KR 100546940 B1 KR100546940 B1 KR 100546940B1
Authority
KR
South Korea
Prior art keywords
copper
copper wiring
insulating film
wiring
diffusion preventing
Prior art date
Application number
KR1020030046292A
Other languages
Korean (ko)
Other versions
KR20050006469A (en
Inventor
박상균
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020030046292A priority Critical patent/KR100546940B1/en
Priority to JP2003424483A priority patent/JP4638140B2/en
Priority to US10/749,022 priority patent/US7199043B2/en
Publication of KR20050006469A publication Critical patent/KR20050006469A/en
Application granted granted Critical
Publication of KR100546940B1 publication Critical patent/KR100546940B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 저유전율 층간 절연막에 형성된 다마신 패턴에 구리층을 매립하고, 화학적 기계적 연마 공정으로 구리층을 연마하여 다마신 패턴 내에 구리 배선을 형성할 때, 구리 배선 상부가 오목한 표면을 이루어 주변의 저유전율 층간 절연막의 표면보다 낮게 형성되도록 화학적 기계적 연마 공정을 과도하게 실시하고, 구리 배선을 안정화 시키면서 구리 배선 상부가 오목한 표면에서 볼록한 표면으로 형성되도록 열처리를 실시하고, 볼록한 표면을 갖는 구리 배선 상부를 포함한 전체 구조상에 구리 확산 방지 절연막을 형성하므로, 구리 확산 방지 절연막이 다마신 패턴 내에 형성될 뿐만 아니라 전체 구조상에도 형성되어 구리 이동을 억제하는 장벽 역할을 하여 배선의 신뢰성을 향상시키고, 또한 구리 배선의 상부를 포함한 전체 면이 단차 없이 평탄화되어 후속으로 실시되는 포토리소그라피 공정 및 식각 공정 등을 용이하게 하여 공정상의 신뢰성을 향상시킬 수 있다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and when a copper layer is embedded in a damascene pattern formed in a low dielectric constant interlayer insulating film, and the copper layer is polished by a chemical mechanical polishing process to form a copper wiring in the damascene pattern In addition, the chemical mechanical polishing process is excessively performed so that the upper portion of the copper wiring is formed concave and lower than the surface of the surrounding low dielectric constant interlayer insulating film. Since the copper diffusion preventing insulating film is formed on the entire structure including the upper portion of the copper wiring having the convex surface, the copper diffusion preventing insulating film is formed not only in the damascene pattern but also on the whole structure, and serves as a barrier to suppress copper migration. Improve the reliability of the wiring, The entire surface, including the upper portion of the re-wiring is flattened with no step difference can be easily to improve the reliability in the process and the like carried out by the subsequent photolithography process and etching process.

구리 배선, 화학적 기계적 연마, 구리 확산 방지 절연막, 스핀-온 증착Copper wiring, chemical mechanical polishing, copper diffusion barrier, spin-on deposition

Description

반도체 소자의 구리 배선 형성 방법{Method of forming copper wiring in semiconductor device} Method of forming copper wiring in semiconductor device             

도 1은 종래 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS The cross section of the element for demonstrating the copper wiring formation method of the conventional semiconductor element.

도 2a 내지 2c는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도.
2A to 2C are cross-sectional views of a device for explaining a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11, 21: 기판 12, 22: 제 1 층간 절연막11, 21: substrate 12, 22: first interlayer insulating film

13, 23: 연마 정지층 14, 24: 다마신 패턴13, 23: abrasive stop layer 14, 24: damascene pattern

15, 25: 구리 확산 방지 도전막 16, 26: 구리 배선15, 25: copper diffusion prevention conductive film 16, 26: copper wiring

17, 27: 제 2 층간 절연막 100, 200: 구리 확산 방지 절연막
17, 27: second interlayer insulating film 100, 200: copper diffusion preventing insulating film

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 다마신 패턴 내에 형성된 구리 배선의 구리 이동을 억제하면서, 이웃하는 구리 배선 상호간의 전기적 단락 현상을 방지할 수 있을 뿐만 아니라 표면 평탄화로 후속 공정을 용이하게 할 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and in particular, while suppressing copper movement of a copper wiring formed in a damascene pattern, it is possible to prevent an electrical short circuit between neighboring copper wirings as well as to perform a subsequent process by surface planarization The present invention relates to a copper wiring forming method of a semiconductor device that can be easily made.

일반적으로, 반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리는 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 사용되고 있다.In general, as the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of devices continues to shrink into the sub-half-micron area, while improving performance and reliability. In terms of circuit density, circuit density is increasing. In response to these demands, copper has a higher melting point than aluminum in forming metal wirings of semiconductor devices, and thus has high resistance to electro-migration (EM), thereby improving reliability of the device and having low specific resistance. The speed of signal transmission can be increased, making it a useful interconnection material for integration circuits.

현재, 사용이 가능한 구리 매립 방법으로는 물리기상증착(PVD)법/리플로우 (reflow), 화학기상증착법(CVD), 전기 도금(Electroplating)법, 무전기 도금(Electroless-plating)법 등이 있으며, 이 중에서 선호되는 방법은 구리 매립 특성이 비교적 양호한 전기 도금법과 화학기상증착법이다.Currently available copper embedding methods include physical vapor deposition (PVD) method / reflow, chemical vapor deposition (CVD), electroplating method, electroless-plating method, etc. Among these, the preferred methods are electroplating and chemical vapor deposition, which have relatively good copper embedding properties.

금속 배선의 재료로 구리를 채용하면서, 반도체 소자의 구리 배선 형성 공정에 하부층과 전기적으로 연결하기 위한 비아 콘택홀 및 금속 배선이 위치되는 트렌치를 동시에 형성시키는 다마신 기법이 널리 적용되고 있으며, 다마신 패턴이 형성 될 층간 절연막으로 유전율이 낮은 저유전 절연물질이 적용되고 있다.While adopting copper as a material for the metal wiring, a damascene technique for forming a via contact hole and a trench in which the metal wiring is located at the same time is electrically applied in the copper wiring forming process of a semiconductor device. A low dielectric insulating material having a low dielectric constant is applied as an interlayer insulating film on which a pattern is to be formed.

비아 콘택홀 및 트렌치로 이루어진 다마신 패턴에 구리 배선을 형성하기 위해서는 상기한 여러 방법으로 다마신 패턴에 구리를 매립시킨 후에 매립된 구리층을 화학적 기계적 연마(CMP) 공정으로 연마하여 이웃하는 구리 배선과 격리(isolation)시킨다.
In order to form a copper wiring in the damascene pattern made of the via contact hole and the trench, the copper layer is buried by the chemical mechanical polishing (CMP) process after embedding the copper in the damascene pattern by various methods described above. Isolate with.

도 1은 종래 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of forming a copper wiring of a conventional semiconductor device.

기판(11) 상에 제 1 층간 절연막(12) 및 연마 정지층(13)을 형성하고, 다마신 기법으로 연마 정지층(13) 및 제 1 층간 절연막(12)을 식각하여 다마신 패턴(14)을 형성한다.The first interlayer insulating layer 12 and the polishing stop layer 13 are formed on the substrate 11, and the damascene pattern 14 is etched by etching the polishing stop layer 13 and the first interlayer insulating layer 12 by a damascene technique. ).

다마신 패턴(14)을 포함한 연마 정지층(13) 표면을 따라 구리 확산 방지 도전막(15)을 형성하고, 다마신 패턴(14)이 충분히 매립되도록 구리층을 형성한다. 화학적 기계적 연마 공정을 연마 정지층(13)이 노출될 때까지 실시하여 다마신 패턴(14) 내에 구리 배선(16)을 형성한다. 이후, 구리 배선(16)을 포함한 전체 구조 상에 구리 확산 방지 절연막(100) 및 제 2 층간 절연막(17)을 형성한다.A copper diffusion preventing conductive film 15 is formed along the surface of the polishing stop layer 13 including the damascene pattern 14, and a copper layer is formed so that the damascene pattern 14 is sufficiently embedded. The chemical mechanical polishing process is performed until the polishing stop layer 13 is exposed to form the copper wiring 16 in the damascene pattern 14. Thereafter, the copper diffusion preventing insulating film 100 and the second interlayer insulating film 17 are formed on the entire structure including the copper wiring 16.

상기한 종래 방법은 구리 배선(16)으로부터 구리 원자가 외부로 확산 되는 것을 방지하기 위하여 구리 확산 방지 도전막(15)과 구리 확산 방지 절연막(100)으로 구리 배선(16)을 밀봉하고 있다. 그런데, 종래 방법에 따라 형성된 구리 배선(16)을 갖는 소자는 구리 원자의 이동(Electro-migration and stress migration)에 의해 발생하는 대부분의 배선 신뢰성 불량이, 지시 부호 "A"에 나타낸 바와 같이, 구리 확산 방지 절연막(100)과 구리 확산 방지 도전막(15) 사이의 계면에서 일어나고 있다. 이러한 현상은 구리 확산 방지 절연막(100)과 하부층(13, 15 및 16)과의 접합성 부족에 기인한다.
In the conventional method described above, the copper wiring 16 is sealed with the copper diffusion preventing conductive film 15 and the copper diffusion preventing insulating film 100 in order to prevent diffusion of copper atoms from the copper wiring 16 to the outside. By the way, in the element having the copper wiring 16 formed according to the conventional method, most of the wiring reliability caused by the electro-migration and stress migration is caused by the copper as indicated by the reference numeral "A". This occurs at the interface between the diffusion barrier insulating film 100 and the copper diffusion barrier conductive film 15. This phenomenon is due to the lack of bonding between the copper diffusion preventing insulating film 100 and the lower layers 13, 15, and 16.

따라서, 본 발명은 종래 문제점인 다마신 패턴 내에 형성된 구리 배선의 구리 이동을 방지하여 소자의 전기적 특성을 향상시키면서, 이웃하는 구리 배선 상호간의 전기적 단락 현상을 방지할 수 있을 뿐만 아니라 표면 평탄화로 후속 공정을 용이하게 할 수 있는 반도체 소자의 구리 배선 형성 방법을 제공함에 그 목적이 있다.
Therefore, the present invention improves the electrical characteristics of the device by preventing the copper migration of the copper wiring formed in the damascene pattern, which is a conventional problem, and can prevent electrical short-circuit between neighboring copper wirings, as well as subsequent process by surface planarization. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a copper wiring of a semiconductor device that can facilitate the process.

이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성 방법은 층간 절연막에 다마신 패턴이 형성된 기판이 제공되는 단계; 상기 다마신 패턴을 포함한 구조 상에 구리 확산 방지 도전막 및 구리층을 형성하는 단계; 화학적 기계적 연마 공정에 의해 구리 배선을 형성하되, 상기 구리 배선의 표면이 상기 층간 절연막의 표면보다 낮게 형성되도록 하는 단계; 및 상기 구리 배선 상부를 포함한 전체 구조 상에 구리 확산 방지 절연막을 형성하는 단계를 포함한다. According to another aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: providing a substrate having a damascene pattern formed on an interlayer insulating film; Forming a copper diffusion preventing conductive film and a copper layer on the structure including the damascene pattern; Forming copper wiring by a chemical mechanical polishing process, wherein the surface of the copper wiring is formed lower than the surface of the interlayer insulating film; And forming a copper diffusion preventing insulating layer on the entire structure including the upper portion of the copper wiring.                     

상기 구리 확산 방지 절연막은 졸이나 겔 형태의 Si, C, N 이 함유된 메칠, 벤조클로르부탄, 폴리이미드, 아릴에테르, 하이드로겐 실세스퀴옥산을 스핀-온 증착법으로 도포한 후, 도포된 막의 치밀화를 위해 열처리하여 형성한다. 여기서, 상기 열처리는 N2, Ar, H2 또는 He와 같은 불활성 기체나 이들의 혼합 기체를 이용하여 100 ~ 500℃의 온도 범위에서 실시하거나, 100 ~ 500℃의 온도 범위에서 진공 상태로 실시한다.
The copper diffusion preventing insulating film is formed by applying spin-on deposition of methyl, benzochlorbutane, polyimide, arylether, and hydrogen silsesquioxane in a sol or gel form, including Si, C, and N. It is formed by heat treatment for densification. Here, the heat treatment is carried out in a temperature range of 100 ~ 500 ℃ using an inert gas such as N 2 , Ar, H 2 or He or a mixture of these, or in a vacuum at a temperature range of 100 ~ 500 ℃. .

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

도 2a 내지 2c는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2C are cross-sectional views of devices for describing a method of forming copper wirings of a semiconductor device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 기판(21) 상에 제 1 층간 절연막(22) 및 연마 정지층(23)을 형성하고, 다마신 기법으로 연마 정지층(23) 및 제 1 층간 절연막(22)을 식각하여 다마신 패턴(24)을 형성한다. 다마신 패턴(24)을 포함한 연마 정지층(23) 표면을 따라 구리 확산 방지 도전막(25)을 형성하고, 다마신 패턴(24)이 충분히 매립되 도록 구리층을 형성한다. 화학적 기계적 연마 공정을 실시하여 다마신 패턴(24) 내에 구리 배선(26)을 형성하되, 구리 배선(26) 상부가 오목한 표면으로 되고 주변의 제 1 층간 절연막(22)의 표면보다 낮게 형성되도록 화학적 기계적 연마 공정을 과도하게 실시한다. 화학적 기계적 연마 공정을 완료한 후 세정 공정을 실시한다.Referring to FIG. 2A, the first interlayer insulating layer 22 and the polishing stop layer 23 are formed on the substrate 21, and the polishing stop layer 23 and the first interlayer insulating layer 22 are etched by a damascene technique. To form a damascene pattern 24. A copper diffusion preventing conductive film 25 is formed along the surface of the polishing stop layer 23 including the damascene pattern 24, and a copper layer is formed to sufficiently fill the damascene pattern 24. A chemical mechanical polishing process is performed to form a copper wiring 26 in the damascene pattern 24, wherein the upper portion of the copper wiring 26 becomes a concave surface and is chemically formed below the surface of the surrounding first interlayer insulating film 22. Excessive mechanical polishing process. After the chemical mechanical polishing process is completed, the cleaning process is performed.

상기에서, 제 1 층간 절연막(22)은 배선과 배선 사이의 기생 캐패시터로 인한 문제를 해결하기 위해 저유전율을 갖는 물질로 형성하는데, 예를 들어, 유전 상수값이 1.5 내지 4.5 대역의 SiO2 계열에 H, F, C, CH3 등이 부분적으로 결합되어 있는 물질이나, C-H를 기본 구조로 하는 SiLKTM제품, FlareTM제품 등의 유기 물질(organic material)이나, 이들 물질의 유전 상수값을 낮추기 위해 이들 물질의 기공도(porosity)를 증가시킨 다공성(porous) 물질로 형성한다.In the above, the first interlayer insulating layer 22 is formed of a material having a low dielectric constant to solve the problem caused by the parasitic capacitor between the wiring, for example, the SiO 2 series having a dielectric constant value of 1.5 to 4.5 band Lowering the dielectric constant value of organic materials such as a substance in which H, F, C, CH 3, etc. are partially bonded to, a SiLK TM product based on CH, and a Flare TM product In order to increase the porosity of these materials.

연마 정지층(23)은 탄소를 함유하지 않은 산화물로 형성하거나, 구리 확산 방지 특성을 가지도록 화학기상증착법(CVD)으로 질소를 함유한 실리콘 질화물 및 실리콘 질화 산화물 또는 탄소를 함유한 실리콘 카바이드 계열의 물질로 형성한다.The polishing stop layer 23 may be formed of an oxide containing no carbon, or may be formed of silicon nitride containing silicon nitride and silicon nitride oxide or silicon carbide containing carbon by chemical vapor deposition (CVD) to have copper diffusion preventing properties. Form into material.

구리 확산 방지 도전막(25)은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN 중 어느 하나로 형성한다.The copper diffusion preventing conductive film 25 is formed of any one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, and CVD WN.

세정 공정은 구리 배선(26)의 표면이 주변의 제 1 층간 절연막(22)의 표면보다 더욱 낮게 형성되도록 세정액에 질산 등을 소량 함유시켜 진행한다.The cleaning process proceeds by containing a small amount of nitric acid or the like in the cleaning liquid so that the surface of the copper wiring 26 is formed lower than the surface of the surrounding first interlayer insulating film 22.

도 2b를 참조하면, 제 1 열처리를 실시하여 구리 배선(26)을 안정화 시키며, 이때 구리 배선(26)의 표면은 열에 의한 표면 에너지를 최소화하기 위해 상부가 오목한 표면에서 볼록한 표면으로 된다.Referring to FIG. 2B, a first heat treatment is performed to stabilize the copper wiring 26, wherein the surface of the copper wiring 26 becomes a convex surface at the top concave surface to minimize surface energy due to heat.

상기에서, 제 1 열처리는 2가지 방법으로 실시하는데, 첫번째 방법은 N2, Ar, H2 또는 He 등의 불활성 기체나 이들의 혼합 기체를 이용하여 100 ~ 500℃의 온도 범위에서 실시하는 것이고, 두번째 방법은 N2, Ar, H2 또는 He 등의 불활성 기체나 이들의 혼합 기체를 이용하거나, 진공 상태에서 200 ~ 700℃의 온도 범위에서 5분 이내, 바람직하게는 1 ~ 5분 동안 급속 열처리로 실시하는 것이다.In the above, the first heat treatment is carried out in two ways, the first method is carried out in a temperature range of 100 ~ 500 ℃ using an inert gas such as N 2 , Ar, H 2 or He or a mixture thereof, The second method uses an inert gas such as N 2 , Ar, H 2 or He or a mixture of these, or rapid heat treatment for 5 minutes, preferably 1 to 5 minutes, in a temperature range of 200 to 700 ° C. in a vacuum state. It is to be carried out.

도 2c를 참조하면, 구리 배선(26)의 표면에 생성되는 산화층과 같은 불순물들을 제거하기 위하여 플라즈마 처리하고, 볼록한 표면을 갖는 구리 배선(26) 상부를 포함한 전체 구조상에 구리 확산 방지 절연막(200)을 형성한다. 구리 확산 방지 절연막(200)을 포함한 전체 구조 상에 제 2 층간 절연막(27)을 형성한다.Referring to FIG. 2C, a copper diffusion preventing insulating layer 200 is formed on the entire structure including the upper portion of the copper wiring 26 having a plasma treatment to remove impurities such as an oxide layer formed on the surface of the copper wiring 26 and having a convex surface. To form. The second interlayer insulating film 27 is formed on the entire structure including the copper diffusion preventing insulating film 200.

상기에서, 플라즈마 처리는 질소와 수소를 함유한 혼합 가스, 암모니아 계열의 가스 또는 질소가 포함되지 않은 수소/불활성 기체의 혼합 가스를 분위기 가스로 사용하여 100 ~ 350℃의 온도 범위에서 실시한다.In the above, the plasma treatment is carried out in a temperature range of 100 ~ 350 ℃ using a mixed gas containing nitrogen and hydrogen, ammonia-based gas or a mixed gas of hydrogen / inert gas not containing nitrogen as the atmosphere gas.

구리 확산 방지 절연막(200)은 구리 확산 방지 특성이 있으면서 표면 평탄화가 용이한 물질로 형성한다. 즉, 구리 확산 방지 절연막(200)은 그 원료로 유동성이 우수한 졸(sol)이나 겔(gel) 형태의 Si, C, N 등이 함유된 메칠(Methyl), 벤조클로르부탄(Benzochlorobutane), 폴리이미드(Polyimide), 아릴에테르(arylethers), 하이드로겐 실세스퀴옥산(Hydrogen Silsesquioxane) 등의 소스를 이용하여 300Å 이상 바람직하게는 300 ~ 700Å의 두께로 스핀-온 증착(Spin-on deposition) 방식으로 도포하고, 도포된 막을 치밀화하기 위해 제 2 열처리를 실시하여 형성한다. 제 2 열처리는 2가지 방법으로 실시하는데, 첫번째 방법은 N2, Ar, H2 또는 He 등의 불활성 기체나 이들의 혼합 기체를 이용하여 100 ~ 500℃의 온도 범위에서 1분 이상, 바람직하게는 1 ~ 5분 동안 실시하는 것이고, 두번째 방법은 진공 상태에서 100 ~ 500℃의 온도 범위에서 1분 이상, 바람직하게는 1 ~ 5분 동안 실시하는 것이다.The copper diffusion preventing insulating layer 200 is formed of a material having copper diffusion preventing properties and easy surface planarization. That is, the copper diffusion barrier insulating film 200 is methyl, benzochlorobutane, polyimide containing sol, gel, Si, C, N, etc., which have excellent fluidity as a raw material. (Polyimide), arylethers, hydrogen silsesquioxane (Hydrogen Silsesquioxane), etc. using a source such as spin-on deposition (Spin-on deposition) to a thickness of 300 Å or more, preferably 300 ~ 700 Å In order to densify the coated film, a second heat treatment is performed. The second heat treatment is carried out in two ways, the first method using an inert gas such as N 2 , Ar, H 2 or He or a mixture of these gases in a temperature range of 100 ~ 500 ℃ at least one minute, preferably It is carried out for 1 to 5 minutes, the second method is to perform for 1 minute or more, preferably 1 to 5 minutes in a temperature range of 100 ~ 500 ℃ in a vacuum state.

제 2 층간 절연막(27)은 다층 금속 배선 구조일 경우에는 전술한 제 1 층간 절연막(22)과 같이 배선과 배선 사이의 기생 캐패시터로 인한 문제를 해결하기 위해 저유전율을 갖는 물질로 형성하는 것이 바람직하지만, 단층 금속 배선 구조일 경우에는 통상적으로 반도체 소자의 층간 절연막으로 적용되는 다른 절연물로도 형성할 수 있다.
In the case of the multi-layered metal wiring structure, the second interlayer insulating film 27 is preferably formed of a material having a low dielectric constant to solve the problem caused by the parasitic capacitor between the wirings, as in the first interlayer insulating film 22 described above. However, in the case of a single-layer metal wiring structure, it may also be formed of other insulators that are typically applied as an interlayer insulating film of a semiconductor device.

상술한 바와 같이, 본 발명은 구리 확산 방지 절연막이 다마신 패턴 내에 형성될 뿐만 아니라 전체 구조상에도 형성되어 구리 이동을 억제하는 장벽 역할을 하여 배선의 신뢰성을 향상시키고, 또한 구리 배선의 상부를 포함한 전체 면이 단차 없이 평탄화되어 후속으로 실시되는 포토리소그라피 공정 및 식각 공정 등을 용이하게 하여 공정상의 신뢰성을 향상시킬 수 있다. 따라서 본 발명은 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있으며, 소자의 고집적화 실현을 가능하게 한다.As described above, in the present invention, not only the copper diffusion preventing insulating layer is formed in the damascene pattern but also in the overall structure, and serves as a barrier to suppress copper movement, thereby improving the reliability of the wiring, and also including the entire top of the copper wiring. The surface is flattened without a step, thereby facilitating a subsequent photolithography process, an etching process, and the like, thereby improving process reliability. Therefore, the present invention can improve the electrical characteristics and reliability of the device, and enables high integration of the device.

Claims (5)

층간 절연막에 다마신 패턴이 형성된 기판이 제공되는 제 1 단계;A first step of providing a substrate having a damascene pattern formed on the interlayer insulating film; 상기 다마신 패턴을 포함한 구조 상에 구리 확산 방지 도전막 및 구리층을 형성하는 제 2 단계;A second step of forming a copper diffusion preventing conductive film and a copper layer on the structure including the damascene pattern; 화학적 기계적 연마 공정에 의해 구리 배선을 형성하되, 상기 구리 배선의 표면이 상기 층간 절연막의 표면보다 낮게 형성되도록 하는 제 3 단계; 및Forming a copper wiring by a chemical mechanical polishing process, wherein the surface of the copper wiring is formed lower than the surface of the interlayer insulating film; And 상기 구리 배선 상부를 포함한 전체 구조 상에 구리 확산 방지 절연막을 형성하는 제 4 단계를 포함하며,A fourth step of forming a copper diffusion preventing insulating layer on the entire structure including the upper portion of the copper wiring, 상기 구리 확산 방지 절연막은 구리 확산 방지 특성이 있으면서 유동성이 우수한 물질을 스핀-온 증착법으로 도포한 후, 열처리하여 형성하는 반도체 소자의 구리 배선 형성 방법.The copper diffusion preventing insulating film is a copper wiring forming method of a semiconductor device which is formed by applying a material having excellent copper diffusion preventing properties and excellent fluidity by spin-on deposition method, and then heat treatment. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 구리 확산 방지 절연막은 그 원료로 졸이나 겔 형태의 Si, C, N 이 함유된 메칠, 벤조클로르부탄, 폴리이미드, 아릴에테르, 하이드로겐 실세스퀴옥산을 이용하는 반도체 소자의 구리 배선 형성 방법.The copper diffusion preventing insulating film is a copper wiring forming method of a semiconductor device using a sol or gel-containing methyl, benzochlorbutane, polyimide, arylether, hydrogen silsesquioxane as a raw material. 제 1 항에 있어서,The method of claim 1, 상기 열처리는 N2, Ar, H2 또는 He와 같은 불활성 기체나 이들의 혼합 기체를 이용하여 100 ~ 500℃의 온도 범위에서 실시하는 반도체 소자의 구리 배선 형성 방법.The heat treatment is a copper wiring forming method of a semiconductor device to be carried out in a temperature range of 100 ~ 500 ℃ using an inert gas such as N 2 , Ar, H 2 or He or a mixed gas thereof. 제 1 항에 있어서,The method of claim 1, 상기 열처리는 100 ~ 500℃의 온도 범위에서 진공 상태로 실시하는 반도체 소자의 구리 배선 형성 방법.The heat treatment is a copper wiring forming method of a semiconductor device to be carried out in a vacuum state in a temperature range of 100 ~ 500 ℃.
KR1020030046292A 2003-07-09 2003-07-09 Method of forming copper wiring in semiconductor device KR100546940B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020030046292A KR100546940B1 (en) 2003-07-09 2003-07-09 Method of forming copper wiring in semiconductor device
JP2003424483A JP4638140B2 (en) 2003-07-09 2003-12-22 Method for forming copper wiring of semiconductor element
US10/749,022 US7199043B2 (en) 2003-07-09 2003-12-30 Method of forming copper wiring in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030046292A KR100546940B1 (en) 2003-07-09 2003-07-09 Method of forming copper wiring in semiconductor device

Publications (2)

Publication Number Publication Date
KR20050006469A KR20050006469A (en) 2005-01-17
KR100546940B1 true KR100546940B1 (en) 2006-01-26

Family

ID=37220281

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030046292A KR100546940B1 (en) 2003-07-09 2003-07-09 Method of forming copper wiring in semiconductor device

Country Status (1)

Country Link
KR (1) KR100546940B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101607802B1 (en) 2012-04-27 2016-03-30 도쿄엘렉트론가부시키가이샤 Film-forming method and film-forming device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744420B1 (en) * 2006-08-29 2007-07-30 동부일렉트로닉스 주식회사 Semiconductor device and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101607802B1 (en) 2012-04-27 2016-03-30 도쿄엘렉트론가부시키가이샤 Film-forming method and film-forming device

Also Published As

Publication number Publication date
KR20050006469A (en) 2005-01-17

Similar Documents

Publication Publication Date Title
US6057226A (en) Air gap based low dielectric constant interconnect structure and method of making same
US6972253B2 (en) Method for forming dielectric barrier layer in damascene structure
US7871923B2 (en) Self-aligned air-gap in interconnect structures
US5858869A (en) Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers
US6577011B1 (en) Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6566283B1 (en) Silane treatment of low dielectric constant materials in semiconductor device manufacturing
US7224068B2 (en) Stable metal structure with tungsten plug
US20040232552A1 (en) Air gap dual damascene process and structure
US20100055898A1 (en) Method for fabricating an integrated circuit
US7834459B2 (en) Semiconductor device and semiconductor device manufacturing method
US20070085209A1 (en) Anchored damascene structures
US6495448B1 (en) Dual damascene process
JP4638140B2 (en) Method for forming copper wiring of semiconductor element
KR100546209B1 (en) Copper wiring formation method of semiconductor device
KR100546940B1 (en) Method of forming copper wiring in semiconductor device
US6784095B1 (en) Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing
US7250364B2 (en) Semiconductor devices with composite etch stop layers and methods of fabrication thereof
KR100399909B1 (en) Method of forming inter-metal dielectric in a semiconductor device
KR100688758B1 (en) Method for forming gap fill of metal line for semiconductor
KR20100026399A (en) Metal wiring of semiconductor device and method for forming the same
KR100960934B1 (en) Metal wiring of semiconductor device and method of manufacturing the same
KR20050006468A (en) Method of forming copper wiring in semiconductor device
KR100645225B1 (en) Method for forming metal wiring for semiconductor device and semiconductor device therefore
KR100784105B1 (en) Method of manufacturing a semiconductor device
KR20060118257A (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121210

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20131217

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20141222

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20151217

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20161220

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20171218

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20181218

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20191217

Year of fee payment: 15