CN1249537A - 多层布线结构及其生产方法 - Google Patents
多层布线结构及其生产方法 Download PDFInfo
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- CN1249537A CN1249537A CN99119454A CN99119454A CN1249537A CN 1249537 A CN1249537 A CN 1249537A CN 99119454 A CN99119454 A CN 99119454A CN 99119454 A CN99119454 A CN 99119454A CN 1249537 A CN1249537 A CN 1249537A
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- Prior art keywords
- wiring layer
- metal
- layer
- insulating barrier
- hole
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- 238000000034 method Methods 0.000 title claims description 54
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 136
- 229910052751 metal Inorganic materials 0.000 claims description 136
- 230000004888 barrier function Effects 0.000 claims description 108
- 239000000758 substrate Substances 0.000 claims description 68
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 49
- 238000009713 electroplating Methods 0.000 claims description 41
- 230000015572 biosynthetic process Effects 0.000 claims description 36
- 229910052802 copper Inorganic materials 0.000 claims description 35
- 239000010949 copper Substances 0.000 claims description 35
- 229910045601 alloy Inorganic materials 0.000 claims description 27
- 239000000956 alloy Substances 0.000 claims description 27
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- 238000002360 preparation method Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 239000000945 filler Substances 0.000 description 13
- 238000007747 plating Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
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- 210000000988 bone and bone Anatomy 0.000 description 3
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- 230000005611 electricity Effects 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000006263 metalation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920005575 poly(amic acid) Polymers 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Images
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09554—Via connected to metal substrate
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10924—Leads formed from a punched metal foil
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (38)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP271239/1998 | 1998-09-25 | ||
JP27123998A JP3169907B2 (ja) | 1998-09-25 | 1998-09-25 | 多層配線構造およびその製造方法 |
JP271239/98 | 1998-09-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1249537A true CN1249537A (zh) | 2000-04-05 |
CN1154185C CN1154185C (zh) | 2004-06-16 |
Family
ID=17497302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB991194543A Expired - Fee Related CN1154185C (zh) | 1998-09-25 | 1999-09-27 | 多层布线结构及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US6274404B1 (zh) |
EP (1) | EP0989610A3 (zh) |
JP (1) | JP3169907B2 (zh) |
KR (1) | KR100341153B1 (zh) |
CN (1) | CN1154185C (zh) |
TW (1) | TW451262B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100336425C (zh) * | 2003-06-11 | 2007-09-05 | 三洋电机株式会社 | 混合集成电路装置 |
CN101989645A (zh) * | 2009-07-30 | 2011-03-23 | 索尼公司 | 制造电路板的方法以及电路板 |
CN106783634A (zh) * | 2016-12-26 | 2017-05-31 | 通富微电子股份有限公司 | 一种扇出封装器件及其封装方法 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3575001B2 (ja) | 1999-05-07 | 2004-10-06 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ及びその製造方法 |
JP3398721B2 (ja) * | 1999-05-20 | 2003-04-21 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ及びその製造方法 |
US7173336B2 (en) * | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
JP2002076250A (ja) * | 2000-08-29 | 2002-03-15 | Nec Corp | 半導体装置 |
JP3840921B2 (ja) * | 2001-06-13 | 2006-11-01 | 株式会社デンソー | プリント基板のおよびその製造方法 |
US7081373B2 (en) * | 2001-12-14 | 2006-07-25 | Staktek Group, L.P. | CSP chip stack with flex circuit |
JP4283514B2 (ja) * | 2002-09-24 | 2009-06-24 | 株式会社日立製作所 | 電子回路装置 |
JP2005191148A (ja) * | 2003-12-24 | 2005-07-14 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
TWI280657B (en) * | 2004-05-28 | 2007-05-01 | Sanyo Electric Co | Circuit device |
JP2005347353A (ja) * | 2004-05-31 | 2005-12-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
US8436250B2 (en) * | 2006-11-30 | 2013-05-07 | Sanyo Electric Co., Ltd. | Metal core circuit element mounting board |
US9466545B1 (en) | 2007-02-21 | 2016-10-11 | Amkor Technology, Inc. | Semiconductor package in package |
US8138607B2 (en) * | 2009-04-15 | 2012-03-20 | International Business Machines Corporation | Metal fill structures for reducing parasitic capacitance |
US20110048505A1 (en) * | 2009-08-27 | 2011-03-03 | Gabriela Bunea | Module Level Solution to Solar Cell Polarization Using an Encapsulant with Opened UV Transmission Curve |
US8377738B2 (en) | 2010-07-01 | 2013-02-19 | Sunpower Corporation | Fabrication of solar cells with counter doping prevention |
JP5848976B2 (ja) * | 2012-01-25 | 2016-01-27 | 新光電気工業株式会社 | 配線基板、発光装置及び配線基板の製造方法 |
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- 1998-09-25 JP JP27123998A patent/JP3169907B2/ja not_active Expired - Fee Related
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- 1999-09-22 US US09/401,789 patent/US6274404B1/en not_active Expired - Lifetime
- 1999-09-22 KR KR1019990041126A patent/KR100341153B1/ko not_active IP Right Cessation
- 1999-09-22 TW TW088116468A patent/TW451262B/zh not_active IP Right Cessation
- 1999-09-24 EP EP99118900A patent/EP0989610A3/en not_active Withdrawn
- 1999-09-27 CN CNB991194543A patent/CN1154185C/zh not_active Expired - Fee Related
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100336425C (zh) * | 2003-06-11 | 2007-09-05 | 三洋电机株式会社 | 混合集成电路装置 |
CN101989645A (zh) * | 2009-07-30 | 2011-03-23 | 索尼公司 | 制造电路板的方法以及电路板 |
CN106783634A (zh) * | 2016-12-26 | 2017-05-31 | 通富微电子股份有限公司 | 一种扇出封装器件及其封装方法 |
CN106783634B (zh) * | 2016-12-26 | 2019-09-20 | 通富微电子股份有限公司 | 一种扇出封装器件及其封装方法 |
Also Published As
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TW451262B (en) | 2001-08-21 |
EP0989610A3 (en) | 2003-11-12 |
JP2000100989A (ja) | 2000-04-07 |
EP0989610A2 (en) | 2000-03-29 |
JP3169907B2 (ja) | 2001-05-28 |
KR100341153B1 (ko) | 2002-06-20 |
CN1154185C (zh) | 2004-06-16 |
US20010038149A1 (en) | 2001-11-08 |
US6274404B1 (en) | 2001-08-14 |
US6351026B2 (en) | 2002-02-26 |
KR20000023423A (ko) | 2000-04-25 |
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