CN1234606A - 用于制造BEOL布线的小接触通孔的高生产率Al-Cu薄膜溅射工艺 - Google Patents
用于制造BEOL布线的小接触通孔的高生产率Al-Cu薄膜溅射工艺 Download PDFInfo
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- 229910052782 aluminium Inorganic materials 0.000 title claims 2
- 229910052802 copper Inorganic materials 0.000 title claims 2
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- 238000004544 sputter deposition Methods 0.000 claims abstract description 65
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- 239000002184 metal Substances 0.000 claims abstract description 47
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 2
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
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Abstract
一种薄膜溅射工艺,其中:首先在低温和低溅射功率下,在通孔的侧壁上淀积第一Al-Cu膜,然后在高温和高溅射功率下,在该第一Al-Cu膜上淀积第二Al-Cu膜,形成填充该通孔的金属互连层。溅射是在同一溅射室内的低温和高温的两个步骤内完成的。在低温和低溅射功率下的淀积在该通孔内形成良好覆盖,在高温和高溅射功率下的淀积减少了工艺时间。
Description
本发明涉及一种制造大规模集成半导体器件的方法,特别涉及以高生产率在小通孔内淀积Al-Cu薄膜的工艺。
对于大规模集成半导体器件,例如目前的256 Mb DRAM,要求填充非常小的通孔,以构成多级互连的第二级(最顶层)。一种Al-Cu的溅射工艺,可在一个步骤中形成第二级互连和在第一与第二级互连之间的接触,它可减少工艺时间并降低成本,因此被用于64-Mb DRAM和CMOS逻辑电路的BEOL(线后端)布线工艺。
但是,对于256-Mb DRAM,该通孔的尺寸按比例缩小到0.8μm以下。因此常规的Al-Cu溅射工艺不能不留下空隙地完全填充通孔。该空隙会大大降低金属线路可靠性。在可靠性测试中,对第二级金属和第一与第二级金属之间的接触施加电流和温度,在所有硬件上都观察到了早期缺陷。由于特别在最高金属层上不能进行高温(超过450℃)热回流工艺,因此难于通过后处理去除空隙。
至于填充小的且长宽比大的通孔以形成互连层并抑制空隙形成的技术,已知的有远掷溅射(long throw sputfering)和准直溅射。远掷溅射是一个通过使靶至晶片的距离延长以降低到达晶片的金属颗粒的水平分量而在一深通孔的底部淀积一金属膜的工艺。例如,在《真空科学和技术杂志》B Vol. 13(4)(1995) p.1906中,N.Motegi等人已描述了该远掷溅射工艺。与准直溅射比较,远掷溅射工艺具有可获得相对高的溅射速率和良好靶效率的优点。
另一方面,准直溅射是一个采用放置在靶和晶片之间的准直器并只使金属颗粒的垂直分量从靶射出穿过该准直器而到达该深接触孔的底部的工艺。例如在美国专利No.4,724,060、《真空科学和技术杂志》A Vol. 9(2) (1991) P.261中S.M.Rossnagel等人以及《薄固体膜》Vol. 247 (1994) P. 104中B.Vollmer等人描述了该准直溅射工艺。该准直溅射工艺具有良好的中心边缘一致性。
在淀积用于256-Mb DRAM的第二级金属(顶层)的工艺中,采用在低温大约150℃下长时间内淀积Al-Cu薄膜的远掷溅射或准直溅射。远掷溅射和准直溅射均可填充通孔而不留下空隙,可通过可靠性测试。
但是,远掷溅射和准直溅射工艺只利用了由靶射出的金属颗粒的垂直分量,这样,与普通溅射工艺相比,就需要较长时间来淀积金属膜。为了淀积1μm厚的Al-Cu膜,需要6至7分钟淀积时间。为此,与采用普通溅射工艺的情况相比,晶片产量变低了,导致制造成本提高。此外,对于准直溅射,金属也会淀积在准直器上,致使准直器常常阻塞。准直器阻塞改变了溅射速度。这样,必须更换一新准直器,由于准直器更换造成停工期,进一步降低了产量。
因此,本发明的一个目的是提供一种半导体器件制造方法,它可提高生产量并抑制空隙形成和降低制造成本。
通过下述半导体器件制造方法可实现本发明目的,该方法包括:第一步,在半导体衬底的表面上形成绝缘膜;第二步,在该绝缘膜内形成一开口;第三步,将半导体衬底放置在溅射设备的室中,在第一温度下,在该绝缘膜上和该开口内形成第一金属层;以及第四步,该半导体衬底放置在溅射设备的上述室中,在高于第一温度的第二温度下,在第一金属层上形成第二金属层。
根据该制造方法,在第一温度(低温)下形成第一金属层提供对小通孔的良好覆盖,在第二温度(高温)下形成第二金属层以提供高淀积速率。填充该开口的金属层在短时间内有效形成,并减少了空隙的形成。这样,由于可以使用常规的溅射设备形成金属层,因此消除了在使用远掷溅射和准直溅射时遇到的问题,保证高产量和低成本,并且不留下空隙。
本发明的其他目的和优点在下面的说明中得到阐明,从说明书中可以部分地看出,也可通过本发明的实施而理解。可通过由附后的权利要求书特别指出的手段和组合来实现和获得本发明的目的和优点。
结合上面的概括描述和下面最佳实施例的详细描述,并参照作为说明书的一部分的附图,解释本发明的原理。
图1A至1D是根据本发明一实施例的按形成第一和第二层金属的步骤顺序的剖面图。
本发明的半导体器件制造方法采用常规的溅射设备,并在控制三个重要参数:室内压力、背侧(backside)Ar气体的流速和溅射功率的情况下通过多于一个步骤在相同室内淀积由金属制成的薄膜来实现其溅射工艺。通过打开或关闭背侧的Ar气体来控制晶片的温度,通过改变溅射功率来控制淀积速度。首先,关闭背侧的Ar气体,在低于150℃的低温和低溅射功率下,淀积几百nm厚的Al-Cu膜。接着,打开背侧Ar气体,在350℃较高温加热晶片,然后,在基于高溅射功率的一高淀积速率下淀积Al-Cu膜。结果,依次形成包括低温和高温金属颗粒的两类金属薄膜。低温、低溅射功率工艺在通孔内进行良好覆盖,但是需要长淀积时间。另一方面,高温、高溅射功率溅射工艺可减少淀积时间,但是在通孔内进行较差覆盖。这样,结合进行两个工艺。即,首先实施低温低溅射功率工艺部分填充通孔,然后进行高温高溅射功率形成一金属薄膜,由此,保证通孔内的良好覆盖并减少淀积时间。此外,在常规的溅射设备中的A1-Cu淀积室可用于满足具有小填充通孔的256-Mb DRAM的需要,并保证足够的可靠性。这样,可以形成高质量BEOL布线而不降低生产率和提高制造成本。
下面将说明应用上述的溅射工艺形成半导体器件内的互连。
图1A至1D图示了根据本发明的半导体器件的制造步骤,特别是形成第一和第二级互连的步骤。
首先,如图1A所示,在形成于半导体晶片11的表面上的绝缘层12上通过溅射形成Ti膜13、TiN膜14、Al-Cu膜15、Ti膜16和TiN膜17。通过光刻和RIE技术,对这些膜构图以构成第一层金属互连(M1)18。Ti膜13、TiN膜14、Al-Cu膜15、Ti膜16和TiN膜17的厚度,例如,分别是10nm、10nm、230nm、5nm和40nm。此后,在400℃的成膜气体内进行20分钟的烧结退火。
接着,如图1B所示,在第一级金属互连层18上和绝缘膜12上形成60nm厚的层间绝缘膜19,然后通过光刻和RIE技术在层间绝缘膜19上形成开口(通孔)20。
然后,如图1C所示,在层间绝缘膜19上和通孔20内形成第二金属互连层(M2)21。为形成第二金属互连层21,首先在Ti/TiN溅射室内依次形成25nm厚的Ti膜22和25nm厚的TiN膜23然后在具有设定在较高温度150℃的Al溅射室内,不在晶片背侧施加加热Ar气体流,以3.2kW的低溅射功率溅射Al-Cu55秒钟。这样,在低温(可以是远远低于150℃的50℃或室温)形成300nm厚的Al-Cu膜24-1。在这种情况下,由于没有背侧Ar气体流,即使在350℃的高温,晶片温度也将低于150℃,因为加热器和晶片之间的热传导率较差,导致了类似结果。根据这个方法,加热器升温所需的时间进一步降低。此后,引入加热Ar气体45秒钟将晶片加热至350℃。然后,在加热Ar气流下,以12.7kW的高溅射功率溅射Al-Cu 32秒钟。这样,在高温下形成700nm厚的Al-Cu膜24-2。结果形成了总厚度为1μm的Al-Cu膜24。此后,在Ti/TiN溅射室内形成37.5nm厚的TiN膜25。
接着,如图1D所示,采用光刻和RIE技术对第二金属互连层21构图,由此完成多级布线工艺。
根据上述的制造方法,由在低温下形成的Al-Cu膜24-1填充通孔20以实现良好覆盖,然后在高温形成Al-Cu膜24-2以实现高淀积速率。因此,可在短时间内形成第二金属互连层21,同时抑制通孔20内空隙的形成。这样,可消除采用远掷溅射或准直溅射中遇到的问题,可确保高生产率和低成本。尤其是,远掷溅射和准直溅射形成1μm厚的金属互连层需要6至7分钟,而上述的发明方法可在低于3分钟内形成同样厚度的金属互连层,极大地提高了生产率。此外,与准直溅射不同,本发明方法不会由于部件消耗提高成本,也不会由于置换消耗部件而造成停机时间增加。从这些方面看,本发明方法可降低成本并提高生产率。
根据各制造方法在256-Mb DRAM BEOL布线的第一和第二级互连之间形成通孔接触,并进行应力测试。第二级互连包括以下列次序叠在一起的25nm厚的Ti膜、25nm厚的TiN膜、1μm厚的Al-Cu膜和37.5nm厚的TiN膜。根据下面的方法形成该Al-Cu膜:
(a)将溅射室内温度设定在350℃,采用标准溅射设备进行溅射。
(b)在根据本发明的多步骤中进行溅射。
(c)将室内温度设定在150℃,进行远掷溅射。
(d)进行准直溅射。
当在测试温度为245℃和第一与第二级互连之间的电流为11.00mA的条件下,芯片显示接触电阻增加20%时,该芯片视为有缺陷。观察到根据本方法(a)制成通孔接触的50个芯片中有6片有早期缺陷(产生于开始测试后的5小时内)。在根据(b)、(c)和(d)中的每个方法制造的50个芯片上没有发现早期缺陷。方法(b)所需工艺时间少于3分钟,而方法(c)和(d)每个都需要6到7分钟,因为Al-Cu膜淀积速度很低。
根据本发明制造的半导体器件由于减少工艺时间而大大降低成本。由于不需要置换准直器使得可消耗部件的费用减少,并且使靶置换的频率降低。
利用在溅射设备内打开和关闭背侧的Ar气体以改变由加热器产生的热导率的例子描述了本发明的实施例,但这不是限制性的。加热器和晶片之间的热导率通过打开和关闭溅射设备的静电吸盘同样可以改变。此外,为了形成1μm厚的Al-Cu膜,已经描述了上述实施例,即首先在低温和低溅射功率下淀积300nm厚的Al-Cu膜24-1,然后在高温和高溅射功率下淀积700nm厚的Al-Cu膜24-2。但是应该指出的是,在低温和低溅射功率下形成的Al-Cu膜厚度可在300至700nm的范围内,在高温和高溅射功率下淀积的Al-Cu膜厚度可在700至300nm的范围内。如果在低温和低溅射功率下淀积的Al-Cu膜厚度低于300nm,则空隙的抑制效果就会削弱。另一方面,如果该厚度高于700nm,溅射时间就会增加。这样,需要结合考虑通孔的大小和深度、在通孔内所需的覆盖以及制造时间,来确定每个Al-Cu膜厚度和溅射功率。
如上所述,根据本发明,提供了一种半导体器件的制造方法,它可提高生产率,降低制造成本,并抑制空隙的形成。
对本领域技术人员来说会很容易发现其它优点和变形。因此,本发明在广义上不局限于这里的具体详述和所示典型实施例。在不背离由附后的权利要求和其等同物所限定的总的发明构思的前提下可以做出种种变更。
Claims (15)
1.一种半导体器件制造方法,包括:
第一步,在半导体衬底的表面上形成绝缘膜;
第二步,在该绝缘膜上形成开口;
第三步,将该半导体衬底放置在溅射设备的室中,在第一温度下,在该绝缘膜上和该开口内形成第一金属层;以及
第四步,将该半导体衬底放置在该溅射设备的该室中,在高于第一温度的第二温度下,在该第一金属层上形成第二金属层。
2.如权利要求1所述的方法,其中:所述的第三步在低溅射功率下进行,所述的第四步在高溅射功率下进行。
3.如权利要求1所述的方法,其中:通过改变由设在该溅射设备的该室内的加热器产生的热导率来形成第一温度和第二温度间的差别。
4.如权利要求3所述的方法,其中:通过在第三步内关闭溅射设备内加热器背侧的Ar气体和在第四步内打开该背侧的Ar气体来改变由加热器产生的热导率。
5.如权利要求3所述的方法,其中:通过在第三步内断开溅射设备的静电吸盘和在第四步内接通该静电吸盘来改变由加热器产生的热导率。
6.如权利要求1所述的方法,其中:所述的第一温度低于150℃,且所述的第二温度在300至400℃的范围内。
7.如权利要求1所述的方法,其中:所述的第一和第二金属层都包含以铝或铜作为其主要成分的材料。
8.如权利要求1所述的方法,进一步包括在第二和第三步之间形成第一阻挡金属层的第五步;以及紧接第四步之后的在第二金属层上形成第二阻挡金属层的第六步。
9.如权利要求1所述的方法,进一步包括在第一步之前,在半导体衬底上形成互连层的第七步,其中所述的绝缘膜形成在该互连层上,该开口形成在该绝缘膜的位于该互连层上面的部分内。
10.如权利要求9所述的方法,其中所述的第七步包括:在该半导体衬底上形成第三阻挡金属层的步骤;在该第三阻挡金属层上形成第三金属层的步骤;在该第三金属层上形成第四阻挡金属层的步骤;以及对第三阻挡金属层、第三金属层和第四阻挡金属层构图的步骤。
11.如权利要求10所述的方法,进一步包括在第四阻挡金属层和第一阻挡金属层之间的开口内形成第五阻挡金属层的步骤。
12.如权利要求11所述的方法,其中:所述的第一至第五阻挡金属层中的每一层均包含难熔金属。
13.如权利要求10所述的方法,其中:所述的第一至第四阻挡金属层中的每一层均包含氮化钛。
14.如权利要求10所述的方法,其中:所述的第一至第四阻挡金属层中的每一层均包含钛和氮化钛的堆叠层。
15.如权利要求11所述的方法,其中:所述的第五阻挡金属层包含钛。
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US09/063,094 US6140236A (en) | 1998-04-21 | 1998-04-21 | High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring |
US063094 | 1998-04-21 | ||
US063,094 | 1998-04-21 |
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CN1234606A true CN1234606A (zh) | 1999-11-10 |
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US (1) | US6140236A (zh) |
EP (1) | EP0954015B1 (zh) |
JP (1) | JP3335931B2 (zh) |
KR (1) | KR100328901B1 (zh) |
CN (1) | CN1155075C (zh) |
DE (1) | DE69937317T2 (zh) |
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CN100424868C (zh) * | 2005-07-13 | 2008-10-08 | 精工爱普生株式会社 | 半导体装置及其制造方法 |
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CN105990227A (zh) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | 金属连线的制作方法及半导体器件 |
CN105990227B (zh) * | 2015-02-27 | 2019-11-08 | 中芯国际集成电路制造(上海)有限公司 | 金属连线的制作方法及半导体器件 |
CN104934332A (zh) * | 2015-04-29 | 2015-09-23 | 安徽松泰包装材料有限公司 | 一种铜铝复合薄膜生产工艺 |
CN110890318A (zh) * | 2018-09-11 | 2020-03-17 | 长鑫存储技术有限公司 | 接触孔填充方法及结构、集成电路芯片 |
Also Published As
Publication number | Publication date |
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JPH11307478A (ja) | 1999-11-05 |
EP0954015A3 (en) | 2002-09-11 |
US6140236A (en) | 2000-10-31 |
CN1155075C (zh) | 2004-06-23 |
DE69937317T2 (de) | 2008-07-03 |
KR19990083367A (ko) | 1999-11-25 |
KR100328901B1 (ko) | 2002-03-14 |
EP0954015A2 (en) | 1999-11-03 |
JP3335931B2 (ja) | 2002-10-21 |
EP0954015B1 (en) | 2007-10-17 |
DE69937317D1 (de) | 2007-11-29 |
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