CN1213174A - 一种芯片封装型半导体器件及其生产方法 - Google Patents

一种芯片封装型半导体器件及其生产方法 Download PDF

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CN1213174A
CN1213174A CN98119391A CN98119391A CN1213174A CN 1213174 A CN1213174 A CN 1213174A CN 98119391 A CN98119391 A CN 98119391A CN 98119391 A CN98119391 A CN 98119391A CN 1213174 A CN1213174 A CN 1213174A
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lead
wire
semiconductor chip
connecting rod
end portion
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木村直人
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NEC Corp
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NEC Corp
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Abstract

本发明涉及一种CSP型半导体器件及其生产方法。通过线接合,把半导体芯片上的每个焊头连接到引线的端头部分,然后把该引线弯折成弯折部分。每个端头部分向着半导体芯片移动。然后,用模制树脂把上述结构密封起来。这样,可以放宽由线接合过程使用的毛细管的尺寸所造成的限制。同时可以进一步提高该器件的防潮能力。

Description

一种芯片封装型半导体器件及其生产方法
本发明涉及一种CSP(芯片封装)型半导体器件及其生产方法,特别是涉及一种带有COL(引线架上芯片)-BGA(网络焊球阵列)结构的半导体器件。
根据图1A和1B所示,对于传统的CSP型半导体器件,引线30通过粘性绝缘胶带70A附着于半导体芯片60A的背部,每个引线30被通过导线90接到半导体芯片60A表面的一焊头50上。上述部件都被模制树脂110A密封。另外,每个引线30都连接到焊球120上。附图标记40表示悬空管脚。
上述传统的CSP型半导体器件的结构包括一种COL结构和一种BGA结构。
根据图1A和1B所示的具有COL-BGA结构的传统半导体器件,通过导线90把半导体芯片的焊头50与引线30连接,引线30和导线90的连接点必须与半导体芯片60A保持一定距离,这样导线接合装置的毛细管130不会接触到半导体芯片60A,如图2中所示方式。引线和导线的连接点与半导体芯片60A之间的距离芯片由该芯片的一侧与导线90之间的距离,以及毛细管130的尺寸及边缘余地所决定。例如该距离可以为250μm~300μm。另外,导线90与引线30的连接点可以包含于模制树脂110A内,以利于防潮。
不用说,传统的CSP型半导件器件的外部尺寸必须保持在一个确定的可允许数值范围内。另外,在同一边的该半导体芯片的一侧面与模制树脂一侧面之间的距离必须保持在1mm或1mm以下。如果该模制树脂的毛边尺寸约为200μm,半导体芯片的尺寸误差为±50μm,并且在安装和线接合过程中,半导体芯片的位置移动不可避免,在导线90和引线30的连接点处的模制树脂厚度变得相当薄。而且导线90与引线30之间的连接点与模制树脂侧边的距离很近。另外,在该连接点的附近,引线30的一端头部分从模制树脂110A中暴露出来。相应地,在这种状况下很难保持抗湿性或过量潮湿耐受性。
本发明的目的在于提供一种能改善其抗潮湿性或过量潮湿耐受性的CSP型半导体器件及其生产方法。
根据本发明的第一方面,提供一种CSP型半导体器件包括:形成在其正面上的电子线路和该线路的多个端头(即第一焊头和第二焊头)的一半导体芯片;附着在半导体芯片正面背侧的绝缘胶带;第一引线与第二引线平行地分布于半导体芯片的背侧下方,而绝缘胶带则置于这些引线之间和引线与半导体芯片之间;分别把第一焊头和第二焊头连接到第一和第二引线的第一导线和第二导线;把上述部件的特定部位密封的模制树脂,第一引线通过半导体芯片的底部,并从该模制树脂的第一侧向第二侧延伸,但不与其接触,在该第一引线的末梢形成第一端头部分并连接到第一导线,第二引线在半导体芯片的下部通过,并从模制树脂的第二侧向着第一侧延伸,但并不与其接触,在该第二引线的末梢形成第二端头部分并连接到第二导线,第一引线和第二引线分别连接到第一导电球和第二导电球,该第一和第二导电球穿过模制树脂。
根据本发明的第一方面,可以使整个第一引线和第二引线的位置低于半导体芯片的背面所在的平面,第一和第二端头部分分别与第一和第二导线接合。另外,也可以使每个第一和第二引线在半导体芯片的下面穿过后向半导体芯片的正面弯曲,引线的第一和第二端头部分分别焊接第一和第二导线。
根据本发明的第二方面,提供一种生产CSP型半导体器件的方法,包括如下步骤:准备一个包括相互平行的第一框架和第二框架的引线框架,第一和第二连杆均把第一和第二框架连接在一起,将第一引线从第一连杆中叉出向第二连杆的方向延伸,在其末梢形成第一端头部分,第二引线从第二连杆中叉出向第一连杆的方向延伸,在其末梢形成第二端头部分,第一悬空管脚从第一框架中叉出,第二悬空管脚从第二框架中叉出;把绝缘胶带附着在半导体芯片的背面,通过绝缘粘性材料使该半导体芯片固定在引线框架的第一和第二悬空管脚上,在该半导体芯片正面上形成一个电子线路和该线路的多个端头(即第一和第二焊头);通过线接合,用第一和第二导线将第一和第二焊头分别与第一和第二端头部分连接起来;使在第一连杆侧的每条第一引线和第二连杆侧的每条第二引线上的特定部位发生机械形变,使得第一和第二端头部位向该半导体芯片方向移动;形成模制树脂,密封位于半导体芯片附近的部分第一引线、第二引线、第一悬空管脚和第二悬空管脚,并密封第一和第二导线以及该半导体芯片;选择性地除去模制树脂,使得第一和第二引线暴露出来,以形成第一和第二导电球;分别从第一和第二连杆以及第一和第二框架上切下第一和第二引线以及第一和第二悬空管脚。
根据本发明的第三方面,在此提供一种生产CSP型半导体器件的方法,其中包括如下步骤:准备一个包括相互平行的第一和第二框架的引线框架,第一和第二连杆均把第一和第二框架连接起来,第一引线从第一连杆叉出并在其端头附近向第一连杆方向弯折的同时向第二连杆的方向延伸,在该引线末梢形成第一端头部分,第二引线从第二连杆中叉出,并在其端头附近向第二连杆方向弯折的同时向第一连杆的方向延伸,在该引线末梢形成第二端头部分,第一悬空管脚从第一框架上叉出,第二悬空管脚从第二框架上叉出;把绝缘胶带附着在半导体芯片的背面且位于第一和第二端头部分之间,以通过绝缘粘性材料使该半导体芯片固定在引线框架的第一和第二悬空管脚上,在该的半导体芯片正面上形成一个电子线路和该线路的多个端头(即第一和第二焊头);通过线接合,用跨在第一端头部分上的第一导线与跨在第二端头部分上的第二导线分别把第一和第二焊头与第一和第二连杆连接;在第一和第二端头部分将第一和第二导线焊接封口;把第一导线从第一导线与第一端头部分之间的焊头处切断,把第二导线从第二导线与第二端头部分之间的焊头处切断,使第一导线与第二连杆分离,第二导线与第一连杆分离;用模制树脂密封位于半导体芯片附近的部分第一引线、第二引线、第一悬空管脚和第二悬空管脚,并密封第一和第二导线以及该半导体芯片;选择性地除去模制树脂,使得第一和第二引线暴露出来,以形成第一和第二导电球;分别从第一和第二连杆以及第一和第二框架上切下第一和第二引线以及第一和第二悬空管脚。
根据本发明的上述各方面,只要先把引线弯折,再把该导线连接到引线上,可以通过在引线与导线相接合后移动该引线或通过导线与连杆相接合,使得引线与导线之间的连接点更加靠近半导体芯片。
本发明的上述目的和新特点将在下面结合附图的说明中得到充分地体现。
附图说明如下:
图1A为用于说明一种传统的CSP型半导体器件及其生产方法的俯视图;
图1B为用于说明这种传统的CSP型半导体器件及其生产方法的侧视图;
图2为用于说明在传统CSP型半导体器件中存在的问题的传统CSP型半导体器件的结构图;
图3A为用于说明本发明第一实施例的生产工艺的俯视图;
图3B为用于说明本发明第一实施例的生产工艺的侧视图;
图4A为用于说明本发明第一实施例的生产工艺,并且在工艺过程上与图3A和3B相接续的俯视图;
图4B为用于说明本发明第一实施例的生产工艺,并且在工艺过程上与图3A和3B相接续的侧视图;
图5A为用于说明本发明第一实施例的生产工艺,并且在工艺过程上与图4A和4B相接续的俯视图;
图5B为用于说明本发明第一实施例的生产工艺,并且在工艺过程上与图4A和4B相接续的侧视图;
图6A为用于说明本发明第一实施例的生产工艺,并且在工艺过程上与图5A和5B相接续的俯视图;
图6B为用于说明本发明第一实施例的生产工艺,并且在工艺过程上与图5A和5B相接续的侧视图;
图7A为用于说明本发明第二实施例的生产工艺的俯视图;
图7B为用于说明本发明第二实施例的生产工艺的侧视图;
图8A为用于说明本发明第二实施例的生产工艺,并且在工艺过程上与图7A和7B相接续的俯视图;
图8B为用于说明本发明第二实施例的生产工艺,并且在工艺过程上与图7A和7B相接续的侧视图;
图9A为用于说明本发明第二实施例的生产工艺,并且在工艺过程上与图8A和8B相接续的俯视图;
图9B为用于说明本发明第二实施例的生产工艺,并且在工艺过程上与图8A和8B相接续的侧视图;
图10A为用于说明本发明第二实施例的生产工艺,并且在工艺过程上与图9A和9B相接续的俯视图;
图10B为用于说明本发明第二实施例的生产工艺,并且在工艺过程上与图9A和9B相接续的侧视图;
下面将参照附图具体说明本发明的最佳实施例。
在下文中根据生产工艺过程的顺序对本发明的第一实施进行说明。
根据图3A和3B所示,在此提供一个引线框架,其中包括:相互平行的第一框架11和第二框架12;连接到第一和第二框架的第一连杆21和第二连杆22;在其边缘形成第一端头部分31a,且从第一连杆21叉出并向着第二连杆22的方向延伸的第一引线31;在其边缘形成第二端头部分32a,且从第二连杆22叉出并向着第一连杆21的方向延伸的第二引线32;从第一框架11叉出的第一悬空管脚41;从第二框架12叉出的第二悬空管脚42。
在半导体芯片60的正面上形成电子线路(未示出)和该线路的多个端头(即第一焊头51和第二焊头52)。附着绝缘胶带70的半导体芯片的正面背侧通过绝缘粘性材料80连接引线框架的第一悬空管脚41和第二悬空管脚42。
通过线接合分别用第一导线91和第二导线92把第一焊头51和第二焊头52连接到第一端头部分31a和第二端头部分32a。在此种情况下,最好焊头与相邻导线以及引线与相邻导线所形成的角度约为直角。
接着根据图4A和图4B所示,使在第一连杆21一侧的第一引线31的特定部位及在第二连杆22一侧的第二引线32的特定部位发生机械变形形成第一弯折部分101和第二弯折部位102。这样,第一端头部分31a和第二端头部分32a分别向着半导体芯片60的方向平行移动。每个引线与导线的连接点到半导体芯片60的侧边的距离可以为50m~100m。
接着根据图5A和5B所示,形成一个模制树脂110,它密封如下部分:在半导体芯片60附近的部分第一引线31和第二引线32、第一悬空管脚41和第二悬空管脚42;包括第一端头部分31a和第二端头部分32a的部分;第一导线91;第二导线92;半导体芯片60。
有选择地除去模制树脂110的一部分,使第一引线31和第二引线32暴露出来。接着通过回流焊接或类似的方法形成分别连接第一焊球121和第二焊球122的第一引线31和第二引线32。
最后,把第一引线31、第二引线32、第一悬空管脚41和第二悬空管脚42切下,使它们与第一连杆21、第二连杆22、第一框架11和第二框架22相分离。这样就制成图6A和6B所示的CSP型半导体器件。
根据本发明的第一实施例,CSP型半导体器件中包括:一个半导体芯片60,在该芯片的正面上形成电子线路和该电路的多个端头(即第一焊头51和第二焊头52);附着在该半导体芯片60的背面的绝缘胶带70;均平行设置于半导体芯片60的背面下方的第一引线31和第二引线32,而绝缘胶带70则夹在这些引线之间与引线和半导体芯片60之间;分别把第一焊头51和第二焊头52连接到第一引线31和第二引线32的第一导线91和第二导线92;以及一个在特定部位密封上述各部件的模制树脂。另外,第一引线31从该半导体芯片60下方通过,并从模制树脂110的第一侧边141向着树脂110的第二侧边142方向延伸,但不触及第二侧边,在该引线的末梢形成连接第一导线91的第一端头部分31a。类似地,第二引线32从该半导体芯片60下方通过,并从模制树脂110的第二侧边142向着树脂110的第一侧边141方向延伸,但不触及第一侧边,在该引线的末梢形成连接第二导线92的第二端头部分32a。第一引线31和第二引线32分别连接第一焊球121和第二焊球122,并且第一和第二焊球穿过模制树脂110。
根据第一实施例,在通过线接合把半导体芯片的焊头与引线接合起来之后,对引线进行机械变形,使引线上连接导线的端头部分向半导体芯片平移。结果,每个引线的端头部分与半导体芯片60的侧边之间的距离比进行线接合时缩短。这样,即使当半导体芯片的侧边与模制树脂的侧边之间的距离为固定的,也有可能使模制树脂的侧边到每个引线与导线的连接点之间的距离较大。另外,这样可以保证每个引线的端头部分不从模制树脂中暴露出来。由于树脂阻挡了空气中湿气的侵入,从而提高半导体芯片的防潮能力。
接着,根据生产工艺过程的顺序对发明的第二实施实例进行说明。
根据图7A和7B所示,在此提供一个引线框架,其中包括:相互平行的第一框架11和第二框架12;连接到第一和第二框架的第一连杆21和第二连杆22;从第一连杆21叉出的第一引线31A向着第二连杆22的方向延伸,在其边缘向着第一连杆21方向弯成直角以形成第一端头部分31Aa;从第二连杆22叉出的第二引线32向着第一连杆21的方向延伸,在其边缘向着第二连杆22方向弯成直角以形成第二端头部分32Aa;从第一框架11叉出的第一悬空管脚41;从第二框架12叉出的第二悬空管脚42。
在半导体芯片60的正面上形成电子线路(未示出)和该线路的多个端头(即第一焊头51和第二焊头52)。位于第一端头部分31Aa与第二端头部分32Aa之间的芯片背面上附着绝缘胶带70,通过绝缘粘性材料80把芯片背面与第一悬空管脚41和第二悬空管脚42连接起来。在此种情况下,确定引线框架与半导体芯片60的尺寸,使该半导体芯片侧边与每个引线端头部分之间的距离在50μm~100μm之间。另外,第一端头部分31Aa与第二端头部分32Aa的厚度约为100μm。
通过线接合,用跨过第一端头部分31Aa的导线91A把第一焊头51和第二连杆22相连接。类似地,通过线接合,用跨过第二端头部分32Aa的导线92A把第二焊头52和第一连杆21相连接。
接着通过回流焊接等方法,用焊锡131把第一导线91A与第一端头部分31Aa相连接,类似地,用焊锡132把第二导线92A与第二端头部分32Aa相连接。另外,最好作为回流焊接前的工艺,在焊接上半导体芯片之前,在第一端头部分31Aa和第二端头部分32Aa的端头镀上一层易于吸附焊锡的金属(如金)。
根据图8A和8B所示,把第一导线91A从第一导线91A与第一端头部分31Aa的焊头处切下,类似地,把第二导线92A从第二导线92A与第二端头32Aa的焊头切下,使得它们与第二连杆22和第一连杆21分离。
接着根据图9A和9B所示,形成一个模制树脂110B,它密封如下部分:位于半导体芯片60附近的第一引线31A和第二引线32A、第一和悬空管脚41和第二悬空管脚42;包括第一端头部分31Aa和第二端头部分32Aa的部分;第二导线91Aa;第二导线92Aa;半导体芯片60。
有选择地除去模制树脂110B的一部分,使第一引线31A和第二引线32A暴露出来。接着分别形成连接第一引线31A和第二引线32A的第一焊球121A和第二焊球122A。
最后,把第一引线31A、第二引线32A、第一悬空管脚41和第二悬空管脚42切下,使它们与第一连杆21、第二连杆22、第一框架11和第二框架22相分离。这样就制成图10A和10B所示的CSP型半导体器件。
根据本发明的第二实施例,每个第一引线31A和第二引线32A从半导体芯片60下方通过,并向着带有第一焊头51和第二焊头52的半导体芯片60的正面弯折。在此种情况下,每条第一引线31A和第二引线32A都弯成接近直角。接着,通过焊锡131、132分别把第一端头部分31Aa和第二端头部分32Aa连接到第一导线91Aa和第二导线92Aa上。这样,引线从半导体芯片的侧边伸出,其优点是使出现短路的可能性变小。另外,由于引线的长度变短,其第二个优点是从外部端头(即焊球)看,其寄生电阻变小了。
如上所述,根据本发明,在引线与导线相接合之后,移动引线,或者在导线与连杆相接合之后,先把引线弯折再连接该导线。具有这种结构,可以放宽由在线接合中使用的毛细管所造成的限制,并可缩短每个导线与引线的连接点到半导体芯片侧边的距离。可以把带有所述连接点的每条引线的端头部分封装于模制树脂中。这样,可以进一步地提高该CSP型半导体器件的防潮能力。
在上文中用具体的术语对本发明的最佳实施例进行说明,这种说明只是解释性的,应当知道在本发明权利要求的精神和范围内还可以作出各种改动和变化。

Claims (5)

1、一种CSP型半导体器件,其特征在于,它包括如下几个部分:
一块半导体芯片,在半导体芯片的正面上形成电子线路及该线路的多个端头部分(即第一焊头和第二焊头);
一条附着在该半导体芯片的正面背侧的绝缘胶带;
均平行设置于半导体芯片背面的下方的第一引线和第二引线,而所述绝缘胶带则位于这些引线与半导体芯片之间;
分别把第一焊头和第二焊头连接到第一引线和第二引线上的第一导线和第二导线;
把上述部件的一部分密封起来的模制树脂。
第一引线,从所述半导体芯片的下方通过,并从模制树脂的第一侧边向其第二侧边方向延伸,但不触及该第二侧边,在该引线的末梢形成第一端头部分,第一端头部分与第一导线相连接。
第二引线,从所述半导体芯片的下方通过,并从模制树脂的第二侧边向其第一侧边方向延伸,但不触及该第一侧边,在该引线的末梢形成第二端头部分,第二端头与第二导线相连接。
分别连接到第一和第二导电球上的第一和第二引线,该第一和第二导电球穿过所述模制树脂。
2、如权利要求1所述的CSP型半导体器件,其特征在于,其中第一和第二引线的整体位置比半导体芯片背面所在的平面低,第一和第二端头部分分别与第一和第二导线相连接。
3、如权利要求1所述的CSP型半导体器件,其特征在于,每条第一和第二引线在通过半导体芯片下方后,向着该半导体芯片的正面弯折,该引线第一和第二端头部分分别通过焊接连接第一和第二导线。
4、一种生产CSP型半导体器件的方法,其特征在于,其中包括如下步骤:
准备一个包括相互平行的第一和第二框架的引线框架,第一连杆和第二连杆均把第一框架与第二框架连接在一起,第一引线从第一连杆上叉出,并向着第二连杆的方向延伸,在该引线末梢形成第一端头部分,第二引线从第二连杆上叉出,并向着第一连杆的方向延伸,在该引线末梢形成第二端头部分,第一悬空管脚从第一框架上叉出,第二悬空管脚从第二框架上叉出;
在半导体芯片的背面附着上绝缘胶带,使得该半导体芯片通过绝缘粘性材料固定到引线框架的第一和第二悬空管脚上,在该半导体芯片的正面上形成电子线路及该电路的多个端头(即第一焊头和第二焊头);
进行线接合,使第一和第二导线分别把第一和第二焊头连接到第一和第二端头部分;
通过对在第一连杆侧边的每条第一引线上的特定部位以及第二连杆侧边的每条第二引线上的特定部位进行机械变形,使第一和第二端头部分向着半导体芯片的方向移动;
形成模制树脂,把在半导体芯片附近的部分第一引线、第二引线、第一悬空管脚和第二悬空管脚密封起来,并把第一导线和第二导线以及所述半导体芯片一同密封起来;
有选择地除去部分模制树脂,使得第一引线和第二引线暴露出来,形成第一和第二导电球;
分别把第一和第二引线、第一和第二悬空管脚从第一和第二连杆以及第一和第二框架上切下。
5、一种生产CSP型半导体器件的方法,其特征在于,其中包括如下步骤:
准备一个包括相互平行的第一和第二框架的引线框架,第一和第二连杆均把第一和第二框架连接起来,第一引线从第一连杆叉出并在其端头附近向第一连杆方向弯折的同时向第二连杆的方向延伸,在该引线末梢形成第一端头部分,第二引线从第二连杆中叉出,并在其端头附近向第二连杆方向弯折的同时向第一连杆的方向延伸,在该引线末梢形成第二端头部分,第一悬空管脚从第一框架上叉出,第二悬空管脚从第二框架上叉出;
把绝缘胶带附着在半导体芯片的背面且位于第一和第二端头部分之间,以通过绝缘粘性材料使该半导体芯片固定在引线框架的第一和第二悬空管脚上,在该的半导体芯片正面上形成一个电子线路和该线路的多个端头(即第一和第二焊头);
通过线接合,用跨在第一端头部分上的第一导线与跨在第二端头部分上的第二导线分别把第一和第二焊头与第一和第二连杆连接;
在第一和第二端头部分将第一和第二导线焊接封口;
把第一导线从第一导线与第一端头部分之间的焊头处切断,把第二导线从第二导线与第二端头部分之间的焊头处切断,使第一导线与第二连杆分离,第二导线与第一连杆分离;
形成模制树脂,密封位于半导体芯片附近的部分第一引线、第二引线、第一悬空管脚和第二悬空管脚,并密封第一和第二导线以及该半导体芯片;
选择性地除去模制树脂,使得第一和第二引线暴露出来,以形成第一和第二导电球;
分别从第一和第二连杆以及第一和第二框架上切下第一和第二引线以及第一和第二悬空管脚。
CN98119391A 1997-09-26 1998-09-25 一种芯片封装型半导体器件及其生产方法 Pending CN1213174A (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320619C (zh) * 2002-06-10 2007-06-06 日东电工株式会社 制作半导体器件和其中所用耐热压敏粘结带的方法
CN101170071B (zh) * 2006-10-27 2011-08-03 三星Techwin株式会社 半导体封装和形成半导体封装的导线环的方法
CN101202254B (zh) * 2006-12-13 2012-03-28 雅马哈株式会社 半导体装置及其制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3501281B2 (ja) * 1999-11-15 2004-03-02 沖電気工業株式会社 半導体装置
US7148561B2 (en) * 2001-03-29 2006-12-12 Siliconware Precision Industries Co., Ltd. Ball grid array substrate strip with warpage-preventive linkage structure
JP3920629B2 (ja) * 2001-11-15 2007-05-30 三洋電機株式会社 半導体装置
US7132314B2 (en) * 2004-05-28 2006-11-07 Texas Instruments Incorporated System and method for forming one or more integrated circuit packages using a flexible leadframe structure
DE102004057485B4 (de) * 2004-11-29 2007-10-18 Infineon Technologies Ag Leistungshalbleiterbauelement und Verfahren zu dessen Herstellung
US8269324B2 (en) * 2008-07-11 2012-09-18 Stats Chippac Ltd. Integrated circuit package system with chip on lead
USD934452S1 (en) 2017-12-04 2021-10-26 Signature Systems Group Llc Modular flooring tile with cable channels
CN116441752B (zh) * 2023-04-27 2023-11-21 广州丰江微电子有限公司 高精度定位引线框架切割系统

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949416A (en) * 1991-05-28 1999-09-07 Borland International, Inc. Method for providing help information for nested functions
KR930014916A (ko) * 1991-12-24 1993-07-23 김광호 반도체 패키지
JPH0637136A (ja) * 1992-05-22 1994-02-10 Nec Ic Microcomput Syst Ltd 半導体装置
EP0595021A1 (en) * 1992-10-28 1994-05-04 International Business Machines Corporation Improved lead frame package for electronic devices
KR100292036B1 (ko) * 1993-08-27 2001-09-17 윤종용 반도체패키지의제조방법및그에 따른반도체패키지
US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
KR0179803B1 (ko) * 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
JP2859194B2 (ja) * 1996-01-30 1999-02-17 九州日本電気株式会社 プラスチックパッケージ型半導体集積回路及びその製造 方法
KR980006174A (ko) * 1996-06-18 1998-03-30 문정환 버틈 리드 패키지
JP3679199B2 (ja) * 1996-07-30 2005-08-03 日本テキサス・インスツルメンツ株式会社 半導体パッケージ装置
JP3012816B2 (ja) * 1996-10-22 2000-02-28 松下電子工業株式会社 樹脂封止型半導体装置およびその製造方法
KR100237051B1 (ko) * 1996-12-28 2000-01-15 김영환 버텀리드 반도체 패키지 및 그 제조 방법
JP3793628B2 (ja) * 1997-01-20 2006-07-05 沖電気工業株式会社 樹脂封止型半導体装置
KR100214561B1 (ko) * 1997-03-14 1999-08-02 구본준 버틈 리드 패키지
US6271582B1 (en) * 1997-04-07 2001-08-07 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
KR100246587B1 (ko) * 1997-09-19 2000-03-15 유무성 볼 그리드 어레이 반도체 팩키지

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320619C (zh) * 2002-06-10 2007-06-06 日东电工株式会社 制作半导体器件和其中所用耐热压敏粘结带的方法
CN101170071B (zh) * 2006-10-27 2011-08-03 三星Techwin株式会社 半导体封装和形成半导体封装的导线环的方法
CN101202254B (zh) * 2006-12-13 2012-03-28 雅马哈株式会社 半导体装置及其制造方法

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