CN1135609C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1135609C
CN1135609C CNB971111677A CN97111167A CN1135609C CN 1135609 C CN1135609 C CN 1135609C CN B971111677 A CNB971111677 A CN B971111677A CN 97111167 A CN97111167 A CN 97111167A CN 1135609 C CN1135609 C CN 1135609C
Authority
CN
China
Prior art keywords
semiconductor element
lead
wire
chip set
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB971111677A
Other languages
English (en)
Other versions
CN1166053A (zh
Inventor
大内伸仁
河野博
山田悦夫
白石靖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of CN1166053A publication Critical patent/CN1166053A/zh
Application granted granted Critical
Publication of CN1135609C publication Critical patent/CN1135609C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/787Means for aligning
    • H01L2224/78703Mechanical holding means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

在塑料封装的半导体器件中,在同一个引线框架上形成芯片支架与引线,将芯片支架放在半导体元件(1)表面以上的位置,弯曲芯片支架,并用绝缘胶带将其固定在半导体元件(1)上聚酰亚胺晶片涂层(9)的表面上,使引线(3)与半导体元件(1)上聚酰亚胺晶片涂层(9)的表面接触,但不固定,用金线(6)连接引线(3)与半导体元件(1)的电极,用封装材料(7)将它们都封装起来。以此防止密封材料产生缝裂,并减小塑料封装半导体器件的厚度。

Description

半导体器件及其制造方法
本发明涉及半导体器件的结构,具体地说,涉及塑料封装的半导体器件的结构及其制造方法。
近年来,在塑料封装半导体器件中,芯片尺寸越来越大,而封装边沿之间和半导体元件的尺寸却趋向于越来越小。这是因为尽管半导体元件的尺寸变得越来越大,但是,装它的封装尺寸却已被标准化,不能增大。因此,为了解决这样一个问题,日本专利公开6-105721所揭示的LOC型(引线在芯片上)结构的塑料封装半导体器件已被采用。
这种LOC型结构塑料封装半导体器件是这样构成的,使得引线用绝缘胶带粘结在半导体元件表面上,借助金线把镀在引线顶面的金线镀层与半导体元件电极上的金球相连接,另外,它们都用树脂材料密封起来。
但是,作为这种传统的塑料封装半导体器件的主要问题,例如,有时发生这样的情况:由于在板上安装(on a board)时产生的热量会使树脂材料开裂,致使功能受损。如果在半导体器件保存在空气中时树脂材料吸收水分而变潮,则在板上安装时水分受热蒸发,由此产生的力导致开裂。绝缘胶带吸收水分的趋势尤为明显,使得绝缘胶带周围往往开裂。另外。作为另一个问题,因为有绝缘胶带,半导体器件厚度的减小受到限制。
本发明是鉴于上述问题而作出的。因此,本发明的目的是提供一种能够防止开裂的塑料封装半导体器件,并使之变薄,以及提供其制造方法。
本发明的特征在于,除了引线以外还提供芯片支架,只把芯片支架固定在半导体元件上,而引线则不固定在芯片上,半导体元件的电极与引线连接。
采用这种结构,由于引线与半导体元件表面之间没有用来固定它们的特殊的材料,所以引线和半导体元件的组合厚度可以减薄。因而整个半导体器件的厚度可以减薄。另外,绝缘胶带只用来将半导体元件粘结在芯片支架上,所以要用的绝缘胶带面积非常小。因此,绝缘胶带所固有的开裂得以防止,因而质量得以提高。
图1是剖面图,表示按本发明的塑料封装的半导体器件有关部位的结构及引线的布置;
图2是剖面图,表示按本发明第一实施例的塑料封装半导体器件有关部位的结构及芯片支架的布置;
图3是顶视图,表示在制造过程中的按本发明第一实施例的塑料封装半导体器件;
图4是剖面图,表示按本发明第二实施例的塑料封装的半导体器件有关部位的结构及引线的布置;
图5是按本发明第二实施例的塑料封装半导体器件及芯片支架的布置的剖面图;
图6是顶视图,表示在制造过程中的按本发明第二实施例的塑料封装半导体器件;
图7是顶视图,表示在制造过程中的按本发明第三实施例的塑料封装半导体器件;
图8是沿着图7中A-A’线的剖面图,表示按本发明第三实施例的塑料封装半导体器件基本部分的结构;
图9是沿着图7中B-B’线的剖面图,表示按本发明第三实施例的塑料封装半导体器件基本部分的结构;
图10A和10B是按本发明第三实施例的塑料封装半导体器件的制造过程的示意图;
图11是剖面图,表示按本发明第四实施例的塑料封装半导体器件基本部分的结构;
图12是按本发明第四实施例的塑料封装半导体器件的制造过程的示意图;
图13是按本发明第五实施例的塑料封装半导体器件的制造过程的示意图;以及
图14是按本发明第六实施例的塑料封装半导体器件的制造过程的示意图;
第一实施例
图1和图2是剖面图,表示按本发明第一实施例的塑料封装半导体器件有关部位的结构。图1是表示引线布置的图形,而图2是表示芯片支架(只画出其中一个)布置的图形。图3是顶视图,表示在制造过程中的按本发明第一实施例的塑料封装半导体器件;
在半导体元件1的电路形成面上,敷上聚酰亚胺晶片涂层9。这个半导体元件1装在厚度约0.125mm的引线框架12上,后者包括引线3和芯片支架10。绝缘胶带2厚约0.15mm,插入半导体元件1与芯片支架10之间,并借助于这种绝缘胶带2,把芯片支架10和聚酰亚胺晶片涂层9粘结并固定在一起。芯片支架10在半导体元件1边沿外(图2标以数字11处)弯曲大体上刚好一个厚度(约0.15mm)。相反,引线3与聚酰亚胺晶片涂层9仅仅彼此接触,而不固定。芯片支架10的底面10a(弯曲部分11以外)及聚酰亚胺晶片涂层9基本上在同一个平面上。图3表示半导体元件1以这样的方法放在引线框架12上时的状态。
接着,用金线6把镀在引线3的顶面的金线镀层(未示出)与半导体元件1上的金球5相连接,用树脂材料7将它们密封起来,再将引线3与芯片支架10从引线框架12切离。然后,如图1和图2所示,塑料封装半导体器件即告完成。
如上所述,在按照第一实施例的塑料封装半导体器件的结构中,引线3与形成半导体元件1表面的聚酰亚胺晶片涂层9只接触,它们之间没有用来固定它们的任何材料。正因为如此,引线3和半导体元件1的组合厚度可以减薄。因此,整个半导体器件的厚度可以减薄。半导体器件1只用粘结在芯片支架10上的绝缘胶带2固定。因此,绝缘胶带的面积相当小。故此绝缘胶带吸收的水分可以减少,因而可以避免安装在板上时出现开裂的现象。因此,质量得以提高。
第二实施例
图4和5都是剖面图,表示按本发明第二实施例的塑料封装半导体器件有关部位的结构。图4表示引线的布置。而图5表示芯片支架(只画出其中的一个)的布置。图6是顶视图,表示在制造过程中的按本发明第二实施例的塑料封装半导体器件。参照图4至图6,相同或对应的构件用与图1至图3相同的标号标示。
在半导体元件1的电路形成面上覆有聚酰亚胺晶片涂层9。半导体元件1放在引线框架12上,后者包括引线3和芯片支架10。引线3与聚酰亚胺晶片涂层9只接触,不固定。引线3在半导体1边界外(在图4中标号21所指的部位)向下(向着半导体元件1)弯曲。每个引线3的顶面3a(弯曲部位以外,封装材料以内)与聚酰亚胺晶片涂层9基本上在同一个平面上。每个芯片支架10的位置是这样确定的,使得它的顶面10b与聚酰亚胺晶片涂层9的表面基本上在同一个平面上,其末端与半导体元件1的侧边界隔开预定的间隙5(图5)。另外,粘贴绝缘胶带2,跨在聚酰亚胺晶片涂层9的顶面与芯片支架10的顶面之间,并用这个绝缘胶带2将聚酰亚胺晶片涂层9与芯片支架10粘结并固定。图6表示用这样的方法将半导体元件1放在引线框架12上的状态。
接着,用金线6将镀在引线3顶面上的金线镀层(未示出)与半导体元件1连接,用树脂材料7将它们密封,并将引线3及芯片支架10从引线框架12切离。然后,如同4和5所述,塑料封装半导体器件即告完成。
如上所述,在按照第二实施例的塑料封装半导体器件的结构中,引线3和在半导体元件1表面上形成的聚酰亚胺晶片涂层9只是接触,它们之间没有用来固定它们的任何材料。正因为如此,引线3和半导体元件1的组合厚度可以减薄。因此,整个半导体器件的厚度可以减薄。另外,因为半导体器件1只用绝缘胶带2固定,后者跨在聚酰亚胺晶片涂层9与芯片支架10之间,所以绝缘胶带2的面积非常小。故此绝缘胶带2吸收的水分可以减少,因而可以避免安装在板上时出现开裂的现象。因此,质量得以提高。
第三实施例
图7至9表示按本发明第三实施例的塑料封装半导体器件的结构。图7是顶视图,表示在制造过程中的按本发明第三实施例的塑料封装半导体器件。图8和9是剖面图,表示有关部分的结构。图8是沿着图7中线A-A’的剖面图。图9是沿着图7中线B-B’的剖面图。参照图7至图9,相同或对应的构件用与图1至图6相同的标号标示。
在半导体元件1的电路形成面上覆有聚酰亚胺晶片涂层9。芯片支架10用绝缘胶带2粘结在聚酰亚胺晶片涂层9上。在基本上同一个平面上形成芯片支架10与引线3。如图8所示,芯片支架10用绝缘胶带2粘结在半导体元件1的表面上。另外,如图9所示,用金线6将镀在引线3顶面上的金线镀层4与设置在半导体元件1的电极(未示出)上的金球连接,以此将引线3与半导体元件1的电极连接。引线3不粘结在半导体元件1上,而是保持分开。也就是说,引线3放置在半导体元件1的上面,彼此相离一个间隙31,这个间隙31用熔化的树脂7填充。
这样,绝缘胶带2便不出现在引线3下面的部分,绝缘胶带2只用在芯片支架10上。正因为如此,绝缘胶带2的用量可以显著减少,从而限制水分的吸收。另外,因为芯片支架10与引线3在同一平面形成,所以可以省去诸如弯曲等处理引线框架的步骤。
接着,参照图10A和图10B描述图7至9所示的塑料封装半导体器件的制造方法。首先,把已经用绝缘胶带2粘结上了引线框架12的芯片支架10的半导体元件1放在图10A所示的热块13内。这时,在引线框架12内,引线3和芯片支架10基本上在同一平面上,而引线3在空气中,离开半导体元件1刚好一个绝缘胶带2的厚度,后者固定在芯片支架10和半导体元件1上。
接着,如图10B所示,用位于引线3和热块13的上表面上的引线夹14夹紧引线3和半导体元件1,使引线3与半导体元件1接触。此后,借助于利用金线6的丝焊方法把引线3的金镀层4和半导体元件1上的金球5连接。然后,放开原来固定的引线夹14,引线3回到图10A所示的位置,而半导体元件1、引线3、金线6、和芯片支架10在这个状态下(参见图8和9)被用树脂材料7密封。用这个方法,不弯曲引线3或芯片支架10,就可以获得只有芯片支架10固定在半导体元件1上的塑料封装半导体器件(参见图7至9)。
第四实施例
图11是剖面图,表示按本发明第四实施例的塑料封装半导体器件有关部分的结构。图12表示图11所示塑料封装半导体器件的制造方法。参照图11和图12,相同或对应的构件用与图1至图10相同的标号标示。
一般说来,按本发明第四实施例的塑料封装半导体器件与上述第三实施例的塑料封装半导体器件相同,但差别在于下述几个方面。亦即,图11所示的塑料封装半导体器件中引线3的末端15从半导体元件1的表面向上弯曲。因此,在制造过程中当引线夹14和热块13夹紧引线3和半导体元件1时,引线3的末端并不直接接触半导体元件1上的聚酰亚胺晶片涂层9,已经弯曲的引线3末端15的底面与聚酰亚胺晶片涂层9接触。正因为如此,就能够防止引线3在半导体元件1上造成表面缺陷。
第五实施例
图13表示按本发明第五实施例的塑料封装半导体器件的制造方法。参照图13,相同或对应的构件用与图1至图12相同的标号标示。假定,按本发明这个第五实施例的塑料封装半导体器件的结构与上述第三实施例的塑料封装半导体器件相同。
在按本发明这个第五实施例的这种塑料封装半导体器件的制造过程中,利用含有电磁铁的引线夹16,在不使引线3与半导体元件1的表面接触的情况下,把引线3上金线镀层4与半导体元件1上的金球5连接起来。参照图13,首先把已经用绝缘胶带2粘结上了芯片支架10的半导体元件1放置在热块13内。在这时刻,引线3在空气中,离开半导体元件1,相隔一个将芯片支架10粘结在半导体元件1上的绝缘胶带2的厚度。
接着,将含有电磁铁的引线夹16放在引线3的顶面上,并借助于含有电磁铁的引线夹16的磁力,将引线3固定在含有电磁铁的引线夹16的底面上,并在这种状态下,利用金线6对引线3和半导体元件1上的金球5进行丝焊。用这样的方法连接金球5与引线3,就能够防止半导体元件1的表面缺陷和引线3的变形。
按照第五实施例的制造方法同样适宜于上述按照第四实施例的塑料封装半导体器件。
第六实施例
图14表示按本发明第六实施例的塑料封装半导体器件的制造方法。参照图14,相同或对应的构件用与图1至图13相同的标号标示。假定,按本发明这个第六实施例的这种塑料封装半导体器件的结构与上述图7至9所示的第三实施例的塑料封装半导体器件相同。
在按本发明第六实施例的塑料封装半导体器件的制造过程中,利用含有电磁铁的热块17使引线3与半导体元件1的表面接触。参照图14,首先把已经用绝缘胶带2粘结上了芯片支架10的半导体元件1放置在含有电磁铁的热块17内。然后,使含有电磁铁的热块17工作,并借助于这个磁力,将引线3拉向半导体元件1的表面,并与之接触。在这种状态下,利用金线6连接金球5与引线3。用这样的方法连接金球5与引线3,不用引线夹就能够把引线3稳定地固定起来。
按照第六实施例的制造方法同样适宜于上述图11所示按照第四实施例的塑料封装半导体器件。
如上所述,按照本发明的塑料封装半导体器件及其制造方法,就能使整个半导体器件更薄。另外,能够防止粘结用的绝缘胶带所固有的产生开裂的现象,从而能够提高质量。

Claims (10)

1.一种密封材料封装的半导体器件,包括:
在其表面上有电极的半导体元件;
与所述电极连接的引线;
其特征在于还包括:
伸展在半导体元件表面上的芯片支架;以及
绝缘胶带,设置在芯片支架与所述半导体元件之间,用来将芯片支架粘结在半导体元件上。
2.权利要求1提出的半导体器件,其特征在于:
所述芯片支架在半导体元件边界以外、按照基本上刚好一个绝缘胶带的厚度的行程、向半导体元件方向弯曲。
3.一种塑料封装的半导体器件,包括:
在其表面上有电极的半导体元件;
与所述电极连接的引线;
其特征在于还包括:
芯片支架,其上表面位于半导体元件边沿以外、与半导体元件的表面基本上在同一个平面上;以及
绝缘胶带,跨在芯片支架与所述半导体元件之间,用来将芯片支架粘结在半导体元件上,其中,
所述引线在半导体元件边沿外面向半导体元件方向弯曲。
4.权利要求1提出的半导体器件,其特征在于:
引线和半导体元件用丝焊方法连接。
5.一种塑料封装的半导体器件,包括:
在其表面上有电极的半导体元件;
位于与半导体元件表面分开的位置的引线;
其特征在于还包括:
粘结在半导体元件的表面上的芯片支架;以及
连接所述电极与所述引线的导线。
6.一种制造塑料封装的半导体器件的方法,其特征在于包括下列步骤:
制备在其表面上有电极的半导体元件和包含基本上在同一个平面上形成的引线和芯片支架的引线框架;
将芯片支架粘结在半导体元件的表面上,把引线设置在半导体元件表面之上又离开所述表面的位置;以及
在使所述引线与所述半导体元件表面接触的情况下,将所述引线与所述电极连接起来。
7.权利要求6提出的方法,其特征在于:
所述引线的端部向上弯曲,离开半导体元件的表面。
8.权利要求6提出的方法,其特征在于:
将引线和电极连接的步骤包括用位于半导体元件下表面的热块和位于引线上表面的引线夹夹紧半导体元件和引线,使引线与半导体元件接触。
9.权利要求6提出的方法,其特征在于:
将引线和电极连接的步骤包括用含有电磁铁的位于半导体元件下表面的热块使引线与半导体元件接触。
10.一种制造塑料封装的半导体器件的方法,其特征在于包括下列步骤:
制备在其表面上有电极的半导体元件和包含基本上在同一个平面上形成的引线和芯片支架的引线框架;
将芯片支架粘结在半导体元件的表面上,把引线设置在半导体元件表面之上又离开所述表面的位置;以及
将含有电磁铁的引线夹放在引线的上表面,使这些引线与所述电极连接起来。
CNB971111677A 1996-05-09 1997-05-09 半导体器件及其制造方法 Expired - Fee Related CN1135609C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP114586/1996 1996-05-09
JP114586/96 1996-05-09
JP8114586A JPH09326463A (ja) 1996-05-09 1996-05-09 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
CN1166053A CN1166053A (zh) 1997-11-26
CN1135609C true CN1135609C (zh) 2004-01-21

Family

ID=14641569

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971111677A Expired - Fee Related CN1135609C (zh) 1996-05-09 1997-05-09 半导体器件及其制造方法

Country Status (3)

Country Link
JP (1) JPH09326463A (zh)
CN (1) CN1135609C (zh)
TW (1) TW408407B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3882712B2 (ja) * 2002-08-09 2007-02-21 住友電気工業株式会社 サブマウントおよび半導体装置
US7253506B2 (en) * 2003-06-23 2007-08-07 Power-One, Inc. Micro lead frame package
US7663211B2 (en) * 2006-05-19 2010-02-16 Fairchild Semiconductor Corporation Dual side cooling integrated power device package and module with a clip attached to a leadframe in the package and the module and methods of manufacture
US7489026B2 (en) * 2006-10-31 2009-02-10 Freescale Semiconductor, Inc. Methods and apparatus for a Quad Flat No-Lead (QFN) package

Also Published As

Publication number Publication date
JPH09326463A (ja) 1997-12-16
CN1166053A (zh) 1997-11-26
TW408407B (en) 2000-10-11

Similar Documents

Publication Publication Date Title
US5864174A (en) Semiconductor device having a die pad structure for preventing cracks in a molding resin
CN1065662C (zh) 半导体芯片封装及其制造方法
CN1144276C (zh) 树脂封装型半导体装置的制造方法
CN1043828A (zh) 半导体器件的制造方法
CN1751390A (zh) 包括无源器件的引线框架
JPH02201948A (ja) 半導体装置パッケージ
CN1099131C (zh) 栅阵列球半导体封装
CN1135609C (zh) 半导体器件及其制造方法
JPH10223819A (ja) 半導体装置
CN1092843C (zh) 半导体器件封装
JP3424184B2 (ja) 樹脂封止型半導体装置
CN1061174C (zh) 一种带有透明窗口的半导体封装的制造方法
CN2684375Y (zh) 芯片封装结构
CN1023675C (zh) 半导体器件的制造方法
CN1234158C (zh) 封装基板制造方法及其结构
KR100373891B1 (ko) 반도체장치
CN1119833C (zh) 封装的集成电路器件
KR100282414B1 (ko) 바텀 리디드 타입의 브이·씨·에이 패키지
JPS62296541A (ja) 樹脂封止型半導体装置
KR19980034119A (ko) 반도체 칩 적층형 패키지
KR100251331B1 (ko) 리드 프레임 및 그것을 이용한 반도체 디바이스
CN2779610Y (zh) 导线架型电气封装体
KR950000457Y1 (ko) 반도체 패키지
KR0157890B1 (ko) 반도체 패키지의 실장구조 및 실장방법
JPH05218271A (ja) Icパッケージ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: OKI SEMICONDUCTOR CO., LTD.

Free format text: FORMER OWNER: OKI ELECTRIC INDUSTRY CO., LTD.

Effective date: 20090508

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090508

Address after: Tokyo, Japan, Japan

Patentee after: OKI Semiconductor Co., Ltd.

Address before: Tokyo port area, Japan

Patentee before: Oki Electric Industry Co., Ltd.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040121

Termination date: 20120509