CN1181494C - 峰值编程电流降低装置和方法 - Google Patents
峰值编程电流降低装置和方法 Download PDFInfo
- Publication number
- CN1181494C CN1181494C CNB001355546A CN00135554A CN1181494C CN 1181494 C CN1181494 C CN 1181494C CN B001355546 A CNB001355546 A CN B001355546A CN 00135554 A CN00135554 A CN 00135554A CN 1181494 C CN1181494 C CN 1181494C
- Authority
- CN
- China
- Prior art keywords
- current
- storer
- current source
- switch
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000006096 absorbing agent Substances 0.000 claims description 26
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 208000012978 nondisjunction Diseases 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/467,788 US6236611B1 (en) | 1999-12-20 | 1999-12-20 | Peak program current reduction apparatus and method |
US09/467,788 | 1999-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1302069A CN1302069A (zh) | 2001-07-04 |
CN1181494C true CN1181494C (zh) | 2004-12-22 |
Family
ID=23857180
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB001355546A Expired - Fee Related CN1181494C (zh) | 1999-12-20 | 2000-12-19 | 峰值编程电流降低装置和方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6236611B1 (zh) |
EP (1) | EP1111619B1 (zh) |
JP (1) | JP2001222882A (zh) |
KR (1) | KR100748070B1 (zh) |
CN (1) | CN1181494C (zh) |
DE (1) | DE60033776T2 (zh) |
SG (1) | SG88805A1 (zh) |
TW (1) | TW505921B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6256224B1 (en) * | 2000-05-03 | 2001-07-03 | Hewlett-Packard Co | Write circuit for large MRAM arrays |
WO2003001532A2 (en) * | 2001-01-24 | 2003-01-03 | Infineon Technologies North America Corp. | Current source and drain arrangement for magnetoresistive memories (mrams) |
JP4637388B2 (ja) * | 2001-03-23 | 2011-02-23 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
EP1433181B1 (en) * | 2001-06-20 | 2007-10-24 | Qimonda AG | Current source and drain arrangement for magnetoresistive memories (mrams) |
JP4771631B2 (ja) * | 2001-09-21 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
US6711052B2 (en) * | 2002-06-28 | 2004-03-23 | Motorola, Inc. | Memory having a precharge circuit and method therefor |
US6714440B2 (en) | 2002-06-28 | 2004-03-30 | Motorola, Inc. | Memory architecture with write circuitry and method therefor |
US6621729B1 (en) | 2002-06-28 | 2003-09-16 | Motorola, Inc. | Sense amplifier incorporating a symmetric midpoint reference |
WO2004049344A2 (en) | 2002-11-28 | 2004-06-10 | Koninklijke Philips Electronics N.V. | Method and device for improved magnetic field generation during a write operation of a magnetoresistive memory device |
US6778431B2 (en) * | 2002-12-13 | 2004-08-17 | International Business Machines Corporation | Architecture for high-speed magnetic memories |
US7221582B2 (en) * | 2003-08-27 | 2007-05-22 | Hewlett-Packard Development Company, L.P. | Method and system for controlling write current in magnetic memory |
CN1957423A (zh) * | 2004-05-27 | 2007-05-02 | 皇家飞利浦电子股份有限公司 | Mram功率有效字节写入的颠倒磁性隧道结 |
KR100587702B1 (ko) | 2004-07-09 | 2006-06-08 | 삼성전자주식회사 | 피크 전류의 감소 특성을 갖는 상변화 메모리 장치 및그에 따른 데이터 라이팅 방법 |
KR100694967B1 (ko) * | 2005-06-29 | 2007-03-14 | 주식회사 하이닉스반도체 | 프로그램 동작시 에러 발생 비율을 감소시키는 플래시메모리 장치 및 그 프로그램 동작 제어 방법 |
TWI398065B (zh) * | 2009-09-02 | 2013-06-01 | Giga Byte Tech Co Ltd | 分配器、控制方法及電子系統 |
KR102081757B1 (ko) | 2013-06-26 | 2020-02-26 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 방법 |
KR20150022242A (ko) | 2013-08-22 | 2015-03-04 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US9330746B2 (en) * | 2014-03-19 | 2016-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Resistive memory array |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59101095A (ja) * | 1982-11-29 | 1984-06-11 | Toshiba Corp | 不揮発性半導体メモリ |
JPH0793040B2 (ja) * | 1987-11-11 | 1995-10-09 | 日本電気株式会社 | 書込み・消去可能な読出し専用メモリ |
US5025419A (en) * | 1988-03-31 | 1991-06-18 | Sony Corporation | Input/output circuit |
JPH0512891A (ja) * | 1990-09-17 | 1993-01-22 | Toshiba Corp | 半導体記憶装置 |
JPH0562484A (ja) * | 1991-09-06 | 1993-03-12 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
US5534793A (en) * | 1995-01-24 | 1996-07-09 | Texas Instruments Incorporated | Parallel antifuse routing scheme (PARS) circuit and method for field programmable gate arrays |
JPH09306159A (ja) * | 1996-05-14 | 1997-11-28 | Nippon Telegr & Teleph Corp <Ntt> | 逐次読出しメモリ |
JP4136028B2 (ja) * | 1997-04-28 | 2008-08-20 | キヤノン株式会社 | 磁性薄膜メモリ素子、それを用いた磁性薄膜メモリ及びその記録再生方法 |
JPH11176179A (ja) * | 1997-12-15 | 1999-07-02 | Nec Corp | 不揮発性半導体記憶装置 |
US6097626A (en) * | 1999-07-28 | 2000-08-01 | Hewlett-Packard Company | MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells |
-
1999
- 1999-12-20 US US09/467,788 patent/US6236611B1/en not_active Expired - Lifetime
-
2000
- 2000-12-04 TW TW089125774A patent/TW505921B/zh not_active IP Right Cessation
- 2000-12-08 SG SG200007282A patent/SG88805A1/en unknown
- 2000-12-15 KR KR1020000076921A patent/KR100748070B1/ko active IP Right Grant
- 2000-12-18 JP JP2000384226A patent/JP2001222882A/ja active Pending
- 2000-12-19 EP EP00127789A patent/EP1111619B1/en not_active Expired - Lifetime
- 2000-12-19 CN CNB001355546A patent/CN1181494C/zh not_active Expired - Fee Related
- 2000-12-19 DE DE60033776T patent/DE60033776T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
SG88805A1 (en) | 2002-05-21 |
CN1302069A (zh) | 2001-07-04 |
EP1111619A3 (en) | 2001-09-26 |
DE60033776D1 (de) | 2007-04-19 |
KR100748070B1 (ko) | 2007-08-09 |
TW505921B (en) | 2002-10-11 |
KR20010062468A (ko) | 2001-07-07 |
US6236611B1 (en) | 2001-05-22 |
EP1111619A2 (en) | 2001-06-27 |
DE60033776T2 (de) | 2007-06-28 |
EP1111619B1 (en) | 2007-03-07 |
JP2001222882A (ja) | 2001-08-17 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: FISICAL SEMICONDUCTOR INC. Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP. |
|
CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: FREESCALE SEMICONDUCTOR, Inc. Address before: Texas in the United States Patentee before: FreeScale Semiconductor |
|
CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP USA, Inc. Address before: Texas in the United States Patentee before: FREESCALE SEMICONDUCTOR, Inc. |
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CP01 | Change in the name or title of a patent holder | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20041222 Termination date: 20181219 |
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CF01 | Termination of patent right due to non-payment of annual fee |