CN1173407C - 具有电容器的半导体器件及其制造方法 - Google Patents
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Abstract
一种用于存储单元的半导体器件，包括：有源矩阵，由晶体管和在晶体管四周形成的第一绝缘膜提供；电容器结构，形成在第一绝缘膜上，由底电极，位于底电极上的电容器薄膜和形成在电容器薄膜上的上电极构成；第二绝缘层，形成在晶体管和电容器结构上；金属互连，形成在第二绝缘层和有源矩阵上，使晶体管和电容器结构电连接；以及氢阻挡层，形成在金属互连上。其中所述氢阻挡层具有双层结构。
Description
技术领域
本发明涉及一种半导体器件；更进一步讲，涉及在存储单元中使用的具有电容器结构的半导体器件及其制造方法。
背景技术
众所周知，包括晶体管和电容器的存储单元的动态随机存取存储器(DRAM)主要通过微型化来减小尺寸而具有较高的集成度。然而，这仍然需要降低存储单元的面积。
因此，为了满足这种需要，已提出几种方法，如沟槽型结构或叠层型电容器，这些电容器在存储器件中对于电容器来说以三维形式排列来实现减小存储单元面积的目的。然而，制造三维排列的电容器是一个长而且耗时的过程并且通常需要高的制造成本。因此，迫切需要一种新的存储器件，这种存储器件能减小单元面积并确保必要的信息量而不需要复杂的制造步骤。
因此，DRAM器件使用一种高介电常数材料作电容器薄膜如钛酸钡锶(BST)和氧化钽(Ta2O5)来满足这种需要。但是，DRAM存储器具有易失性的缺点并且每秒必须刷新多次的问题，尽管它的优点是小，便宜，快速，和能耗低。
为了解决DRAM的上述问题，已提出一种铁电随机存取存储器(FeRAM)，其中用具有铁电性质的电容器薄膜如钽酸锶钡(SBT)和锆钛酸铅(PZT)代替了常规的氧化硅膜或氮化硅膜，FeRAM由于铁电材料的剩余极化而具有非易失性特性以及能在低电压下使用。
在制造存储器件如DRAM和FeRAM中，为了在一种外部有害的环境如潮湿，颗粒等中保护半导体器件，具有在金属导电层之上形成钝化层的步骤。钝化层是利用一种方法如等离子增强化学气相淀积(PECVD)在富氢的环境中形成的。然而，在钝化层的制造过程中，通过PECVD过程产生的氢气使存储单元的电容器退化。那就是，氢气和离子渗透到上电极和电容器的侧面，进而到达电容器薄膜并同组成电容器薄膜的铁电材料中的氧原子反应。
因而，这些问题导致了获得所需要的重复制造、可靠性和制造存储单元的产量方面的困难。
发明内容
因此，本发明的一个目的是提供一种半导体器件，具有由钛层和原硅酸四乙酯(TEOS)提供的双氢阻挡层，用于在形成金属连接之后的防止电容器的氢损伤。
本发明的另一个目的是提供一种其内具有双氢阻挡层为了防止在形成钝化层过程中电容器的氢损伤的半导体器件的制造方法。
根据本发明的一方面，提供一种在存储单元中使用的半导体器件，包括：设有晶体管和形成在晶体管四周的第一绝缘层的有源矩阵；电容器结构，形成在第一绝缘层之上，由底电极，位于底电极上的电容器薄膜和形成在电容器薄膜上的上电极构成；第二绝缘层，形成在晶体管和电容器结构上；金属互连，形成在第二绝缘层和有源矩阵上，将晶体管电连接到电容器结构；和氢阻挡层，形成在金属互连之上，其中所述氢阻挡层具有双层结构。
根据本发明的另一方面，提供一种在存储单元中使用的半导体器件的制造方法，该方法包括以下步骤：a)制备一个设有晶体管和形成在晶体管的四周的第一绝缘层的有源矩阵；b)在第一绝缘层之上形成一个电容器结构，所述电容器结构包括由铁电材料构成的电容器薄膜；c)在电容器和晶体管结构上形成第二绝缘层；d)形成金属互连层并布图金属互连成为预定形状，使其将晶体管和电容器结构电连接；和e)在金属互连之上形成氢阻挡层，其中所述氢阻挡层具有双层结构。
附图说明
通过下面结合附图对优选实施例的描述，可以使本发明的上述和其它目的以及特点更明显易懂。附图中：
图1是本发明的一个优选实施例的半导体器件的剖面图；以及
图2A至2G是根据本发明的半导体存储器件的制造方法的示意剖面图。
图1和图2A至2G是用于存储单元的半导体器件100的剖面图根据本发明的优选实施例的半导体器件制造方法。在图1和图2A至2G中，相同的部分用相同的数字做标记。
具体实施方式
图1提供了本发明的半导体器件100的剖面图，包括有源矩阵110，电容器结构150，第二绝缘层126，位线134，金属互连136，和由原硅酸四乙酯(TEOS)SiO2138和Ti金属层140提供的双氢阻挡层142。
此外，钝化层144形成在位线134之上，Ti金属层140和第二绝缘层126通过等离子增强化学气相淀积(PECVD)技术，在富氢气环境中高温下完成，例如，320～400℃。半导体器件100中，位线134是与扩散区106之一电连接，并且电容器结构150的上电极是通过金属互连136与另一扩散区106电连接，所述位线134和金属互连136彼此没有电连接。电容器结构150的底电极可以与平板线(图中未示出)连接，以提供一个恒定的电位。而且，在底电极和上电极之间，具有由铁电材料例如SBT(SrBiTaOx)，PZT(PbZrTiOx)等构成的电容器薄膜。这里，数字标记125表示形成在上电极上的TiN粘结层，是为了增强上电极和金属互连136的连接。这里，双氢阻挡层142起着重要的防止由于氢的渗透导致半导体器件100的电容器劣化的作用。因为氢原子的扩散速率在Ti金属里显著降低。
图2A至2G是表示根据本发明的优选实施例的半导体存储器件100的制造方法的示意剖面图。
半导体器件100的制造步骤是首先制备包括半导体衬底102的有源矩阵110，隔离区104，扩散区106，栅氧化物112，栅导线113，间隔114和第一绝缘层116，如图2A所示。扩散区106之一作为源区和另一扩散区106作为漏区。第一绝缘层116由材料如硼磷硅玻璃(BPSG)或中等温度氧化物(MTO)等构成。
此后，缓冲层118，例如由Ti或TiOx构成，形成在第一绝缘层116上具有50～250nm的厚度范围。然后，第一金属层120，介质层122和第二金属层124是形成在缓冲层118上。在本优选实施例中，介质层122由铁电材料如钛酸锶钡(SBT)，锆钛酸铅(PZT)等构成，通过如旋涂、化学气相淀积(CVD)的方法形成。
随后的步骤如图2B所示，将第二金属层124布图为第一预定形状得到上电极124A和电容器薄膜122A。然后，将介质层122，第一金属层120和缓冲层118是布图在第二预先构成的电容器薄膜122A和底电极结构上，因而形成缓冲118A，底电极120A，电容器薄膜122A和上电极124A的电容器结构150。在以下步骤中最好底电极120A的尺寸不同于上电极124A的尺寸来形成平板线(图中未示出)。
下面的步骤如图2C所示，第二绝缘层126，由材料如BPSG、MTO、或BPSG和原硅酸四乙酯(TEOS)基氧化物组成的双层构成，通过使用如CVD方法形成在电容器结构150和第一绝缘层116上，并且通过BPSG回流步骤或化学机械抛光(CMP)平坦化，如图2C所示。
随后的步骤是，通过如光刻和等离子刻蚀方法，例如，反应离子刻蚀(RIE)，将第一和第二开槽128、130形成在扩散区106的上方，分别穿过第二和第一绝缘层126、116。并且，通过一种方法如光刻和等离子刻蚀，将第三开槽132形成在电容器结构150的上方，穿过第二绝缘层126。并且，为了增强上电极124A和金属互连136的连接，如图2D所示，TiN层125是通过第三开槽132形成在电容器结构150的上电极124A上。但是，TiN层125是可以省略的。
然后，金属互连层136，例如，由Ti/Ti/Al构成，是形成在包括开槽128、130、132的内部的整个表面上并布图成第三形状形成位线134和金属互连层136，如图2E所示。然后，TEOS-SiO2层138和Ti金属层140形成在金属互连136上，并布图成第三预定形状，如图2F所示。这里，其中TEOS-SiO2层138和Ti金属层140是通过一种方法如CVD和PVD方法形成的，TEOS-SiO2和Ti金属层140的厚度分别至少为50nm和20nm。要提到的是双氢阻挡层142应充分覆盖电容器结构来有效防止在以后的钝化步骤中电容器结构150的氢损伤。
最后，例如用未搀杂的硅玻璃(USG)和Si3N4制作的钝化层140，通过一种方法如PECVD方法形成在金属互连136和第二绝缘层126上用来保护半导体器件100不被外围环境如潮湿、颗粒等的损坏，如图2F所示。该钝化步骤是在富氢环境中高温下进行的，如320～400℃。
如前面所述的本发明形成的半导体器件100，是能够防止电容器结构150因氢的渗透被损坏。也就是说，通过由TEOS-SiO2138和Ti金属层140形成的双氢阻挡层142，因为氢原子的扩散速率在Ti金属里显著的降低而有效的避免了氢损伤。
根据上述实施例描述的本分明，对于本领域技术人员来说，在不离开本发明权利要求所限定的范围时，显然可以做各种变化和修改。
Claims (17)
1、一种用于存储单元的半导体器件包括：
有源矩阵，由晶体管和在晶体管四周形成的第一绝缘膜提供；
电容器结构，形成在第一绝缘膜上，由底电极，位于底电极上的电容器薄膜和形成在电容器薄膜上的上电极构成；
第二绝缘层，形成在晶体管和电容器结构上；
金属互连，形成在第二绝缘层和有源矩阵上，并将晶体管电连接到电容器结构；以及
氢阻挡层，形成在金属互连上，
其中所述氢阻挡层具有双层结构。
2、根据权利要求1所述的半导体器件，还包括：
TiN粘结层，用于金属互连和上电极的连接，该TiN粘结层形成在上电极之上；以及
钝化层，在富氢环境下通过等离子增强CVD形成在金属互连之上。
3、根据权利要求1所述的半导体器件，其中所述双层结构由TEOS-SiO2和Ti金属提供。
4、根据权利要求3所述的半导体器件，其中，TEOS-SiO2的厚度至少为50nm。
5、根据权利要求3所述的半导体器件，其中，Ti金属的厚度至少为20nm。
6、根据权利要求1所述的半导体器件，其中，氢阻挡层充分覆盖电容器结构用于防止器件的氢损伤。
7、根据权利要求1所述的半导体器件，其中，电容器薄膜是从包括SrBiTaOx、PbZrTiOx组成的组中选择出的铁电材料构成的。
8、根据权利要求2所述的半导体器件，其特征在于：钝化层是由非掺杂的硅玻璃和Si3N4构成。
9、一种用于存储单元的半导体器件的制造方法，该方法包括以下步骤：
a)制备有源矩阵，由晶体管和形成在晶体管的四周的第一绝缘层提供；
b)在第一绝缘层之上形成电容器结构，其中，电容器结构包括由铁电材料制成的电容器薄膜；
c)在晶体管和电容器结构上形成第二绝缘层；
d)形成金属互连层，并将金属互连布图为预定形状，使晶体管和电容器结构电连接；以及
e)在金属互连之上形成氢阻挡层，
其中所述氢阻挡层具有双层结构。
10、根据权利要求9的方法，在步骤c)之后，还包括在上电极上形成TiN粘结层的步骤，用于金属互连和所述电容器结构的上电极的连接。
11、根据权利要求9的方法，在步骤e)之后，还包括在富氢环境下通过等离子增强CVD方法在金属互连上形成钝化层的步骤。
12、根据权利要求9所述的半导体器件，其中，所述双层结构由TEOS-SiO2和Ti金属提供。
13、根据权利要求12所述的半导体器件，其中，TEOS-SiO2的厚度至少为50nm。
14、根据权利要求12所述的半导体器件，其中，Ti金属的厚度至少为20nm。
15、根据权利要求9所述的半导体器件，其中，氢阻挡层充分覆盖所述电容器结构来防止所述器件的氢损伤。
16、根据权利要求9所述的半导体器件，其中，电容器薄膜是从包括SrBiTaOx、PbZrTiOx组成的组中选择出的铁电材料构成。
17、根据权利要求2所述的半导体器件，其中，钝化层是由非掺杂的硅玻璃和Si3N4制成。
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| KR1019990065831A KR100362189B1 (ko) | 1999-12-30 | 1999-12-30 | 수소 확산을 방지할 수 있는 산화막 및 티타늄막 이중층을구비하는 반도체 메모리 소자 및 그 제조 방법 |
| KR65831/1999 | 1999-12-30 |
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| JP4497493B2 (ja) * | 2000-04-20 | 2010-07-07 | セイコーＮｐｃ株式会社 | 強誘電体記憶素子および強誘電体記憶素子の製造方法 |
| US6706584B2 (en) * | 2001-06-29 | 2004-03-16 | Intel Corporation | On-die de-coupling capacitor using bumps or bars and method of making same |
| CN1264220C (zh) * | 2001-09-27 | 2006-07-12 | 松下电器产业株式会社 | 强电介质存储装置及其制造方法 |
| JP2003297956A (ja) * | 2002-04-04 | 2003-10-17 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
| JP3836052B2 (ja) * | 2002-06-25 | 2006-10-18 | 沖電気工業株式会社 | 半導体素子及びその製造方法 |
| JP2005229001A (ja) * | 2004-02-16 | 2005-08-25 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
| JP2006147771A (ja) * | 2004-11-18 | 2006-06-08 | Oki Electric Ind Co Ltd | 強誘電体メモリ及びその製造方法 |
| CN103578919A (zh) * | 2012-07-26 | 2014-02-12 | 无锡华润上华科技有限公司 | 一种mos器件的钝化层形成方法以及一种mos器件 |
| JP7248966B2 (ja) * | 2016-07-06 | 2023-03-30 | 国立研究開発法人産業技術総合研究所 | 半導体記憶素子、電気配線、光配線、強誘電体ゲートトランジスタ及び電子回路の製造方法並びにメモリセルアレイ及びその製造方法 |
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| JP3131982B2 (ja) * | 1990-08-21 | 2001-02-05 | セイコーエプソン株式会社 | 半導体装置、半導体メモリ及び半導体装置の製造方法 |
| JP3319869B2 (ja) * | 1993-06-24 | 2002-09-03 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
| US5438023A (en) * | 1994-03-11 | 1995-08-01 | Ramtron International Corporation | Passivation method and structure for a ferroelectric integrated circuit using hard ceramic materials or the like |
| JP3417167B2 (ja) * | 1995-09-29 | 2003-06-16 | ソニー株式会社 | 半導体メモリ素子のキャパシタ構造及びその形成方法 |
| JP3028080B2 (ja) * | 1997-06-18 | 2000-04-04 | 日本電気株式会社 | 半導体装置の構造およびその製造方法 |
| JP2846310B1 (ja) * | 1997-06-24 | 1999-01-13 | 松下電子工業株式会社 | 半導体装置及びその製造方法 |
| TW366593B (en) * | 1997-06-28 | 1999-08-11 | United Microelectronics Corp | Manufacturing method of DRAM |
| KR100246783B1 (ko) * | 1997-06-30 | 2000-03-15 | 김영환 | 플래쉬 메모리 소자의 제조방법 |
| JP2926050B2 (ja) * | 1997-07-24 | 1999-07-28 | 松下電子工業株式会社 | 半導体装置及びその製造方法 |
| JP3484324B2 (ja) * | 1997-07-29 | 2004-01-06 | シャープ株式会社 | 半導体メモリ素子 |
| US5923970A (en) * | 1997-11-20 | 1999-07-13 | Advanced Technology Materials, Inc. | Method of fabricating a ferrolelectric capacitor with a graded barrier layer structure |
| JP3212930B2 (ja) * | 1997-11-26 | 2001-09-25 | 日本電気株式会社 | 容量及びその製造方法 |
| JPH11238862A (ja) * | 1997-12-18 | 1999-08-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| KR100300868B1 (ko) * | 1997-12-27 | 2001-09-22 | 박종섭 | 질소가함유된확산장벽막을이용한강유전체캐패시터형성방법 |
| US6130103A (en) * | 1998-04-17 | 2000-10-10 | Symetrix Corporation | Method for fabricating ferroelectric integrated circuits |
| TW434877B (en) * | 1998-12-03 | 2001-05-16 | Matsushita Electronics Corp | Semiconductor memory device and method for manufacturing the same |
| JP3276007B2 (ja) * | 1999-07-02 | 2002-04-22 | 日本電気株式会社 | 混載ｌｓｉ半導体装置 |
| US6238933B1 (en) * | 1999-05-06 | 2001-05-29 | Ramtron International Corporation | Polarization method for minimizing the effects of hydrogen damage on ferroelectric thin film capacitors |
| JP3331334B2 (ja) * | 1999-05-14 | 2002-10-07 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2001015696A (ja) * | 1999-06-29 | 2001-01-19 | Nec Corp | 水素バリヤ層及び半導体装置 |
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| JP4594517B2 (ja) | 2010-12-08 |
| US6423554B2 (en) | 2002-07-23 |
| TW476158B (en) | 2002-02-11 |
| US20010006239A1 (en) | 2001-07-05 |
| CN1302086A (zh) | 2001-07-04 |
| KR100362189B1 (ko) | 2002-11-23 |
| JP2001196551A (ja) | 2001-07-19 |
| KR20010058497A (ko) | 2001-07-06 |
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