CN1172344A - 用以形成半导体装置的中间层绝缘薄膜的方法 - Google Patents

用以形成半导体装置的中间层绝缘薄膜的方法 Download PDF

Info

Publication number
CN1172344A
CN1172344A CN97112407A CN97112407A CN1172344A CN 1172344 A CN1172344 A CN 1172344A CN 97112407 A CN97112407 A CN 97112407A CN 97112407 A CN97112407 A CN 97112407A CN 1172344 A CN1172344 A CN 1172344A
Authority
CN
China
Prior art keywords
insulation film
mesosphere insulation
mesosphere
chemical vapour
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN97112407A
Other languages
English (en)
Other versions
CN1090818C (zh
Inventor
李相奎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1172344A publication Critical patent/CN1172344A/zh
Application granted granted Critical
Publication of CN1090818C publication Critical patent/CN1090818C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

一种用以形成半导体装置的中间层绝缘薄膜的方法被揭示。第一中间层绝缘薄膜被沉积在一具有高的阶梯元件区域与低的阶梯周边区域之半导体装置的整个上表面之上,接着做热处理。较该第一中间层绝缘薄膜更能抵抗蚀刻的第二中间层绝缘薄膜被沉积。再者,第三中间层绝缘薄膜被沉积,接着做热处理。这些中间层绝缘薄膜系借助于一CMP制程而被平坦化。在该CMP制程中,该第一中间层绝缘薄膜被快速蚀刻,而该第二中间层绝缘薄膜则被缓慢除去。

Description

用以形成半导体装置的 中间层绝缘薄膜的方法
本发明一般涉及一种用以形成半导体装置的中间层绝缘薄膜的方法，特别涉及在为使中间层绝缘薄膜平坦化的化学机械研磨中，利用一种高密度的等离子体氧化物薄膜作为一种研磨减速器(retarder)。
主要产生自半导体元件高度集成化的结果的半导体装置的高阶梯(step)有可能引起所谓的缺口化(notching)，一种产生自照相蚀刻制程中的漫反射的图形缺陷问题。此使得接续的制程难以进行。
为了解决此问题，将该高阶梯掩埋覆盖以一种绝缘材料的平坦化技术已被提出。在半导体装置的高度集成化中，这些平坦化的技术现已被认为是一种非常重要的制程，因为其有助于后续的制程。
通常为了将一具有高阶梯覆盖的半导体装置平坦化，一种掺杂有高密度的硼(B)与磷(P)的硼磷硅玻璃(以下称做“BPSG”)薄膜被使用，且将其在高温下处理。
然而，此种利用BPSG薄膜的平坦化制程在制造具有高集成度的例如为256M或更多之DRAM的半导体装置中仍系引起缺口化的问题，其中介于元件(cell)区域与周边区域之间的阶梯覆盖被保持在0.8至1.0μm的高度。
此外，由于在半导体装置中金属线被要求为更窄，一种利用例如为深UV的更短波作为光源之步进机被用于其照相蚀刻。然而，此种步进机之聚焦深度变为小到至约为0.4μm，此使其无法形成金属线用的光致抗蚀剂图形。即使该光致抗蚀剂图形被形成，所产生之金属线不是易于断开、就是产生一跨接(bridge)的问题。在此，为了在一晶片上利用一暴光掩模经由一光学透镜形成一图形，该聚焦深度被定义成如下。当焦点被带入晶片之中时，虚像系呈现在该晶片以该透镜的中心为基准的上方及下方的位置。换言之，该聚焦深度系为介于该透镜与该最靠近透镜的影像之间的长度之两倍。
在高度集成的半导体元件中，一种不同的方法已被发展来克服上述的难题。一种利用化学浆体的化学机械研磨(以下称做“CMP”)技术现已被利用来研磨与平坦化该高阶梯的覆盖。
为了更深入了解本发明的背景，一种公知的CMP技术参照图1与2的说明将被提出。
首先，如图1中所示，制备一半导体基板1其中一底层结构3被制得。借助于形成一场氧化薄膜而将半导体元件分开、形成一栅电极、提供一源极与漏极、以及形成一位线与一电容。为了方便起见，这些在图1与2中被省去。
然后，一具有大约为1000埃厚的BPSG薄膜5，其系厚于介于元件区域100与周边区域200之间的阶梯覆盖，而被沉积在该底层结构3之上，接着在800℃或是更高的温度下做该BPSG薄膜5的热处理。
然后，如图2中所示，为了上部的结构之平坦化，一种CMP的制程被进行来蚀刻该BPSG薄膜5。在此时，该蚀刻系作用在周边区域200以及该元件区域100。因此，虽然在图2中标示“B”的阶梯覆盖系小于在图1中标示“A”的阶梯覆盖，在此CMP的制程之后其仍然存在。
如上所述，该CMP的制程借助于厚厚地沉积该BPSG薄膜并且用化学药剂将其机械地研磨而容许该阶梯覆盖被降低。然而，由于该元件区域系沿着该周边区域被研磨的CMP制程的凹曲(dishing)效应，要获得整个的平坦化是困难的，并且因此接续的步骤并不能顺利地进行。于是，许多的问题系产生，其包含在半导体装置高度集成化的困难以及因此所得到的半导体装置在特性与可靠度上的劣化。
由于只有某一特定的厚度的BPSG薄膜被研磨，公知的CMP额外需要一终点的检测器，例如为一用以感测与马达速度有关的电流变化的检测器、或是一光学式的检测器。该点检测一个因素系增加了半导体装置的制程成本。再者，运作该检测器的协定系增加了半导体装置之整体制造过程的复杂度，以导致生产率的降低。
本发明之一目的系为克服公知技术所遭遇到的上述的问题，并且系为提供一种用以形成半导体装置的中间层绝缘薄膜的方法，其系可达成半导体装置的特性、可靠度、生产率以及高集成度的明显改善。
根据本发明的第一特点，一种用以形成半导体装置的中间层绝缘薄膜的方法被提供并且包含步骤为提供一在元件与周边区域上形成有一较低结构层的半导体基板；在该较低结构层的整个上表面之上形成一第一中间层绝缘薄膜并且将该第一中间层绝缘薄膜做热处理；将一第二中间层绝缘薄膜沉积在该第一中间层绝缘薄膜之上；将一第三中间层绝缘薄膜沉积在该第二中间层绝缘薄膜之上并且将该第三中间层绝缘薄膜做热处理；以及将该第一、第二与第三中间层绝缘薄膜蚀刻以平坦化。
根据本发明之另一特点，一种用以形成半导体装置的中间层绝缘薄膜的方法被提供并且包含步骤为提供一在元件与周边区域上形成有一较低结构层的半导体基板；在该较低结构层的整个上表面之上形成一第一硼磷硅玻璃(BPSG)绝缘薄膜并且将该第一BPSG绝缘薄膜做热处理；将一高密度的等离子体氧化物薄膜沉积在该第一BPSG中间层绝缘薄膜之上；将一第二BPSG沉积在该高密度的等离子体氧化物薄膜之上并且将该第二BPSG中间层绝缘薄膜做热处理；以及将该第一BPSG中间层绝缘薄膜、该高密度的等离子体氧化物薄膜与该第二BPSG中间层绝缘薄膜借助于一种化学机械研磨技术蚀刻以平坦化。
本发明之其它的目的与特点将从以下的实施例的说明并参照附图而更为明显，其中：
图1与2系为表示一种公知的用以形成半导体装置的中间层绝缘薄膜的方法的概要剖面图；以及
图3与4系为表示一种根据本发明的用以形成半导体装置的中间层绝缘薄膜的方法的概要剖面图。
较佳实施例的详细说明
参照该附图对本发明的较佳实施例的应用会更好的了解，其中同样的参考图号被分别用于同样与对应的部件上。
参照图3与4说明根据本发明的用以形成半导体装置的中间层绝缘薄膜的制程。
如图3中所示，准备一半导体基板11，于其上建立一底层结构13以包含一用以将元件分开的场氧化薄膜、一栅电极、源极与漏极、一位线以及一电容，其中全部均未显示。
然后，一厚度约为1000至5000埃且厚于该介于一元件区域300与一周边区域400的阶梯覆盖的第一BPSG绝缘薄膜15被沉积在该底层结构13的上表面之上以作为一第一中间层绝缘薄膜。或者是，不用该第一BPSG绝缘薄膜15，一种BSG薄膜或是其它的绝缘薄膜系可被使用。例如，一种O3-TEOS的氧化硅薄膜可利用常压的化学气相沉积(APCVD)或是低压的化学气相沉积(LPCVD)而被沉积。再者，一种经由等离子体增强的化学气相沉积(PECVD)而沉积得到的氧化硅薄膜可取代该第一BPSG绝缘薄膜15。
一约在700至900℃的热处理被进行以稳定该第一BPSG绝缘薄膜15。
接着，一作为一第二中间层绝缘薄膜之高密度的等离子体氧化物薄膜17系以一厚度约为500至3000埃而被沉积在该所产生的结构上。为达成此目的，一种电子回旋加速器共振(ECR)的化学气相沉积技术、一种螺旋波的CVD技术或是一种电感耦合等离子体(ICP)的化学气相沉积技术被使用。
其后，具有大约为2000至10000埃的厚度之第二BPSG绝缘薄膜19被沉积在该高密度的等离子体氧化物薄膜17之上作为一第三中间层绝缘薄膜，在等离子体密度范围从约为1010至1012离子/厘米2且接着该第二BPSG绝缘薄膜19在700至900℃用作稳定的热处理之下。
然后，如图4中所示，一个CMP制程被执行以将该元件区域300与周边区域400平坦化。在此例中，该高密度的等离子体氧化物薄膜17被当作一个比该BPSG薄膜15更能抵挡研磨的阻挡层，因而该凹曲的现象并未发生。
根据本发明，该CMP制程系在该研磨头的压力被设为5到7psi、旋转速度为20至50rpm、该平台的桌面速度为15至40rpm以及该研磨头的背压为0到2psi的情形下被进行。作为一种悬浮的化学品，一种例如为KOH或是NH4OH的碱性溶液被用来防止该研磨粒聚集成更大的颗粒或是沉淀。
如同之前所述，根据本发明的用以形成半导体装置的中间层绝缘薄膜的方法的特征在于利用一高密度的等离子体氧化物薄膜于一CMP制程中。当一包含有该第一BPSG绝缘薄膜、该高密度的等离子体氧化物薄膜与该第二BPSG绝缘薄膜的堆积结构被送至一CMP制程处理时，该氧化物薄膜被缓慢地被除去，而该BPSG绝缘薄膜则快速地被完成，因而此种在蚀刻上的差异系容许该研磨终点容易地被检测。此外，较低阶梯的周边区域可避免被过度研磨，于是一完全平坦而毫无凹曲的问题之结构可被获得，因此使接续的制程变得容易。于是，本发明具有改善半导体装置之可靠度与生产率且获得半导体装置的高集成度的极大优点。
本发明已用一种说明的性质而被描述，并且应了解的是所使用的词汇是用作说明而并不是用做限制。
本发明的许多修改与变化在上述的指教之下系为可能的。因此，应了解的是在所附的申请专利范围之范畴中，本发明可用不同于以上所特别描述的方式来实行。

Claims (20)

1.一种用以形成半导体装置的中间层绝缘薄膜的方法，其系包含步骤为：
提供一在元件与周边区域上形成有一较低结构层的半导体基板；
在该较低结构层的整个上表面之上形成一第一中间层绝缘薄膜并且将该第一中间层绝缘薄膜做热处理；
将一第二中间层绝缘薄膜形成在该第一中间层绝缘薄膜之上；
将一第三中间层绝缘薄膜形成在该第二中间层绝缘薄膜之上并且将该第三中间层绝缘薄膜做热处理；以及
将该第一、第二与第三之中间层绝缘薄膜蚀刻以平坦化。
2.根据权利要求1的方法，其中该第一中间层绝缘薄膜系由硼磷硅玻璃所形成。
3.根据权利要求1的方法，其中该第一中间层绝缘薄膜系利用一种常压的化学气相沉积技术的O3-TEOS的氧化硅薄膜所形成。
4.根据权利要求1的方法，其中该第一中间层绝缘薄膜系利用一种低压的化学气相沉积技术的O3-TEOS的氧化硅薄膜所形成。
5.根据权利要求1的方法，其中该第一中间层绝缘薄膜系利用一种等离子体增强的化学气相沉积技术的氧化硅薄膜所形成。
6.根据权利要求1的方法，其中该第一中间层绝缘薄膜系沉积大约为1000至5000埃的厚度。
7.根据权利要求1的方法，其中该第一中间层绝缘薄膜系在大约为700至900℃的温度下被热处理。
8.根据权利要求1的方法，其中该第二中间层绝缘薄膜系利用一种电子回旋加速器的化学气相沉积技术在范围从约为1010至1012个离子/厘米2的等离子体密度下由一高密的等离子体氧化物薄膜所形成。
9.根据权利要求1的方法，其中该第二中间层绝缘薄膜系利用一种螺旋波的化学气相沉积技术下由一高密度的等离子体氧化物薄膜所形成。
10.根据权利要求1的方法，其中该第二中间层绝缘薄膜系利用一种电感耦合的化学气相沉积技术下由一高密度的等离子体氧化物薄膜所形成。
11.根据权利要求1的方法，其中该第二中间层绝缘薄膜系形成大约为500至3000埃的厚度。
12.根据权利要求1的方法，其中该第三中间层层绝缘薄膜系由硼磷硅玻璃所形成。
13.根据权利要求1的方法，其中该第三中间层绝缘薄膜系利用一种常压的化学气相沉积技术的O3-TEOS的氧化硅薄膜所形成。
14.根据权利要求1的方法，其中该第三中间层绝缘薄膜系利用一种低压的化学气相沉积技术的O3-TEOS的氧化硅薄膜所形成。
15.根据权利要求1的方法，其中该第三中间层绝缘薄膜系利用一种等离子体增强的化学气相沉积技术的氧化硅薄膜所形成。
16.根据权利要求1的方法，其中该第三中间层绝缘薄膜系沉积大约为2000至10000埃的厚度。
17.根据权利要求1的方法，其中该蚀刻的步骤之进行系借助于一种化学机械研磨制程。
18.根据权利要求17的方法，其中该化学机械研磨制程系在一研磨头的压力被设为5到7psi、旋转速度为20至50rpm、该平台的桌面速度为15至40rpm以及该研磨头的背压为0到2psi的情况下被进行。
19.根据权利要求17的方法，其中该化学机械研磨制程系借助于利用一种选自KOH或是NH4OH的碱性悬浮物而被进行。
20.一种用以将半导体装置的中间层绝缘薄膜平坦化的方法，其系包含步骤为：
提供一在元件与周边区域上形成有一较低结构层的半导体基板；
在该较低结构层的整个上表面之上形成一第一硼磷硅玻璃中间层绝缘薄膜并且将该第三硼磷硅玻璃中间层绝缘薄膜在一温度约为700至900℃下做热处理；
将一高密度的等离子体氧化物薄膜沉积在该第一中间层绝缘薄膜之上，该氧化物薄膜系具有范围从约为1010至1012个离子/厘米2的等离子体密度；
将一第二硼磷硅玻璃中间层绝缘薄膜沉积在该高密度的等离子体氧化物薄膜之上并且将该第二硼磷硅玻璃中间层绝缘薄膜在一温度约为700至900℃下做热处理；以及
将该第一硼磷硅玻璃中间层绝缘薄膜、该高密度的等离子体氧化物薄膜与该第二硼磷硅玻璃中间层绝缘薄膜借助于一种化学机械研磨技术蚀刻以平坦化。
CN97112407A 1996-05-22 1997-05-22 用以形成半导体装置的中间层绝缘薄膜的方法 Expired - Fee Related CN1090818C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960017357A KR100211540B1 (ko) 1996-05-22 1996-05-22 반도체소자의 층간절연막 형성방법
KR17357/96 1996-05-22

Publications (2)

Publication Number Publication Date
CN1172344A true CN1172344A (zh) 1998-02-04
CN1090818C CN1090818C (zh) 2002-09-11

Family

ID=19459421

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97112407A Expired - Fee Related CN1090818C (zh) 1996-05-22 1997-05-22 用以形成半导体装置的中间层绝缘薄膜的方法

Country Status (4)

Country Link
US (1) US5880039A (zh)
KR (1) KR100211540B1 (zh)
CN (1) CN1090818C (zh)
TW (1) TW381305B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646688A (zh) * 2011-02-22 2012-08-22 索尼公司 半导体装置及其制造方法、半导体晶片层叠法和电子设备
CN113437134A (zh) * 2021-06-22 2021-09-24 福建省晋华集成电路有限公司 一种半导体结构、半导体结构制备方法及半导体装置

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209293A (ja) * 1997-01-22 1998-08-07 Sony Corp 半導体装置の製造方法
US6025279A (en) * 1998-05-29 2000-02-15 Taiwan Semiconductor Manufacturing Company Method of reducing nitride and oxide peeling after planarization using an anneal
KR100470165B1 (ko) 1999-06-28 2005-02-07 주식회사 하이닉스반도체 반도체소자 제조 방법
US6479385B1 (en) 2000-05-31 2002-11-12 Taiwan Semiconductor Manufacturing Company Interlevel dielectric composite layer for insulation of polysilicon and metal structures
KR100721190B1 (ko) * 2001-06-29 2007-05-23 주식회사 하이닉스반도체 반도체 메모리소자 제조방법
KR20050008364A (ko) * 2003-07-15 2005-01-21 삼성전자주식회사 층간절연막 평탄화 방법
KR100624566B1 (ko) * 2004-05-31 2006-09-19 주식회사 하이닉스반도체 커패시터 상부에 유동성 절연막을 갖는 반도체소자 및 그제조 방법
KR100590397B1 (ko) * 2004-07-22 2006-06-19 주식회사 하이닉스반도체 반도체 소자의 패시베이션층 형성 방법
KR100865365B1 (ko) * 2005-01-12 2008-10-24 샤프 가부시키가이샤 반도체 장치의 제조방법 및 반도체 장치
DE102005004708B4 (de) * 2005-02-02 2006-11-02 Atmel Germany Gmbh Verfahren zur Herstellung integrierter Schaltkreise mit mindestens einem Silizium-Germanium-Heterobipolartransistor
US7364997B2 (en) * 2005-07-07 2008-04-29 Micron Technology, Inc. Methods of forming integrated circuitry and methods of forming local interconnects
KR20080095621A (ko) * 2007-04-25 2008-10-29 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
DE102007063271B4 (de) * 2007-12-31 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines dielektrischen Zwischenschichtmaterials mit unterschiedlichen Abtragsraten während eines CMP-Prozesses
US8822287B2 (en) * 2010-12-10 2014-09-02 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices
CN102543839B (zh) * 2010-12-22 2014-01-08 中国科学院微电子研究所 层间电介质层的平面化方法
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
US4972251A (en) * 1985-08-14 1990-11-20 Fairchild Camera And Instrument Corp. Multilayer glass passivation structure and method for forming the same
US5268333A (en) * 1990-12-19 1993-12-07 Samsung Electronics Co., Ltd. Method of reflowing a semiconductor device
JP2538722B2 (ja) * 1991-06-20 1996-10-02 株式会社半導体プロセス研究所 半導体装置の製造方法
US5166093A (en) * 1991-07-31 1992-11-24 Micron Technology, Inc. Method to reduce the reflectivity of a semi-conductor metallic surface
JP2809018B2 (ja) * 1992-11-26 1998-10-08 日本電気株式会社 半導体装置およびその製造方法
US5278103A (en) * 1993-02-26 1994-01-11 Lsi Logic Corporation Method for the controlled formation of voids in doped glass dielectric films
US5532191A (en) * 1993-03-26 1996-07-02 Kawasaki Steel Corporation Method of chemical mechanical polishing planarization of an insulating film using an etching stop
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
US5516729A (en) * 1994-06-03 1996-05-14 Advanced Micro Devices, Inc. Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
US5385868A (en) * 1994-07-05 1995-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Upward plug process for metal via holes
KR960005761A (ko) * 1994-07-27 1996-02-23 이데이 노부유끼 반도체장치
JP3326974B2 (ja) * 1994-07-28 2002-09-24 ソニー株式会社 多層配線の形成方法および半導体装置の製造方法
US5494854A (en) * 1994-08-17 1996-02-27 Texas Instruments Incorporated Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films
US5552346A (en) * 1995-04-27 1996-09-03 Taiwan Semiconductor Manufacturing Co. Planarization and etch back process for semiconductor layers
US5770469A (en) * 1995-12-29 1998-06-23 Lam Research Corporation Method for forming semiconductor structure using modulation doped silicate glasses
US5545585A (en) * 1996-01-29 1996-08-13 Taiwan Semiconductor Manufacturing Company Method of making a dram circuit with fin-shaped stacked capacitors
US5656556A (en) * 1996-07-22 1997-08-12 Vanguard International Semiconductor Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures
US5716890A (en) * 1996-10-18 1998-02-10 Vanguard International Semiconductor Corporation Structure and method for fabricating an interlayer insulating film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646688A (zh) * 2011-02-22 2012-08-22 索尼公司 半导体装置及其制造方法、半导体晶片层叠法和电子设备
CN102646688B (zh) * 2011-02-22 2016-09-21 索尼公司 半导体装置及其制造方法、半导体晶片层叠法和电子设备
CN113437134A (zh) * 2021-06-22 2021-09-24 福建省晋华集成电路有限公司 一种半导体结构、半导体结构制备方法及半导体装置
CN113437134B (zh) * 2021-06-22 2022-09-02 福建省晋华集成电路有限公司 一种半导体结构、半导体结构制备方法及半导体装置

Also Published As

Publication number Publication date
KR100211540B1 (ko) 1999-08-02
TW381305B (en) 2000-02-01
KR970077325A (ko) 1997-12-12
US5880039A (en) 1999-03-09
CN1090818C (zh) 2002-09-11

Similar Documents

Publication Publication Date Title
CN1090818C (zh) 用以形成半导体装置的中间层绝缘薄膜的方法
US5989997A (en) Method for forming dual damascene structure
TWI544573B (zh) 半導體積體電路基板之絕緣結構及其製造方法
CN100549820C (zh) 改善双镶嵌蚀刻轮廓的方法
JPH06295876A (ja) 半導体装置の製造方法
KR20000011863A (ko) 금속간유전체반도체제조시플루오르화실리케이트글래스필름에대한실리콘옥시니트라이드캡
CN1154186C (zh) 半导体器件的金属化
US7119015B2 (en) Method for forming polysilicon plug of semiconductor device
US5981376A (en) Method of forming viahole
TW200525774A (en) Semiconductor device and method of fabricating the same
EP0485086A1 (en) Dielectric layers for integrated circuits
US6221776B1 (en) Anti-reflective coating used as a disposable etch stop
JPH10116904A (ja) 半導体装置の製造方法
KR970053422A (ko) 반도체 소자의 소자분리막 형성방법
EP0853814B1 (en) An efficient and economical method of planarization of multilevel metallization structures in integrated circuits using cmp
CN1173395C (zh) 以覆盖层制造铜内连线的方法
CN1254852C (zh) 制作电绝缘层的方法
CN1229268A (zh) 金属层间介电层及其制造方法
KR0177396B1 (ko) 반도체 디바이스의 표면 평탄화 방법
US6593228B2 (en) Method of fabricating a patterned metal-containing layer on a semiconductor wafer
US6537917B2 (en) Method for fabricating electrically insulating layers
KR100338115B1 (ko) 반도체소자의금속층형성방법
CN1242466C (zh) 降低浅沟渠隔离侧壁氧化层应力与侵蚀的方法
KR100569508B1 (ko) 반도체소자의 평탄화방법
JP3309570B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee