CN1154186C - 半导体器件的金属化 - Google Patents
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Abstract
一种用于在一个基片上形成多条导线的方法，包括步骤：在基片的表面形成一个相对非平面的金属层；在该金属层的表面上沉积自平面化材料，以形成与相对非平面的金属层相比具有相对平面的表面的平面化层；在平面化层的表面沉积一个光致抗蚀层；对光致抗蚀层构图，使其形成掩模，以便选择性地暴露平面化层；在平面化层的暴露部分和平面化层暴露部分之下的非平面的金属层上蚀刻出沟槽，以形成导线，其中这些导线被沟槽隔离开。
Description
本发明总体上涉及一种半导体器件的金属化，尤其涉及在集成电路基片上对金属层进行构图使其成为一些导线。
本技术领域内公知，在现代集成电路金属化工艺中，导线是用光刻和化学腐蚀工艺在集成电路基片上形成的。在此工艺中，光致抗蚀层沉积于金属层表面，在金属层中将形成一些导线。将具有所需导线图案的掩模置于光致抗蚀层之上。用光线照射掩模，光线通过掩模开孔处照射到光致抗蚀层暴露的部分。因而该光致抗蚀层便在光照下显影，其暴露部分被去除。构图了的光致抗蚀层用作腐蚀掩模，以腐蚀掉被显影了的光致抗蚀层掩模所暴露的金属层。因此，光致抗蚀掩模的图案转换到金属层上，从而金属层被构图成导线。
在形成四分之一微米数量级宽度的导线时，要求光致抗蚀层具有极高的平面度。然而，在形成金属层时它却具有非平面的表面，因为在它下面的表面是非平面的。所以，如果把光致抗蚀层沉积到所述金属化层上，通常该光致抗蚀层是不一致的，将具有不均匀的厚度。有一种工艺可获得均匀厚度的光致抗蚀剂层，即用化学机械抛光(CMP)技术把下面的待沉积金属层的表面进行平面化处理。但是，这种CMP技术是比较昂贵的。
根据本发明，提供了一种在基片上形成多条导线的方法。该方法包括：在基片的一个表面上形成一个相对非平面的金属层。在该金属层上沉积一层自平面化材料。该自平面化材料在金属层表面形成一个平面化层。该平面化层与所述相对非平面的金属层相比，具有一个相对平面的表面。在所述平面化层上沉积一光致抗蚀层。该光致抗蚀层具有一个平面表面并被构图一些沟槽以制成掩模。这些沟槽暴露出其下面的平面化层的部分。所述光致抗蚀掩模作为一个掩模用于对平面化层的暴露部分刻蚀沟槽。所述被刻蚀了的平面化层形成第二个掩模。该第二个掩模暴露其下方相对非平面的金属层部分。该第二个掩模用于在相对非平面的金属层中刻蚀沟槽以在其中形成多条导线。这些导线彼此被在相对非平面的金属层中形成的沟槽隔离开来。
根据本发明的另一个特征，形成平面化层的步骤中包括旋涂自平面化材料的步骤。
根据本发明的另一个特征，所述旋涂步骤包括旋涂一种有机聚合物的步骤，例如，一种含硅的有机聚合物，或一种流动性氧化物，或一种氢化倍半氧化硅(hydrogensilsesquioxane)，或二乙烯基硅氧烷苯并环丁烯(divinyl-siloxane-benzocyclobutene)。
根据本发明的又一个特征，刻蚀金属层的步骤包括利用反应离子刻蚀的步骤。
本发明的其它特征以及本发明本身，从以下结合附图的详细描述中会变得更加明显，其中：
图1-6均为横截面示意图，显示了一个具有多条导线的基片，这些导线是按照本发明的各个制造步骤而在其中形成的；图2A是按照本发明处于一个制造步骤时的基片的横截面示意图。
参照图1，包括例如硅片的半导体基片10。值得注意的是，基片10的上表面12是相对非平面的表面。这种非平面性典型地是在基片10上形成各种元件或结构所产生的。例如，基片10的上表面12可以是形成于栅极上的二氧化硅绝缘层13和形成于硅基片10的外延层内的电极接触区(未图示)。
一个金属层14形成于基片10之上，尤其是覆盖于基片10的相对非平面的表面12之上(即绝缘层13之上)，如图1所示。这里，金属层14是一个复合层，下层是较薄的钛/氮化钛，中间是较厚的铝溅射层，上层是较薄的钛/氮化钛防反射覆盖层(ARC)。无论如何，用以形成该金属层的沉积/溅射工艺将形成一个一致性沉积。因此，金属层14具有均匀厚度，从而其上表面15也是一个相对非平面的表面，而且与基片10的非平面的上表面12的非平面的形貌相一致，如图1所示。
其次，参照图2，一个平面化层16形成于金属层14的表面15之上。根据本发明，该平面化层16形成一个非一致性层。即，与金属层14的表面15的一些相对非平面的表面部分例如15a、15b相对比，平面化层16形成一个大致平面的上表面层18，如图所示。
在一个实施例中，一种自平面化材料沉积于金属层14上，以形成平面化层16。例如，该平面化层16可由旋涂氧化硅玻璃(SOG)形成。另外一些可用作旋涂平面化层的材料包括：一种Dow-Corning公司生产和销售的流动性氧化物如氢化倍半氧化硅(hydrogensilsesquioxane)玻璃FOx-15；一种含硅有机聚合物；或二乙烯基硅氧烷苯并环丁烯(divinyl-siloxane-benzocyclobutene)。旋涂这些材料可产生自平面化层16。将材料旋涂上并使其流动而实现自平面化，而后在约150～300℃下烘烤大约1分钟以去除残留溶剂和实现再流动。所生成的自平面化层16(见图2)是比较坚硬的。该平面化层具有足够厚度，以使其上表面19在再流动后是个平面。典型地，该平面的厚度不超过300～2000。
可作替代的是，平面化层16包括，例如，一个如图2A所示的复合层。如图中所示，该复合平面化层16包括一个旋涂二氧化硅玻璃，作为底部16a和一个形成于其上的一个帽层或上层16b。该帽层包括一种介电材料。该帽层促进光致抗蚀剂层和平面化层的粘着。在一个实施例中，该帽层16b包括二氧化硅，它的形成，例如，可采用等离子增强化学气体沉积方法(PE CVD)。该二氧化硅是用PE CVD方法，在大约400℃或以下的温度沉积的，具有一个足够的厚度，以提高光致抗蚀材料和平面化材料间的粘着。在一个实施例中，该帽层的厚度约在300～500，优选约400～500，更优选为500。
再其次，光致抗蚀层18(如图3所示)旋涂于平面化层16(即，或者是如图2所示的单一平面化层16，或者是如图2A所示的复合平面化层16)的平面的表面19上。用一掩模(未图示)在光源下对光致抗蚀层的某些部分进行曝光，例如，可采用常规步进式光刻机曝光。光致抗蚀剂层被曝光源曝光的部分被聚合。光致抗蚀材料因此而显影，光致抗蚀层曝光的或聚合的部分被去除，形成沟槽或切口20。该光致抗蚀层未被去除的部分便成为掩模，用于对其下各层构图。如图所示，该掩模用于对其下的平面化层16的被暴露出的各部分25构图。例如，暴露部分25对应于将导线分隔开的区域，这些导线形成于金属导电层14中。可替代的是，一种负性光致抗蚀层18也是可采用的。应用负性光致抗蚀层将导致未暴露的部分被显影去除。
如图4所示，光致抗蚀掩模28用于刻蚀在光致抗蚀层沟槽以内所暴露的平面化层部分。该暴露部分是例如用反应离子刻蚀(RIE)被各向异性蚀的的。该平面化层与金属层相比更易被反应离子刻蚀，即平面化层16比金属层14的刻蚀速率高。因此，金属层14对反应离子刻蚀来说用作一个刻蚀阻止层。通过反应离子刻蚀暴露出金属层14的某些部分26。在一个实施例中，该平面化层是用含氟离子的化学物，如CF4，C4F8或CHF3进行反应离子刻蚀的。
下一步，用光致抗蚀掩模层18的存留部分，以及在平面化层16中形成的第二掩模28(即用第二掩模28暴露出其下面的金属层14的非平面的表面部分)，金属层14中被暴露部分用反应离子刻蚀腐蚀掉，以在介电层13上方形成一些导线36，如图4所示。(应当注意到，导线36的走向与图4的平面垂直)。在一个示范性实施例中，RIE是用氯离子化学物实现的。
就是说利用在平面化层16上形成的第二掩模28(见图4、5)，沟槽38被刻蚀入相对的非平面的导电金属层14中，形成多条导线36。导线36被在相对的非平面的金属层14中形成的沟槽38与形成于基片10表面之上的介电层13所绝缘分开，如图6所示。典型地，刻蚀液对金属层下面的材料是选择性的。因此，下面这一层就成为刻蚀阻止层。
再下一步，剥掉光致抗蚀层，而后去除平面化层16，例如，可用一种湿化学物。在一个实施例中，湿化学物包括高度稀释的氟化氢溶液(例如水与氟化氢配比为200∶1的溶液)或者是负性光致抗蚀显影液，形成如图6所示的结构。值得注意的是，如果第二个金属化层被采用，则只去掉光致抗蚀层18，然后在此结构上和沟槽38中沉积上平面化介质表面。这种平面化的介质结构的形成，可以采用SOG法，如同形成图2所示的单层结构16或图2A所示的复合结构16。可以替代的是，可把二氧化硅层沉积到刻槽结构的表面上，采用的方法是亚大气化学气相沉积法(SA CVD)，或高浓度等离子沉积(HDP)工艺。然后，第二金属化层被沉积到经过构图的平面化层16上(图5)。值得指出的是，如果第二金属层的平面度不够，则将自平面化材料(即结构层16)旋涂到第二金属化层表面上之后，再按照已经在前面结合图4～6所描述的步骤进行操作，以制备第二层的多条导线。
尽管本发明已经参照各个实施例进行了具体的说明和描述，但是本领域的技术人员会明白，在不超出本发明范围的情况下仍可以对其进行各种修正和更改。仅作为举例，可用一种气相沉积工艺代替利用旋涂沉积材料的工艺，可以形成如同所述旋涂玻璃材料而获得具有类似的流动性的自平面化材料，用于气相沉积的一种材料是PMT-Electrotech，Chatsworth，CA公司所售的Flowfill流动填充材料。因此，本发明的范围不限于以上描述，而是由后附的权利要求书及其等同物所界定。
Claims (9)
1、一种用于在一个基片上形成多条导线的方法，包括以下步骤：
在所述基片的一个表面形成一个相对非平面的金属层；
在该金属层的表面上沉积一种自平面化材料，以形成一个与所述相对非平面的金属层相比具有一个相对平面的表面的平面化层，该平面化层是通过旋涂所述自平面化材料形成的，该自平面化材料选自氢化倍半氧化硅和二乙烯基硅氧烷苯并环丁烯；
在所述平面化层的表面沉积一个光致抗蚀层；
对该光致抗蚀层进行构图，使构图了的光致抗蚀层形成一个掩模，以便选择性地暴露所述平面化层的某些部分；
在所述平面化层的暴露部分和该平面化层暴露部分之下的非平面的金属层上蚀刻出沟槽，以形成一些导线，其中这些导线被沟槽隔离开。
2、根据权利要求1所述的方法，其中，所述形成平面化层的步骤包括在所述自平面化材料上沉积一个介电层的步骤。
3、根据权利要求1所述的方法，其中，刻蚀所述金属层的步骤包括应用反应离子刻蚀的步骤。
4、根据权利要求3所述的方法，包括刻蚀金属层步骤中的去除平面化层的步骤。
5、根据权利要求4所述的方法，其中，去除平面化层的步骤包括对该平面化层进行湿法化学刻蚀的步骤。
6、一种用于在一个基片上形成多条导线的方法，包括下列步骤：
在所述基片的一个相对非平面的表面上形成一个金属层，该金属层具有非平面的表面部分；
在所述金属层的表面沉积一个平面化层，该平面化层具有一个与所述金属层的相对非平面的表面部分相比相对平面的表面，该平面化层是通过旋涂所述自平面化材料形成的，该自平面化材料选自氢化倍半氧化硅和二乙烯基硅氧烷苯并环丁烯；
在所述平面化层的表面沉积一个光致抗蚀层；
将该光致抗蚀层构图为多个沟槽，以形成一个掩模，借助于这些沟槽暴露其下的平面化层部分；
利用该光致抗蚀掩模，在所述平面化层的暴露部分刻蚀沟槽，以形成第二掩模，以暴露其下的金属层的非平面表面部分；以及
利用在所述平面化层中形成的掩模，在相对非平面的金属层中刻蚀沟槽，以形成多条导线，这些导线被所述形成于相对的非平面的金属层中的沟槽隔离开来。
7、根据权利要求6所述的方法，其中，刻蚀金属层的步骤包括利用一种反应离子刻蚀的步骤。
8、根据权利要求7所述的方法，包括刻蚀金属层步骤中的去除平面化层的步骤。
9、根据权利要求8所述的方法，其中，所述去除平面化层的步骤包括对该平面化层进行湿法化学刻蚀的步骤。
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| US829257 | 1986-02-14 | ||
| US08/829,257 US5854126A (en) | 1997-03-31 | 1997-03-31 | Method for forming metallization in semiconductor devices with a self-planarizing material |
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| CN1195194A CN1195194A (zh) | 1998-10-07 |
| CN1154186C true CN1154186C (zh) | 2004-06-16 |
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| EP (1) | EP0875928B1 (zh) |
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| CN (1) | CN1154186C (zh) |
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| US6117345A (en) * | 1997-04-02 | 2000-09-12 | United Microelectronics Corp. | High density plasma chemical vapor deposition process |
| US6218078B1 (en) * | 1997-09-24 | 2001-04-17 | Advanced Micro Devices, Inc. | Creation of an etch hardmask by spin-on technique |
| US6071824A (en) * | 1997-09-25 | 2000-06-06 | Advanced Micro Devices, Inc. | Method and system for patterning to enhance performance of a metal layer of a semiconductor device |
| US6221775B1 (en) * | 1998-09-24 | 2001-04-24 | International Business Machines Corp. | Combined chemical mechanical polishing and reactive ion etching process |
| US6420251B1 (en) * | 1999-01-05 | 2002-07-16 | Trw Inc. | Method for fabricating a microelectronic integrated circuit with improved step coverage |
| US6472291B1 (en) | 2000-01-27 | 2002-10-29 | Infineon Technologies North America Corp. | Planarization process to achieve improved uniformity across semiconductor wafers |
| US6812130B1 (en) | 2000-02-09 | 2004-11-02 | Infineon Technologies Ag | Self-aligned dual damascene etch using a polymer |
| EP1837902B1 (en) | 2000-08-21 | 2017-05-24 | Dow Global Technologies LLC | Use of organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices |
| US6630407B2 (en) | 2001-03-30 | 2003-10-07 | Lam Research Corporation | Plasma etching of organic antireflective coating |
| ATE485627T1 (de) * | 2001-08-14 | 2010-11-15 | Nxp Bv | Elektronisches bauelement und verfahren zur herstellung |
| US6881664B2 (en) * | 2001-08-28 | 2005-04-19 | Lsi Logic Corporation | Process for planarizing upper surface of damascene wiring structure for integrated circuit structures |
| KR100457740B1 (ko) * | 2002-01-09 | 2004-11-18 | 매그나칩 반도체 유한회사 | 반도체소자의 다층 금속배선 형성방법 |
| US7009811B2 (en) * | 2002-07-11 | 2006-03-07 | International Business Machines Corporation | Surface planarization processes for the fabrication of magnetic heads and semiconductor devices |
| JP2006253585A (ja) * | 2005-03-14 | 2006-09-21 | Fujitsu Ltd | 半導体装置の製造方法 |
| CN100505159C (zh) * | 2007-08-21 | 2009-06-24 | 中国科学院上海微系统与信息技术研究所 | 非平面表面金属微细图形化的方法 |
| US9142400B1 (en) | 2012-07-17 | 2015-09-22 | Stc.Unm | Method of making a heteroepitaxial layer on a seed area |
| EP3953746A4 (en) * | 2019-04-11 | 2023-05-10 | Applied Materials, Inc. | STRUCTURING OF MULTI-DEPTH OPTICAL DEVICES |
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| US4510173A (en) * | 1983-04-25 | 1985-04-09 | Kabushiki Kaisha Toshiba | Method for forming flattened film |
| US4758305A (en) * | 1986-03-11 | 1988-07-19 | Texas Instruments Incorporated | Contact etch method |
| US4770739A (en) * | 1987-02-03 | 1988-09-13 | Texas Instruments Incorporated | Bilayer photoresist process |
| US5126289A (en) * | 1990-07-20 | 1992-06-30 | At&T Bell Laboratories | Semiconductor lithography methods using an arc of organic material |
| US5217568A (en) * | 1992-02-03 | 1993-06-08 | Motorola, Inc. | Silicon etching process using polymeric mask, for example, to form V-groove for an optical fiber coupling |
| US5264076A (en) * | 1992-12-17 | 1993-11-23 | At&T Bell Laboratories | Integrated circuit process using a "hard mask" |
| US5567661A (en) * | 1993-08-26 | 1996-10-22 | Fujitsu Limited | Formation of planarized insulating film by plasma-enhanced CVD of organic silicon compound |
| JP2751820B2 (ja) * | 1994-02-28 | 1998-05-18 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
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- 1998-03-17 DE DE69834686T patent/DE69834686T2/de not_active Expired - Fee Related
- 1998-03-17 EP EP98104745A patent/EP0875928B1/en not_active Expired - Lifetime
- 1998-03-31 KR KR1019980011130A patent/KR19980080906A/ko not_active Application Discontinuation
- 1998-03-31 JP JP10086486A patent/JPH10308386A/ja not_active Withdrawn
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| EP0875928A3 (en) | 1998-12-30 |
| DE69834686D1 (de) | 2006-07-06 |
| JPH10308386A (ja) | 1998-11-17 |
| DE69834686T2 (de) | 2007-05-31 |
| EP0875928B1 (en) | 2006-05-31 |
| US5854126A (en) | 1998-12-29 |
| CN1195194A (zh) | 1998-10-07 |
| EP0875928A2 (en) | 1998-11-04 |
| KR19980080906A (ko) | 1998-11-25 |
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