CN1090818C - 用以形成半导体装置的中间层绝缘薄膜的方法 - Google Patents

用以形成半导体装置的中间层绝缘薄膜的方法 Download PDF

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CN1090818C
CN1090818C CN97112407A CN97112407A CN1090818C CN 1090818 C CN1090818 C CN 1090818C CN 97112407 A CN97112407 A CN 97112407A CN 97112407 A CN97112407 A CN 97112407A CN 1090818 C CN1090818 C CN 1090818C
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CN1172344A (zh
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李相奎
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Abstract

一种用以形成半导体装置的中间层绝缘薄膜的方法被揭示。第一中间层绝缘薄膜被淀积在一具有高的阶梯元件区域与低的阶梯周边区域的半导体装置的整个上表面之上，接着做热处理。较该第一中间层绝缘薄膜更能抵抗蚀刻的第二中间层绝缘薄膜被淀积。再者，第三中间层绝缘薄膜被淀积，接着做热处理。这些中间层绝缘薄膜借助于一CMP工艺而被平坦化。在该CMP工艺中，该第一中间层绝缘薄膜被快速蚀刻，而该第二中间层绝缘薄膜则被缓慢除去。

Description

用以形成半导体装置的中间层绝缘薄膜的方法
技术领域
本发明一般涉及一种用以形成半导体装置的中间层绝缘薄膜的方法，特别涉及在为使中间层绝缘薄膜平坦化的化学机械抛光中，利用一种高密度的等离子体氧化物薄膜作为一种抛光减速器(retarder)。
背景技术
主要产生自半导体元件高度集成化的结果的半导体装置的高阶梯(step)有可能引起所谓的缺口化(notching)，一种产生自光刻工艺中的漫反射的图形缺陷问题。此使得接续的工艺难以进行。
为了解决此问题，将该高阶梯掩埋覆盖以一种绝缘材料的平坦化技术已被提出。在半导体装置的高度集成化中，这些平坦化的技术现已被认为是一种非常重要的工艺，因为其有助于后续的工艺。
通常为了将一具有高阶梯覆盖的半导体装置平坦化，一种掺杂有高密度的硼(B)与磷(P)的硼磷硅玻璃(以下称做“BPSG”)薄膜被使用，且将其在高温下处理。
然而，此种利用BPSG薄膜的平坦化工艺在制造具有高集成度的例如为256M或更多的DRAM的半导体装置中仍会引起缺口化的问题，其中介于元件(cell)区域与周边区域之间的阶梯覆盖被保持在0.8至1.0μm的高度。
此外，由于在半导体装置中金属线被要求为更窄，一种利用例如为深UV的更短波作为光源的步进机被用于其光刻。然而，此种步进机的聚焦深度变为小到大约为0.4μm，这使其无法形成金属线用的光致抗蚀剂图形。即使该光致抗蚀剂图形被形成，所产生的金属线不是易于断开、就是产生一跨接(bridge)的问题。在此，为了在一晶片上利用一暴光掩模经由一光学透镜形成一图形，该聚焦深度被定义成如下。当焦点被带入晶片的中时，虚像呈现在该晶片以该透镜的中心为基准的上方及下方的位置。换言的，该聚焦深度为介于该透镜与该最靠近透镜的影像的间的长度的两倍。
在高度集成的半导体元件中，一种不同的方法已被发展来克服上述的难题。一种利用化学浆体的化学机械抛光(以下称做“CMP”)技术现已被利用来抛光与平坦化该高阶梯的覆盖。
为了更深入了解本发明的背景，一种公知的CMP技术参照图1与2的说明将被提出。
首先，如图1中所示，制备一半导体基板1其中一底层结构3被制得。借助于形成一场氧化薄膜而将半导体元件分开、形成一栅电极、提供一源极与漏极、以及形成一位线与一电容。为了方便起见，这些在图1与2中被省去。
然后，一具有大约为1000埃厚的BPSG薄膜5，其厚于介于元件区域100与周边区域200的间的阶梯覆盖，而被淀积在该底层结构3的上，接着在800℃或是更高的温度下做该BPSG薄膜5的热处理。
然后，如图2中所示，为了上部的结构的平坦化，一种CMP的工艺被进行来蚀刻该BPSG薄膜5。在此时，该蚀刻作用在周边区域200以及该元件区域100。因此，虽然在图2中标示“B”的阶梯覆盖小于在图1中标示“A”的阶梯覆盖，在此CMP的工艺之后其仍然存在。
如上所述，该CMP工艺借助于厚厚地淀积该BPSG薄膜并且用化学药剂将其机械地抛光而容许该阶梯覆盖被降低。然而，由于该元件区域是沿着该周边区域被抛光的CMP工艺的凹曲(dishing)效应，要获得整个的平坦化是困难的，并且因此接续的步骤并不能顺利地进行。于是，许多的问题产生，其包含在半导体装置高度集成化的困难以及因此所得到的半导体装置在特性与可靠度上的劣化。
由于只有某一特定的厚度的BPSG薄膜被抛光，公知的CMP额外需要一终点的检测器，例如为一用以感测与马达速度有关的电流变化的检测器、或是一光学式的检测器。该点检测一个因素增加了半导体装置的工艺成本。再者，运作该检测器的协定增加了半导体装置的整体制造过程的复杂度，以导致生产率的降低。
发明内容
本发明的一目的在于克服公知技术所遭遇到的上述的问题，并且在于提供一种用以形成半导体装置的中间层绝缘薄膜的方法，其可达成半导体装置的特性、可靠度、生产率以及高集成度的明显改善。
根据本发明的第一特点，提供了一种用以形成半导体装置的中间层绝缘薄膜的方法，其包含步骤：提供一包括较低结构层的半导体基板，该半导体基板具有元件区域和周边区域，在元件区域和周边区域之间具有高台阶覆盖；在该较低结构层的整个上表面之上形成一第一中间层绝缘薄膜并且将该第一中间层绝缘薄膜做热处理，上述第一中间绝缘薄膜具有第一蚀刻选择性；在第一中间层绝缘薄膜上形成高密度的等离子体氧化物薄膜，该高密度的等离子体氧化物薄膜具有与第一蚀刻选择性不同的第二蚀刻选择性；在高密度的等离子体氧化物薄膜上形成第二中间层绝缘薄膜并且将该该第二中间层绝缘薄膜做热处理，上述第二中间层绝缘薄膜具有第一蚀刻选择性；以及利用化学机械抛光工艺蚀刻第二中间层绝缘薄膜、高密度的等离子体氧化物薄膜和第一中间层绝缘薄膜以平坦化，而暴露出在较低结构的周边区域的高密度的等离子体氧化物薄膜。
根据本发明的另一个特点，提供了一种用以形成半导体装置的中间层绝缘薄膜的方法，其包含步骤：提供一包括较低结构层的半导体基板，该半导体基板具有元件区域和周边区域，在元件区域和周边区域之间具有高台阶覆盖；在该较低结构层的整个上表面之上形成一第一BPSG薄膜并且将该第一BPSG薄膜做热处理，上述第一中间绝缘薄膜具有第一蚀刻选择性；在第一BPSG薄膜上形成高密度的等离子体氧化物薄膜，该高密度的等离子体氧化物薄膜具有与第一蚀刻选择性不同的第二蚀刻选择性；在高密度的等离子体氧化物薄膜上形成第二BPSG薄膜并且将该该第二BPSG薄膜做热处理，上述第二BPSG薄膜具有第一蚀刻选择性；以及利用化学机械抛光工艺蚀刻第二BPSG薄膜、高密度的等离子体氧化物薄膜和第一BPSG薄膜以平坦化，而暴露出在较低结构的周边区域的高密度的等离子体氧化物薄膜。
附图说明
本发明的其它的目的与特点将从以下的实施例的说明并参照附图而更为明显，其中：
图1与2为表示一种公知的用以形成半导体装置的中间层绝缘薄膜的方法的概要剖面图；以及
图3与4为表示一种根据本发明的用以形成半导体装置的中间层绝缘薄膜的方法的概要剖面图。
具体实施方式
参照该附图对本发明的较佳实施例的应用会更好的了解，其中同样的参考图号被分别用于同样与对应的部件上。
参照图3与4说明根据本发明的用以形成半导体装置的中间层绝缘薄膜的工艺。
如图3中所示，准备一半导体基板11，于其上建立一底层结构13以包含一用以将元件分开的场氧化薄膜、一栅电极、源极与漏极、一位线以及一电容，其中全部均未显示。
然后，一厚度约为1000至5000埃且厚于该介于一元件区域300与一周边区域400的阶梯覆盖的第一BPSG绝缘薄膜15被淀积在该底层结构13的上表面之上以作为一第一中间层绝缘薄膜。或者是，不用该第一BPSG绝缘薄膜15，一种BSG薄膜或是其它的绝缘薄膜可被使用。例如，一种O3-TEOS的氧化硅薄膜可利用常压的化学气相淀积(APCVD)或是低压的化学气相淀积(LPCVD)而被淀积。再者，一种经由等离子体增强的化学气相淀积(PECVD)而淀积得到的氧化硅薄膜可取代该第一BPSG绝缘薄膜15。
一约在700至900℃的热处理被进行以稳定该第一BPSG绝缘薄膜15。
接着，一作为一第二中间层绝缘薄膜之高密度的等离子体氧化物薄膜17以一厚度约为500至3000埃而被淀积在该所产生的结构上。为达成此目的，一种电子回旋加速器共振(ECR)的化学气相淀积技术、一种螺旋波的CVD技术或是一种电感耦合等离子体(ICP)的化学气相淀积技术被使用。
其后，具有大约为2000至10000埃的厚度的第二BPSG绝缘薄膜19被淀积在该高密度的等离子体氧化物薄膜17之上作为一第三中间层绝缘薄膜，在等离子体密度范围从约为1010至1012离子/厘米2且在700-900℃的温度下对第二BPSG绝缘薄膜进行热处理使之稳定。
然后，如图4中所示，一个CMP工艺被执行以将该元件区域300与周边区域400平坦化。在此例中，该高密度的等离子体氧化物薄膜17被当作一个比该BPSG薄膜15更能抵挡抛光的阻挡层，因而该凹曲的现象并未发生。
根据本发明，该CMP工艺在该抛光头的压力被设为5到7psi、旋转速度为20至50rpm、该平台的桌面速度为15至40rpm以及该抛光头的背压为0到2psi的情形下被进行。作为一种悬浮的化学品，一种例如为KOH或是NH4OH的碱性溶液被用来防止该抛光粒聚集成更大的颗粒或是沉淀。
如同之前所述，根据本发明的用以形成半导体装置的中间层绝缘薄膜的方法的特征在于利用一高密度的等离子体氧化物薄膜于一CMP工艺中。当一包含有该第一BPSG绝缘薄膜、该高密度的等离子体氧化物薄膜与该第二BPSG绝缘薄膜的堆积结构被送至一CMP工艺处理时，该氧化物薄膜被缓慢地被除去，而该BPSG绝缘薄膜则快速地被完成，因而此种在蚀刻上的差异容许该抛光终点容易地被检测。此外，较低阶梯的周边区域可避免被过度抛光，于是一完全平坦而毫无凹曲的问题的结构可被获得，因此使接续的工艺变得容易。于是，本发明具有改善半导体装置的可靠度与生产率且获得半导体装置的高集成度的极大优点。
本发明已用一种说明的性质而被描述，并且应了解的是所使用的词汇是用作说明而并不是用做限制。
本发明的许多修改与变化在上述的指教之下是可能的。因此，应了解的是在所附的申请专利范围的范畴中，本发明可用不同于以上所特别描述的方式来实行。

Claims (18)

1.一种用以形成半导体装置的中间层绝缘薄膜的方法，其包含步骤：
提供一包括较低结构层的半导体基板，该半导体基板具有元件区域和周边区域，在元件区域和周边区域之间具有高台阶覆盖；
在该较低结构层的整个上表面之上形成一第一中间层绝缘薄膜并且将该第一中间层绝缘薄膜做热处理，上述第一中间绝缘薄膜具有第一蚀刻选择性；
在第一中间层绝缘薄膜上形成高密度的等离子体氧化物薄膜，该高密度的等离子体氧化物薄膜具有与第一蚀刻选择性不同的第二蚀刻选择性；
在高密度的等离子体氧化物薄膜上形成第二中间层绝缘薄膜并且将该该第二中间层绝缘薄膜做热处理，上述第二中间层绝缘薄膜具有第一蚀刻选择性；以及
利用化学机械抛光工艺蚀刻第二中间层绝缘薄膜、高密度的等离子体氧化物薄膜和第一中间层绝缘薄膜以平坦化，而暴露出在较低结构的周边区域的高密度的等离子体氧化物薄膜。
2.根据权利要求1的方法，其中该第一中间层绝缘薄膜是由硼磷硅玻璃所形成的。
3.根据权利要求1的方法，其中该第一中间层绝缘薄膜是利用一种常压的化学气相淀积技术的O3-TEOS的氧化硅薄膜所形成的。
4.根据权利要求1的方法，其中该第一中间层绝缘薄膜是利用一种低压的化学气相淀积技术的O3-TEOS的氧化硅薄膜所形成的。
5.根据权利要求1的方法，其中该第一中间层绝缘薄膜是利用一种等离子体增强的化学气相淀积技术的氧化硅薄膜所形成的。
6.根据权利要求1的方法，其中该第一中间层绝缘薄膜被淀积大约为1000至5000埃的厚度。
7.根据权利要求1的方法，其中该第一中间层绝缘薄膜在大约为700至900℃的温度下被热处理。
8.根据权利要求1的方法，其中该第二中间层绝缘薄膜是利用一种电子回旋加速器的化学气相淀积技术在范围从约为1010至1012个离子/厘米2的等离子体密度下由一高密的等离子体氧化物薄膜所形成的。
9.根据权利要求1的方法，其中该高密度的等离子体氧化物薄膜是利用一种螺旋波的化学气相淀积技术所形成的。
10.根据权利要求1的方法，其中该高密度的等离子体氧化物薄膜是利用一种电感耦合的等离子体化学气相淀积技术所形成的。
11.根据权利要求1的方法，其中该高密度的等离子体氧化物薄膜被形成大约为500至3000埃的厚度。
12.根据权利要求1的方法，其中该第二中间层层绝缘薄膜是由硼磷硅玻璃所形成的。
13.根据权利要求1的方法，其中该第二中间层绝缘薄膜是利用一种常压的化学气相淀积技术的O3-TEOS的氧化硅薄膜所形成的。
14.根据权利要求1的方法，其中该第二中间层绝缘薄膜是利用一种低压的化学气相淀积技术的O3-TEOS的氧化硅薄膜所形成的。
15.根据权利要求1的方法，其中该第二中间层绝缘薄膜是利用一种等离子体增强的化学气相淀积技术的氧化硅薄膜所形成的。
16.根据权利要求1的方法，其中该第二中间层绝缘薄膜被淀积大约为2000至10000埃的厚度。
17.根据权利要求1的方法，其中该化学机械抛光工艺是在一抛光头的压力被设为5到7psi、旋转速度为20至50rpm、该平台的桌面速度为15至40rpm以及该抛光头的背压为0到2psi的情况下被进行的。
18.根据权利要求1的方法，其中该化学机械抛光工艺借助于利用一种选自KOH或是NH4OH的碱性悬浮物而被进行。
CN97112407A 1996-05-22 1997-05-22 用以形成半导体装置的中间层绝缘薄膜的方法 Expired - Fee Related CN1090818C (zh)

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