CN1159760C - 制造高密度半导体存储器件的方法 - Google Patents
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Abstract
本发明公开一种制造高密度半导体存储器件的方法,其可以减少芯片尺寸并提高存储器件特性。本发明提供SOI型存储器件。电容器埋置在半导体晶片下面的绝缘体中,晶体管是在形成电容器之后形成的。结果,防止了晶体管的退化,充分地增加了电容器表面面积,并在处理步骤过程中提供完全平面化的表面。
Description
技术领域
本发明涉及制造高密度半导体存储器件的方法,特别涉及通过键合两体硅晶片制造利用SOI(绝缘体上硅)的高密度动态随机存取存储器(DRAMs)的方法。
背景技术
半导体存储器的位密度每三年增长四倍,其操作速度也随着增加。半导体存储器的这种发展使1Gb(千兆位)DRAM(动态随机存取存储器)或1GHz(千兆赫兹)的操作速度成为可能。
在DRAM器件中,在64K DRAM密度时代采用的8F2存储单元尺寸已经使用至今。从相对于读出放大器的位线排列来看,此8F2存储单元被称为折叠位线单元结构。8F2是折叠位线单元结构的最小理论单元尺寸。这里,F表示最小特征尺寸,并且通常由可以构图的最小设计规则确定。F也可以表示包括存储单元阵列的平行位线间距的一半(1/2)。例如,0.6μm间距的最小单元尺寸为8×0.3×0.3=0.72μm2。
图1A表示具有COB(位线上电容器)的8F2折叠位线单元结构的存储单元的布局,其中COB主要用在目前高密度DRAM中。图1B是沿着图1A的线1A-1A’截取的截面图。
参见图1A和1B,在形成器件隔离层2的半导体衬底1上形成具有栅极(字线(WL))和源/漏区(未示出)的晶体管6。形成接触焊盘以电连接到字线之间的有源区3。接触焊盘包括存储电极接触焊盘8a和位线接触焊盘8b。形成存储电极16和位线11,通过选择层间绝缘膜10,12分别与存储电极接触焊盘8a和位线接触焊盘8b连接。这里,位线11形成在存储电极16的下面,即在形成存储电极16之前形成位线11。
在前述COB存储单元结构中,由于在形成字线(WL)和位线11之后形成存储单元电容器,所以存储单元接触孔14不可避免地具有高的高宽比。换言之,层间绝缘膜12具有较厚的厚度,使得很难在其中开接触孔。为解决腐蚀高的高宽比接触孔14的问题,一般使用形成着陆焊盘(landing pad),即所谓单元焊盘的工艺。
但是,不可能在着陆焊盘应用中同时在栅上表面和源/漏上形成硅化物层,使得同时实现高性能逻辑器件和DRAM器件变得非常复杂和困难。另外,在形成存储单元接触过程中字线和位线的未对准可能引起存储单元和字线或存储单元和位线之间发生短路。这些内在问题妨碍减少DRAM单元密度和实现大容量和高性能DRAM单元。
一旦决定了最小特征尺寸(F),就确定了最小单元尺寸和根据DRAM密度计算出由阵列占据的面积。被阵列占据的面积用‘N位×单元尺寸’给出。例如在1Gb DRAM的情况下,N位对应于230(=1,073,741,824)。阵列面积相对于总芯片尺寸的比称为‘阵列效率’。在诸如64Mb DRAM或更高的高密度DRAM情况下,阵列效率约为65%。因而,芯片尺寸用下面作为最小特征尺寸(F)的函数的等式表示。
[等式]
SC=α-1×N位×8F2
这里,SC表示芯片尺寸,α表示阵列效率。根据前述等式由最小特征尺寸或密度所计算的DRAM芯片尺寸示于图2中。这里,芯片尺寸是根据在每个存储器件密度时代中的8F2折叠位线单元结构和65%的阵列效率计算的。
在图2中,希望1Gb芯片尺寸约为425mm2,4Gb的约为960mm2,16Gb的约为2000mm2。从这种大芯片尺寸获得好芯片生产率被认为是很困难的,并且众所周知,生产率与芯片尺寸成反比。因此对于有成本效率的高密度DRAM来说,必需以相同的最小特征尺寸制成存储单元。在本领域中众所周知,开放(open)线单元结构的最小单元尺寸是6F2(记住8F2是折叠位线单元结构的最小单元尺寸)。但是,开放位线单元结构的缺点是抗噪声性差和读出放大器布局困难。
最近报导了开放位线布局和折叠位线读出的结合方式。但是其也具有需要附加掩模的缺点。
发明内容
本发明是在考虑到上述问题做出的,因此本发明的目的是提供高密度半导体存储器件及其制造方法,能够减少器件隔离区,提供更大的有源区,并有利地减少器件尺寸。本发明采用键合晶片,即建立存储器件的SOI衬底。存储器件是如此制造在键合晶片上的,即减少了阱与阱之间的隔离需要的面积,还可以减少隔离间隔的尺寸,并由此减少芯片尺寸。
为达到此优点和其它优点并根据本发明的目的,提供两晶片,即处理晶片和支撑晶片。首先,在处理晶片上形成沟槽腐蚀掩模以确定有源区和无源区。然后腐蚀暴露的处理晶片以形成沟槽。在沟槽中和沟槽腐蚀掩模上淀积绝缘材料。进行平面化处理直到沟槽腐蚀掩模的上表面,由此形成沟槽隔离。沟槽隔离围绕有源区以电隔离每个有源区。腐蚀沟槽腐蚀掩模的选择部分,直到处理晶片的有源区,以形成用于电容器下电极的接触孔。在接触孔中和沟槽腐蚀掩模和沟槽隔离上淀积导电材料,然后构图以形成下电极。淀积绝缘膜和上电极以形成电容器。对上电极进行平面化。通过在处理晶片的平面化上电极和支撑晶片之间淀积键合绝缘层把它们键合在一起。对键合晶片的处理晶片的表面进行平面化直到沟槽隔离的上表面。在键合晶片的处理晶片的平面化表面上形成晶体管。该晶体管包括栅极和结区。在晶体管上形成层间绝缘膜以对其覆盖。腐蚀所选择的层间绝缘膜以形成暴露结区的位线接触孔。在位线接触孔中和层间绝缘膜上淀积导电材料并构图以形成位线。
在本发明的方案中,由于晶体管是在形成电容器之后形成的,所以可以减少晶体管的退化。没有去掉沟槽腐蚀掩模。而是,沟槽腐蚀掩模和沟槽隔离一同起围绕有源区的作用,因此可以使处理简化,并可以防止沟槽隔离特性的退化。
在本发明的另一方案中,有源区和相邻有源区之间的最小间隔比有源区的最小宽度小。位线和相邻位线之间的间隔比位线的宽度以及栅极之间的间隔小。
附图说明
参照下面的附图使本发明更易被理解,并且其目的对于本领域技术人员也很显然,其中:
图1A示意性地表示具有折叠位线单元结构的存储单元布局图;
图1B表示沿着图1A的线1A-1A’截取的COB叠置单元结构的截面图;
图2表示作为最小特征尺寸和单元面积的函数的阵列尺寸和芯片尺寸;
图3示意性地表示根据本发明实施例的存储单元布局图;
图4A表示沿着图3的线3X-3X’截取的截面图;
图4B表示沿着图3的线3Y-3Y’截取的截面图;
图5表示芯片尺寸和最小特征尺寸之间的关系;
图6A-6F表示根据本发明的实施例,在制造的选择阶段,形成在处理晶片上的存储器件的截面图;
图7A-7C分别表示沿着图6A-6C的线6A-6A’、6B-6B’、6C-6C’截取的截面图;
图7D表示键合在一起形成键合晶片的处理晶片和支撑晶片的截面图;
图7E表示在键合晶片的处理晶片表面上进行平面化处理之后键合晶片的截面图;和
图7F-7H分别表示沿着图6D-6F的线6D-6D’、6E-6E’和6F-6F’截取的截面图。
具体实施方式
下面参照附图说明本发明的优选实施例。本发明涉及使用键合晶片,即SOI衬底,制造高密度存储器件的方法。根据本发明,高密度存储器件被制造成具有小于8F2单元尺寸的设计规则的折叠位线单元结构。图3示意性地表示根据本发明的实施例的存储单元布局图,图4A和图4B分别表示沿着图3的线3X-3X’和3Y-3Y’截取的截面图。
参见图3和图4A,其上形成单元晶体管和存储节和,位线接触的有源区105完全被绝缘材料围绕,除了其上表面之外。具体地说,有源区105被器件隔离层104(这里为沟槽隔离)和沟槽腐蚀掩模102包围。而且,有源区105与周边单元和体硅电隔离。围绕有源区的绝缘材料包括氧化硅层、诸如硼磷硅酸盐玻璃的掺杂氧化硅层、和氮化硅层。
众所周知,氧化硅层的击穿电压比体硅的大1个数量级左右。因此,由氧化物封装的完全隔离可以大大节省在体硅中阱-阱结隔离所需要的面积,并能够完全消除闩锁(latch-up),这在体晶体管中有时是关注重点。相邻有源区之间的最小隔离间隔可以容易地从常规体硅中要求的一个‘F’缩减到‘αF’,其中α大于零且小于1。
从图3和图4B可以看出,沿着位线方向的最小特征尺寸是‘F’,但沿着字线的最小特征尺寸是‘αF’。这里,‘αF’对应隔离间隔尺寸。如上所述,隔离间隔尺寸的减小可以通过氧化物封装来实现。氧化硅层的击穿电压比体硅的大1个数量级左右。因此,可以通过氧化物封装来获得与体硅相比为大约十分之一沟槽隔离尺寸的沟槽隔离。因此,可以从相同的最小特征尺寸(‘F’)获得小于8F2,即大约4(1+α)F2的单元尺寸。根据最小特征尺寸,芯片尺寸相对于密度的评价根据1、0.5和0的α大小分别示于图5中。从图5中可以看出,如果α为1,对应常规折叠位线单元结构的最小单元尺寸。如果α为0.5,对应折叠位线单元结构的最小单元尺寸的四分之三。在这种情况下,芯片尺寸成比例减小。如果α为零,对应折叠位线单元尺寸结构的最小单元尺寸的一半,并且希望获得该单元尺寸以下的情况是不可能的。
再参见图3、图4A和图4B,存储单元电容器116被掩埋在薄硅晶片下面的绝缘体上,即形成在薄半导体衬底100a(处理晶片)和器件隔离区104的下面。存储单元电容器116包括存储节110、绝缘膜112和平板电极114。存储节通过层间绝缘层108中的接触孔109和沟槽腐蚀掩模102与晶体管210的源/漏区208电连接。由于存储单元电容器116被掩埋在有源器件下面的绝缘体中,所以在单元阵列区和周边区之间不产生高度差(台阶)。晶体管形成步骤之后的处理步骤与常规CMOS工艺相同。因此,其可应用于逻辑CMOS处理或埋置逻辑处理,其中DRAM和逻辑合并。
处理晶片100a和支撑晶片200使用设置在其间的键合氧化物层204键合在一起。在处理晶片100a上形成位线214,并通过所选择的层间绝缘层212与源/漏区208电连接。在位线214上形成另一层间绝缘层216,在层间绝缘层216上形成金属线218。
下面参照图6和7说明用于上述单元结构的制造工艺。图6A-6F表示根据本发明的实施例在制造的各选择阶段形成在处理晶片上的存储器件的截面图,图7A-7C分别表示沿着图6A-6C的线6A-6A’6B-6B’和6C-6C’截取的截面图。
参见图6A和7A,在半导体衬底100(处理晶片)上形成沟槽腐蚀掩模102,以确定有源区105和无源区。沟槽腐蚀掩模102是由绝缘材料制成,例如多层氧化物层102a和氮化硅层102b。腐蚀被沟槽腐蚀掩模102暴露的半导体衬底100以形成沟槽103。在沟槽103中和沟槽腐蚀掩模102上淀积沟槽隔离层。进行诸如CMP(化学机械抛光)的平面化处理直到沟槽腐蚀掩模102的上表面,以形成器件隔离层104,即浅槽隔离(以下称为STI)。这里,相邻有源区之间的最小间隔尺寸(‘αF’)比有源区的最小宽度尺寸(‘F’)小。根据本发明沟槽的深度由其上形成有源器件的硅层的厚度确定。另一方面,在体硅中的常规STI技术的情况下,沟槽的深度根据隔离击穿确定。因此,该STI工艺与体硅中的相比有所简化。
参见图6B和7B,在沟槽隔离104和沟槽腐蚀掩模102上淀积层间绝缘层108。腐蚀所选择的层间绝缘层108和沟槽腐蚀掩模102以形成到达半导体衬底100的有源区105的存储节接触孔109。从上述处理步骤可以明白,与常规STI技术不同,没有去掉沟槽腐蚀掩模102,因此可以根本地避免在去掉沟槽腐蚀掩模102的步骤中产生的各种问题。
或者,可以不形成层间绝缘层108,即可以在沟槽腐蚀掩模102中形成接触孔109。由于接触孔109是在形成字线和位线之前形成的,所以可以减少要腐蚀的绝缘层厚度(这里指沟槽腐蚀掩模和层间绝缘层)。接触孔109具有小的高宽比,结果可以减少寄生电阻并且容易制造。典型COB叠置电容器具有大于存储节接触孔的六倍的高宽比。
下面说明电容器118的形成。参见图6C和7C,在所得到的结构上淀积用于存储节的预定厚度的导电材料并构图以形成存储节110。在存储节110上淀积绝缘膜112。在绝缘膜112上淀积用于平板电极114的导电材料。对平板电极层的上表面平面化。
存储节110是由掺杂多晶硅或具有较大逸出功(work function)的金属制成。绝缘膜112由NO层、Ta2O5层、Al2O3层或BST构成。平板电极114由掺杂多晶硅、CVD TiN层、或具有较大逸出功的金属制成。在平面化的上电极114上淀积氧化物层118。
下一道工序是形成SOI(绝缘体上硅)衬底206,并示意性地示于图7D中。SOI衬底206的形成是用键合技术进行的。覆盖有氧化物层118的处理晶片100上下颠倒和覆盖有氧化物层202的支撑晶片200在高真空和高温下(大约650℃-750℃)键合在一起。
在常规CMOS工艺中,阱-阱的隔离要求减少了芯片面积。另一方面,在SOI工艺中,需要较小的面积以隔离阱-阱,并因此减小芯片尺寸。根本地避免了在体硅中遇到的闩锁问题。另外,可以容易形成浅结,并可以获得可靠的软错误免疫特性。
参见图7E,对键合晶片的处理晶片100的裸上表面平面化,直到STI 104的上表面。平面化工艺可以是CMP技术,STI在平面化工艺中起停止层的作用。可以安全调整处理晶片的所要求的厚度。处理晶片的厚度根据STI 104深度确定。
参见图6D和7F,在键合晶片的平面化表面上生长薄层栅氧化物。在栅氧化物层上淀积栅极层并构图成预定形状,即栅极线(字线)。正如现有技术中常规的那样,栅极用栅掩模和栅间隔层覆盖。在形成栅间隔层之前对LDD(轻掺杂漏)进行低浓度离子注入。在形成栅间隔层之后进行高浓度离子注入,由此完全形成LDD源/漏区208,最后形成晶体管210。
由于晶体管210形成在SOI衬底上,所以可以避免结电容或结漏电流的问题。因此,可以减少位线寄生电容,可以增加检测信号裕度和增加数据保存时间。
由于在单元电容器形成之后形成晶体管,所以可以容易地实现高性能晶体管。因为低热堆积(budget)而容易使用低电阻金属字线和位线。另外,晶体管形成在完全平面化的表面上。因此可以采用具有多级金属化的高性能逻辑处理。
可以在源/漏区上和晶体管上表面上形成硅化物层,用于下接触电阻。
形成晶体管210之后,淀积厚度足以覆盖晶体管210的层间绝缘层212。使用光刻法,腐蚀选择的层间绝缘层212以形成到源/漏区的位线接触213,如图6E和7G所示。在接触孔213中和层间绝缘层212上淀积导电材料。然后构图该导电材料,形成位线214,如图6F和7H所示。导电材料可以由钨制成。这里,相邻位线之间的间隔尺寸(‘αF’)比位线宽度(‘F’)和相邻字线之间的间隔尺寸(‘F’)小。
在常规位线工艺中很难在周边区域中同时形成n+接触和p+接触。但是本发明使之成为可能。在常规COB结构中,在形成位线之后形成单元电容器使得在用于电容器成型的热处理过程中n型和p型杂质之间的扩散率有差别。此扩散率的差别导致接触电阻变化。另一方面,象在CUB(位线下面的电容器)的情况一样,位线是在形成电容器之后形成的。因此,可以根本地防止前述问题。本发明使同时形成n+接触和p+接触成为可能,这使制造工艺简单和成本低。本发明具有COB结构和CUB结构的优点。接着,进行金属化处理以形成金属线218,如图4A所示。
上述方法不仅可以适用于具有高密度和高性能的标准DRAM器件,而且适用于包括高性能逻辑处理的埋置式DRAM器件。
从上述解释可以明白,本发明提供SOI存储器件,其能够减少隔离阱-阱所需的面积和减少隔离面积,并由此减少芯片尺寸。根据本发明,晶体管是在形成电容器之后形成的,因此可以抑制晶体管特性的退化。沟槽腐蚀掩模与沟槽隔离一起围绕有源区,使得制造工艺容易并避免了在去掉沟槽腐蚀掩模步骤中遇到的问题。由于在衬底下面的绝缘体中的埋置电容器而可以象COB结构那样获得足够的电容器面积,并且可以象CUB结构那样容易地进行平面化处理。
Claims (8)
1.制造高密度半导体存储器件的方法,所述方法包括以下步骤:
在第一半导体衬底上形成沟槽腐蚀掩模,以在其上确定有源区和无源区,所述沟槽腐蚀掩模是由绝缘体材料制成;
腐蚀所述暴露的第一半导体衬底,并在其中形成沟槽;
用绝缘材料填满所述沟槽,并形成沟槽隔离;
腐蚀所述沟槽腐蚀掩模,直到所述第一半导体衬底的一部分以形成用于到所述第一半导体衬底的电容器下电极的接触孔为止;
用第一导电材料填充所述接触孔,并构图形成电容器下电极,所述电容器下电极与所述第一半导体衬底电连接;
在包括所述电容器下电极的所述第一半导体衬底上连续形成绝缘膜和电容器上电极层,所述电容器上电极具有平坦的上表面;
用设置在其间的键合绝缘层把所述电容器上电极的所述平坦上表面和第二半导体衬底的上表面键合在一起;
对所述键合半导体衬底的所述第一半导体衬底表面进行平面化,直到暴露所述沟槽隔离的上表面为止;
在所述键合半导体衬底的所述第一半导体衬底的所述平面化表面上形成晶体管,所述晶体管具有栅极和结区;
在所述晶体管上形成层间绝缘层以覆盖它;
在所述层间绝缘层中形成到所述结区的位线接触孔;和
用第二导电材料填充所述位线接触孔并构图,形成位线。
2.根据权利要求1所述的方法,其中所述有源区和相邻有源区之间的最小间隔比所述有源区的最小宽度小。
3.根据权利要求1所述的方法,其中所述位线和相邻位线之间的间隔比所述位线的宽度和所述栅极之间的间隔小。
4.根据权利要求1所述的方法,其中所述第一半导体衬底的厚度根据所述沟槽的深度确定。
5.根据权利要求1所述的方法,还包括,在形成用于电容器下电极的所述接触孔的所述步骤之前,在包括所述沟槽的所述第一半导体衬底上形成层间绝缘层的步骤。
6.一种高密度半导体存储器件,包括:
通过用设置在其间的第一绝缘层键合第一半导体衬底和第二半导体衬底形成的SOI衬底,所述第一半导体衬底是处理晶片,所述第二半导体衬底是支撑晶片;
形成在第一半导体衬底中和上的器件隔离层,所述器件隔离层确定有源区和无源区;
形成在所述有源区和所述无源区下面的第二绝缘层,所述第二绝缘层和所述无源区围绕所述有源区;
形成在所述第一半导体衬底的所述有源区上的晶体管,所述晶体管具有栅极和一对结区;
形成在所述第一绝缘层和第一半导体衬底之间的电容器,所述电容器由下电极、绝缘膜和上电极构成,所述电容器通过存储节接触孔与所述晶体管的所述结区之一电连接;和
形成在所述第一半导体衬底上并与另一所述结区电连接的位线,
其特征在于,所述器件隔离层是沟槽隔离,所述第二绝缘层是用于形成所述沟槽隔离的沟槽腐蚀掩模。
7.根据权利要求6所述的高密度半导体存储器件,其特征在于,从所述第一半导体衬底的顶部看,所述有源区和相邻有源区之间的最小间隔比所述有源区的最小宽度小。
8.根据权利要求6所述的高密度半导体存储器件,其特征在于,从所述第一半导体衬底的顶部看,所述位线和相邻位线之间的间隔比所述位线的宽度和所述栅极之间的间隔小。
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1998
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- 1998-08-24 TW TW087113901A patent/TW401626B/zh not_active IP Right Cessation
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- 1999-02-22 US US09/255,293 patent/US6297090B1/en not_active Expired - Lifetime
- 1999-02-25 GB GB9904384A patent/GB2341724B/en not_active Expired - Fee Related
- 1999-02-26 FR FR9902409A patent/FR2782415B1/fr not_active Expired - Fee Related
- 1999-03-18 DE DE19912220A patent/DE19912220B4/de not_active Expired - Fee Related
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100468744C (zh) * | 2006-01-19 | 2009-03-11 | 力晶半导体股份有限公司 | 非挥发性存储器及其制造方法 |
CN101443902B (zh) * | 2006-04-13 | 2011-06-08 | 美光科技公司 | 用于在形成快闪存储器装置期间形成位线触点及位线的方法,及包括所述位线及位线触点的装置 |
Also Published As
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DE19912220B4 (de) | 2005-07-07 |
US6297090B1 (en) | 2001-10-02 |
KR20000013978A (ko) | 2000-03-06 |
DE19912220A1 (de) | 2000-02-24 |
CN1245349A (zh) | 2000-02-23 |
FR2782415A1 (fr) | 2000-02-18 |
KR100268419B1 (ko) | 2000-10-16 |
GB2341724B (en) | 2003-07-16 |
TW401626B (en) | 2000-08-11 |
GB9904384D0 (en) | 1999-04-21 |
GB2341724A (en) | 2000-03-22 |
FR2782415B1 (fr) | 2005-02-11 |
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