CN114823911A - 集成高速续流二极管的沟槽碳化硅mosfet及制备方法 - Google Patents
集成高速续流二极管的沟槽碳化硅mosfet及制备方法 Download PDFInfo
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Abstract
本发明公开了一种集成高速续流二极管的沟槽碳化硅MOSFET及制备方法,属于功率半导体器件技术领域,本发明的MOSFET为沟槽结构,为了解决沟槽底部拐角处的电场集中问题,我们在MOSFET旁边加入了沟槽型的栅控二极管,并且沟槽底部均加入了P型埋层,借此削弱彼此的电场强度。此外,栅控二极管与器件原有的体二极管并联,大幅度降低了体二极管的导通压降,从而降低了反向续流工作模式下的损耗。另外,栅控二极管为单极型器件不存在少子存储效应,可以完全消除体二极管的反向恢复电流,从而降低动态损耗。
Description
技术领域
本发明属于功率半导体器件技术领域,具体涉及集成高速续流二极管的沟槽碳化硅MOSFET及其制备方法。
背景技术
宽禁带半导体材料SiC是制备高压电力电子器件的理想材料,相对于Si材料,SiC材料具有击穿电场强度高(4×106V/cm)、载流子饱和漂移速度高(2×107cm/s)、热导率高、热稳定性好等优点,因此特别适合用于大功率、高压、高温和抗辐射的电子器件中。
SiC VDMOS是SiC功率器件中较为常用的一种器件,相对于双极型的器件,由于SiCVDMOS没有电荷存储效应,所以其拥有更好的频率特性以及更低的开关损耗。同时SiC材料的宽禁带使得SiC VDMOS的工作温度可以高达300℃。
但是平面型SiC VDMOS存在两个问题,其一是JFET区的密度较大,引入了较大的密勒电容,增加了器件的动态损耗;其二是寄生的SiC体二极管导通压降太高,并且其为双极型器件,存在较大的反向恢复电流,此外碳化硅BPD缺陷造成的双极退化现象使得该体二极管的导通压降随着使用时间的增长持续升高,因此,SiC VDMOS的体二极管无法直接作为续流二极管使用。
为了解决这两个问题,本发明提出了所述的集成高速续流二极管的沟槽碳化硅MOSFET。本发明的MOSFET为沟槽结构,沟槽MOSFET的多晶硅底部栅氧化层较厚,并且在本设计中为沟槽底部加入P型掺杂埋层,相对于平面VDMOS可以大幅度降低起密勒电容,降低其开关损耗。为了解决沟槽底部拐角处的电场集中问题,我们在MOSFET旁边加入了沟槽型的栅控二极管,并且沟槽底部均加入了P型埋层,借此削弱彼此的电场强度。此外,栅控二极管与器件原有的体二极管并联,大幅度降低了体二极管的导通压降,从而降低了反向续流工作模式下的损耗。另外,栅控二极管为单极型器件不存在少子存储效应,可以完全消除体二极管的反向恢复电流,从而降低动态损耗。
发明内容
本发明所要解决的技术问题是针对现有技术存在的问题,针对碳化硅功率半导体的高频开关应用需求,提供了集成高速续流二极管的沟槽碳化硅MOSFET及其制备方法。
为解决上述技术问题,本发明技术方案如下:
一种集成高速续流二极管的沟槽碳化硅MOSFET,包括背面欧姆接触合金1,N型掺杂碳化硅衬底2,N型掺杂碳化硅外延层3,第一P型掺杂埋层41,第二P型掺杂埋层42,第三P型掺杂埋层43,第一栅氧化层51,第二栅氧化层52,第一多晶硅61,第二多晶硅62,第一P型掺杂井区71,第二P型掺杂井区72,第三P型掺杂井区73,第一N型掺杂源区81,第二N型掺杂源区82,P型掺杂源区9,层间介质10,正面欧姆接触合金11;
在x轴和y轴构成的平面上,所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方;所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方;所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3的右上方;所述第三P型掺杂埋层43位于所述N型掺杂碳化硅外延层3的左上方;所述第一栅氧化层51位于所述第二P型掺杂埋层42的上方;所述第二栅氧化层52位于所述第三P型掺杂埋层43的上方;所述第一多晶硅61位于所述第一栅氧化层51的右上方;所述第二多晶硅62位于所述第二栅氧化层52的左上方;所述第一N型掺杂源区81位于所述第一栅氧化层51的左上方;所述P型掺杂源区9位于所述第一N型掺杂源区81的左侧;所述第二N型掺杂源区82位于所述P型掺杂源区9的左侧,并且与第二栅氧化层52的右侧相接;所述第一P型掺杂井区71位于所述第一N型掺杂源区81下方,且位于所述第一栅氧化层51的左侧;所述第二P型掺杂井区72位于所述第一N型掺杂源区81、P型掺杂源区9和第二N型掺杂源区82的下方,并且位于所述第一N型掺杂源区71左侧;所述第三P型掺杂井区73位于所述第二N型掺杂源区82下方,并且位于所述第二P型掺杂井区72左侧;所述层间介质10位于所述第一N型掺杂源区81、第一栅氧化层51、第一多晶硅61的上方;所述正面欧姆接触合金11位于所述层间介质10、第一N型掺杂源区81、P型掺杂源区9、第二N型掺杂源区82、第二栅氧化层52、第二多晶硅62的上方;
在y轴和z轴构成的平面上,所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方;所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方;所述第一P型掺杂埋层41位于所述N型掺杂碳化硅外延层3内部右上方;所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3内部左上方;所述第一栅氧化层51位于所述第一P型掺杂埋层41、N型掺杂碳化硅外延层3、第二P型掺杂埋层42上方;所述第一多晶硅61位于所述第一栅氧化层51的上方;所述层间介质10位于所述第一多晶硅61的上方;所述第正面欧姆接触合金11位于所述层间介质10的上方。
作为优选方式,所述N型掺杂碳化硅外延层3的掺杂浓度范围为1E15cm-3 ~1E17cm-3;
作为优选方式,所述第一P型掺杂井区71为Al离子注入时横向散射形成的,其浓度延x轴的负方向逐渐降低,且第一P型掺杂井区71靠近所述第一栅氧化层51处的浓度范围为1E14cm-3 ~ 1E16cm-3。
作为优选方式,所述第三P型掺杂井区73为Al离子注入时横向散射形成的,其浓度延x轴的正方向逐渐降低,且第三P型掺杂井区73靠近所述第二栅氧化层52处的浓度范围为0 ~ 1E15cm-3。
一种所述的集成高速续流二极管的沟槽碳化硅MOSFET的制备方法,其特征在于包括以下步骤:
步骤1:N型碳化硅外延片上淀积氧化层,光刻后形成离子注入的P井离子注入掩膜层101,接着在300K~1000K 的温度下进行Al离子注入,注入形成第二P型掺杂井区72,同时由于碳化硅中进行Al离子注入会横向散射,因此在所述第二P型掺杂井区72的左右两侧将同时形成浓度横向渐变的P型掺杂散射区域,分别为第一P型掺杂井区71和第三P型掺杂井区73,注入完成后去除掩膜层,并且完成表面清洗;
步骤2:淀积氧化层,光刻后形成离子注入的N型源区离子注入掩膜层102,接着在300K~1000K 的温度下进行P离子注入,注入形成第一N型掺杂源区81和第二N型掺杂源区82。注入完成后去除掩膜层,并且完成表面清洗;
步骤3:淀积氧化层,光刻后形成离子注入的P型源区离子注入掩膜层103,接着在300K~1000K 的温度下进行Al离子注入,注入形成P型掺杂源区9,注入完成后去除掩膜层,并且完成表面清洗;
步骤4:淀积氧化层,光刻后形成沟槽刻蚀阻挡层104,接着对N型掺杂碳化硅外延层3进行反应离子刻蚀形成沟槽;
步骤5:在300K~1000K 的高温下进行Al离子注入,在沟槽底部形成第二P型掺杂埋层42和第三P型掺杂埋层43,注入完成后去除沟槽刻蚀阻挡层104;
步骤6:覆盖碳帽,并且在1600℃以上的高温下进行退火,激活注入的杂质,热氧化形成第一栅氧化层51和第二栅氧化层52,接着淀积多晶硅,并刻蚀形成第一多晶硅61和第二多晶硅62;
步骤7:淀积氧化层,光刻形成层间介质10;
步骤8:淀积Ni合金,退火形成金属硅化物,接着正面淀积Al形成源极金属,器件的背面溅射形成Ni合金,退火形成背面欧姆接触合金1。
与现有技术相比,本发明的有益效果是:
本发明采用了沟槽加P型埋层的结构,充分减小了器件的密勒电容,从而降低了器件的开关损耗。此外,P型埋层的加入削弱了沟槽底部及拐角处的电场集中,提高了器件的长期可可靠性;
本发明单片集成了栅控二极管,该栅控二极管为沟槽结构,并且其沟槽和MOSFET的沟槽同时形成不需要额外的工艺步骤。该栅控二极管是一种基于MOSFET二极管接法的整流器,相比于传统MOSFET的体二极管,该整流器具有导通压降低、单极导通(无反向恢复电流、无双击退化)的优点,这是的此整流器可以用作MOSFET的续流二极管,大幅度降低了动态损耗。此外,栅控二极管的加入也削弱了MOSFET沟槽底部及拐角处的电场强度,从而提高了器件的长期可靠性;
本发明利用Al离子注入时的散射效应形成MOSFET和栅控二极管的沟道,采用这种做法可以在保障P型井区电荷总量足够的情况下降低器件的沟道区掺杂浓度。对于MOSFET,我们可以控制沟槽与P型掺杂井区的相对位置来控制沟道区掺杂浓度,从而精确控制其阈值电压。对于栅控二极管,我们可以控制沟槽与P型掺杂井区的相对位置来控制沟道区掺杂浓度,从而调整栅控二极管的导通压降。
在例如半桥或者全桥应用中,碳化硅MOSFET通常需要反向并联碳化硅肖特基二极管进行续流。采用本发明可以避免额外的续流二极管并联。
附图说明
图1 为本发明的集成高速续流二极管的沟槽碳化硅MOSFET结构示意图。
图2 为本发明实施例2步骤1中P型掺杂井区离子注入示意图。
图3 为本发明实施例2步骤2中N型掺杂源区离子注入示意图。
图4 为本发明实施例2步骤3中P型掺杂源区离子注入示意图。
图5 为本发明实施例2步骤4中沟槽刻蚀示意图。
图6 为本发明实施例2步骤5中P型掺杂埋层离子注入示意图。
图7 为本发明实施例2步骤6中栅氧化层形成以及多晶硅填充刻蚀示意图。
图8 为本发明实施例2步骤7中光刻形成层间介质示意图。
图9 为本发明实施例2步骤8中正面欧姆接触合金和背面金属形成示意图。
图10 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET正向导通时的等效电路示意图。
图11 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET反向续流时的等效电路示意图。
1为背面欧姆接触合金,2为N型掺杂碳化硅衬底,3为N型掺杂碳化硅外延层,41为第一P型掺杂埋层,42为第二P型掺杂埋层,43为第三P型掺杂埋层,51为第一栅氧化层,52为第二栅氧化层,61为第一多晶硅,62为第二多晶硅,71为第一P型掺杂井区,72为第二P型掺杂井区,73为第三P型掺杂井区,81为第一N型掺杂源区,82为第二N型掺杂源区,9为P型掺杂源区,10为层间介质,11为正面欧姆接触合金,101为P井离子注入掩膜层,102为N型源区离子注入掩膜层,103为P型源区离子注入掩膜层,104为沟槽刻蚀阻挡层。
具体实施方式
以下结合附图对本发明的原理和特征进行描述,所举实例只用于解释本发明,并非用于限定本发明的范围。
实施例1
如图1所示,本实施例提供一种集成高速续流二极管的沟槽碳化硅MOSFET,包括背面欧姆接触合金1,N型掺杂碳化硅衬底2,N型掺杂碳化硅外延层3,第一P型掺杂埋层41,第二P型掺杂埋层42,第三P型掺杂埋层43,第一栅氧化层51,第二栅氧化层52,第一多晶硅61,第二多晶硅62,第一P型掺杂井区71,第二P型掺杂井区72,第三P型掺杂井区73,第一N型掺杂源区81,第二N型掺杂源区82,P型掺杂源区9,层间介质10,正面欧姆接触合金11;
在x轴和y轴构成的平面上,所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方;所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方;所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3的右上方;所述第三P型掺杂埋层43位于所述N型掺杂碳化硅外延层3的左上方;所述第一栅氧化层51位于所述第二P型掺杂埋层42的上方;所述第二栅氧化层52位于所述第三P型掺杂埋层43的上方;所述第一多晶硅61位于所述第一栅氧化层51的右上方;所述第二多晶硅62位于所述第二栅氧化层52的左上方;所述第一N型掺杂源区81位于所述第一栅氧化层51的左上方;所述P型掺杂源区9位于所述第一N型掺杂源区81的左侧;所述第二N型掺杂源区82位于所述P型掺杂源区9的左侧,并且与第二栅氧化层52的右侧相接;所述第一P型掺杂井区71位于所述第一N型掺杂源区81下方,且位于所述第一栅氧化层51的左侧;所述第二P型掺杂井区72位于所述第一N型掺杂源区81、P型掺杂源区9和第二N型掺杂源区82的下方,并且位于所述第一N型掺杂源区71左侧;所述第三P型掺杂井区73位于所述第二N型掺杂源区82下方,并且位于所述第二P型掺杂井区72左侧;所述层间介质10位于所述第一N型掺杂源区81、第一栅氧化层51、第一多晶硅61的上方;所述正面欧姆接触合金11位于所述层间介质10、第一N型掺杂源区81、P型掺杂源区9、第二N型掺杂源区82、第二栅氧化层52、第二多晶硅62的上方;
在y轴和z轴构成的平面上,所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方;所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方;所述第一P型掺杂埋层41位于所述N型掺杂碳化硅外延层3内部右上方;所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3内部左上方;所述第一栅氧化层51位于所述第一P型掺杂埋层41、N型掺杂碳化硅外延层3、第二P型掺杂埋层42上方;所述第一多晶硅61位于所述第一栅氧化层51的上方;所述层间介质10位于所述第一多晶硅61的上方;所述第正面欧姆接触合金11位于所述层间介质10的上方。
所述N型掺杂碳化硅外延层3的掺杂浓度范围为1E15cm-3 ~ 1E17cm-3;
所述第一P型掺杂井区71为Al离子注入时横向散射形成的,其浓度延x轴的负方向逐渐降低,且第一P型掺杂井区71靠近所述第一栅氧化层51处的浓度范围为1E14cm-3 ~1E16cm-3。
所述第三P型掺杂井区73为Al离子注入时横向散射形成的,其浓度延x轴的正方向逐渐降低,且第三P型掺杂井区73靠近所述第二栅氧化层52处的浓度范围为0 ~ 1E15cm-3。
本发明的集成高速续流二极管的沟槽碳化硅MOSFET,当器件正常工作时右边MOSFET区域的栅极被施加以正向偏置电压,沟道开启,电子在电场的作用下从源极流向漏极,形成自漏极向源极的电流Ids,如图10所示,图10 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET正向导通时的等效电路示意图;当器件关断进入第三象限工作状态时,源极到漏极的正电势差使得二极管区域导通,形成自源极至漏极的电流Isd,如图11所示,图11 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET反向续流时的等效电路示意图。
实施例2
如图2至图9所示,本实施例提供一种集成高速续流二极管的沟槽碳化硅MOSFET的制备方法,包括以下步骤:
步骤1:N型碳化硅外延片上淀积氧化层,光刻后形成离子注入的P井离子注入掩膜层101,接着在300K~1000K 的温度下进行Al离子注入,注入形成第二P型掺杂井区72,同时由于碳化硅中进行Al离子注入会横向散射,因此在所述第二P型掺杂井区72的左右两侧将同时形成浓度横向渐变的P型掺杂散射区域,分别为第一P型掺杂井区71和第三P型掺杂井区73,得到如图2结构。注入完成后去除掩膜层,并且完成表面清洗;
步骤2:淀积氧化层,光刻后形成离子注入的N型源区离子注入掩膜层102,接着在300K~1000K 的温度下进行P离子注入,注入形成第一N型掺杂源区81和第二N型掺杂源区82,得到如图3结构。注入完成后去除掩膜层,并且完成表面清洗;
步骤3:淀积氧化层,光刻后形成离子注入的P型源区离子注入掩膜层103,接着在300K~1000K 的温度下进行Al离子注入,注入形成P型掺杂源区9,得到如图4结构。注入完成后去除掩膜层,并且完成表面清洗;
步骤4:淀积氧化层,光刻后形成沟槽刻蚀阻挡层104,接着对N型掺杂碳化硅外延层3进行反应离子刻蚀形成沟槽;得到如图5结构;
步骤5:在300K~1000K 的高温下进行Al离子注入,在沟槽底部形成第二P型掺杂埋层42和第三P型掺杂埋层43,得到如图6结构。注入完成后去除沟槽刻蚀阻挡层104;
步骤6:覆盖碳帽,并且在1600℃以上的高温下进行退火,激活注入的杂质,热氧化形成第一栅氧化层51和第二栅氧化层52,接着淀积多晶硅,并刻蚀形成第一多晶硅61和第二多晶硅62;得到如图7结构;
步骤7:淀积氧化层,光刻形成层间介质10;得到如图8结构;
步骤8:淀积Ni合金,退火形成金属硅化物,接着正面淀积Al形成源极金属,器件的背面溅射形成Ni合金,退火形成背面欧姆接触合金1。得到如图9结构。
Claims (5)
1.一种集成高速续流二极管的沟槽碳化硅MOSFET,其特征在于:包括背面欧姆接触合金(1),N型掺杂碳化硅衬底(2),N型掺杂碳化硅外延层(3),第一P型掺杂埋层(41),第二P型掺杂埋层(42),第三P型掺杂埋层(43),第一栅氧化层(51),第二栅氧化层(52),第一多晶硅(61),第二多晶硅(62),第一P型掺杂井区(71),第二P型掺杂井区(72),第三P型掺杂井区(73),第一N型掺杂源区(81),第二N型掺杂源区(82),P型掺杂源区(9),层间介质(10),正面欧姆接触合金(11);
在x轴和y轴构成的平面上,所述N型掺杂碳化硅衬底(2)位于所述背面欧姆接触合金(1)的上方;所述N型掺杂碳化硅外延层(3)位于所述N型掺杂碳化硅衬底(2)上方;所述第二P型掺杂埋层(42)位于所述N型掺杂碳化硅外延层(3)的右上方;所述第三P型掺杂埋层(43)位于所述N型掺杂碳化硅外延层(3)的左上方;所述第一栅氧化层(51)位于所述第二P型掺杂埋层(42)的上方;所述第二栅氧化层(52)位于所述第三P型掺杂埋层(43)的上方;所述第一多晶硅(61)位于所述第一栅氧化层(51)的右上方;所述第二多晶硅(62)位于所述第二栅氧化层(52)的左上方;所述第一N型掺杂源区(81)位于所述第一栅氧化层(51)的左上方;所述P型掺杂源区(9)位于所述第一N型掺杂源区(81)的左侧;所述第二N型掺杂源区(82)位于所述P型掺杂源区(9)的左侧,并且与第二栅氧化层(52)的右侧相接;所述第一P型掺杂井区(71)位于所述第一N型掺杂源区(81)下方,且位于所述第一栅氧化层(51)的左侧;所述第二P型掺杂井区(72)位于所述第一N型掺杂源区(81)、P型掺杂源区(9)和第二N型掺杂源区(82)的下方,并且位于所述第一N型掺杂源区(71)左侧;所述第三P型掺杂井区(73)位于所述第二N型掺杂源区(82)下方,并且位于所述第二P型掺杂井区(72)左侧;所述层间介质(10)位于所述第一N型掺杂源区(81)、第一栅氧化层(51)、第一多晶硅(61)的上方;正面欧姆接触合金(11)位于所述层间介质(10)、第一N型掺杂源区(81)、P型掺杂源区(9)、第二N型掺杂源区(82)、第二栅氧化层(52)、第二多晶硅(62)的上方;
在y轴和z轴构成的平面上,所述N型掺杂碳化硅衬底(2)位于所述背面欧姆接触合金(1)的上方;所述N型掺杂碳化硅外延层(3)位于所述N型掺杂碳化硅衬底(2)上方;所述第一P型掺杂埋层(41)位于所述N型掺杂碳化硅外延层(3)内部右上方;所述第二P型掺杂埋层(42)位于所述N型掺杂碳化硅外延层(3)内部左上方;所述第一栅氧化层(51)位于所述第一P型掺杂埋层(41)、N型掺杂碳化硅外延层(3)、第二P型掺杂埋层(42)上方;所述第一多晶硅(61)位于所述第一栅氧化层(51)的上方;所述层间介质(10)位于所述第一多晶硅(61)的上方;正面欧姆接触合金(11)位于所述层间介质(10)的上方。
2.根据权利要求1所述的集成高速续流二极管的沟槽碳化硅MOSFET,其特征在于:所述N型掺杂碳化硅外延层(3)的掺杂浓度范围为1E15cm-3 ~ 1E17cm-3。
3.根据权利要求1所述的集成高速续流二极管的沟槽碳化硅MOSFET,其特征在于:所述第一P型掺杂井区(71)为Al离子注入时横向散射形成的,其浓度延x轴的负方向逐渐降低,且第一P型掺杂井区(71)靠近所述第一栅氧化层(51)处的浓度范围为1E14cm-3 ~ 1E16cm-3。
4.根据权利要求1所述的集成高速续流二极管的沟槽碳化硅MOSFET,其特征在于:所述第三P型掺杂井区(73)为Al离子注入时横向散射形成的,其浓度延x轴的正方向逐渐降低,且第三P型掺杂井区(73)靠近所述第二栅氧化层(52)处的浓度范围为0 ~ 1E15cm-3。
5.一种权利要求1至4任意一项所述的集成高速续流二极管的沟槽碳化硅MOSFET的制备方法,其特征在于包括以下步骤:
步骤1:N型碳化硅外延片上淀积氧化层,光刻后形成离子注入的P井离子注入掩膜层(101),接着在300K~1000K 的温度下进行Al离子注入,注入形成第二P型掺杂井区(72),同时由于碳化硅中进行Al离子注入会横向散射,因此在所述第二P型掺杂井区(72)的左右两侧将同时形成浓度横向渐变的P型掺杂散射区域,分别为第一P型掺杂井区(71)和第三P型掺杂井区(73),注入完成后去除掩膜层,并且完成表面清洗;
步骤2:淀积氧化层,光刻后形成离子注入的N型源区离子注入掩膜层(102),接着在300K~1000K 的温度下进行P离子注入,注入形成第一N型掺杂源区(81)和第二N型掺杂源区(82),注入完成后去除掩膜层,并且完成表面清洗;
步骤3:淀积氧化层,光刻后形成离子注入的P型源区离子注入掩膜层(103),接着在300K~1000K 的温度下进行Al离子注入,注入形成P型掺杂源区(9),注入完成后去除掩膜层,并且完成表面清洗;
步骤4:淀积氧化层,光刻后形成沟槽刻蚀阻挡层(104),接着对N型掺杂碳化硅外延层(3)进行反应离子刻蚀形成沟槽;
步骤5:在300K~1000K 的高温下进行Al离子注入,在沟槽底部形成第二P型掺杂埋层(42)和第三P型掺杂埋层(43),注入完成后去除沟槽刻蚀阻挡层(104);
步骤6:覆盖碳帽,并且在1600℃以上的高温下进行退火,激活注入的杂质,热氧化形成第一栅氧化层(51)和第二栅氧化层(52),接着淀积多晶硅,并刻蚀形成第一多晶硅(61)和第二多晶硅(62);
步骤7:淀积氧化层,光刻形成层间介质(10);
步骤8:淀积Ni合金,退火形成金属硅化物,接着正面淀积Al形成源极金属,器件的背面溅射形成Ni合金,退火形成背面欧姆接触合金(1)。
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