WO2023184812A1 - 基于异质结的高功率密度隧穿半导体器件及其制造工艺 - Google Patents

基于异质结的高功率密度隧穿半导体器件及其制造工艺 Download PDF

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WO2023184812A1
WO2023184812A1 PCT/CN2022/110104 CN2022110104W WO2023184812A1 WO 2023184812 A1 WO2023184812 A1 WO 2023184812A1 CN 2022110104 W CN2022110104 W CN 2022110104W WO 2023184812 A1 WO2023184812 A1 WO 2023184812A1
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region
drift region
type
heterojunction
graphene
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French (fr)
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魏家行
付浩
王恒德
隗兆祥
刘斯扬
孙伟锋
时龙兴
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东南大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the invention mainly relates to the field of high-voltage power semiconductor devices. Specifically, it is a high-power density tunneling semiconductor device based on heterojunction and its manufacturing process. It is suitable for automotive electronics, rail transit, photovoltaic inverter, aerospace, aviation, Application fields such as oil exploration, nuclear energy, radar and communications where high temperature, high frequency, high power, strong radiation and other extreme environments coexist.
  • Power semiconductor devices play a pivotal role in the power electronics industry and are widely used in automobiles, home appliances, high-speed rail and power grids.
  • traditional power devices have many shortcomings, such as large cell size, large on-resistance, high density of interface states, complex manufacturing processes, and doping processes that can cause damage to the semiconductor surface.
  • the conduction band and valence band of graphene material are symmetrical and only intersect at the vertex of the Brillouin zone, that is, at a point on the Fermi surface. It has an obvious controllable electronic band gap. According to the symmetry of the energy band of graphene material, doping or applying an external field can destroy the energy band symmetry, thereby opening the band gap and controlling the size of the band gap.
  • Graphene material has the characteristics of semiconductor energy bands and high conductivity characteristics of metals. Graphene materials have the characteristics of high mobility, high thermal conductivity, strong high temperature stability, and can be produced in large areas, which meet the needs of power semiconductor devices.
  • Figure 1 shows a conventional silicon carbide power semiconductor device, including: N+ type substrate 1.
  • a drain metal 10 is connected to one side of the N+ type substrate 1, and a drain metal 10 is connected to the other side of the N+ type substrate 1.
  • N-type drift region 2, a pair of P-type base regions 3, N+-type source region 5 and P+-type body contact region 4 are symmetrically arranged in the N-type drift region 2, and a gate is provided on the surface of the N-type drift region 2
  • a polysilicon gate 9 is provided on the surface of the gate oxide layer 8
  • a passivation layer 6 is provided above the polysilicon gate 9, and a source metal 7 is connected to the N+ type source region 5 and the P+ type body contact region 4.
  • the working principle of conventional silicon carbide power semiconductor devices is that when a large enough positive voltage is applied to the polysilicon gate, an inversion channel will be generated at the interface between the P-type base region 3 and the gate oxide layer 8, through which electrons can pass from N+ Type source region 5 is implanted into N-type drift region 2 .
  • the P-type base region 3 and the N+-type source region 5 need to be formed by doping.
  • the cell size of the silicon carbide device is limited by the doping process and the width of the JFET region, resulting in a cell width limit of 4-6um, which cannot be further reduced, thus Affects the cell density of the device and the forward current capability of the device.
  • the ion implantation process of silicon carbide material will also cause surface damage to the N-type drift region 2, resulting in a large number of interface state traps on the surface of the N-type drift region 2, resulting in a smaller effective mobility of inversion channel carriers, resulting in Pass resistance is higher.
  • traditional semiconductor devices are based on the working mechanism of carrier hot injection, and the sub-threshold swing can only reach a minimum of 60mV/decade at room temperature. Therefore, there is an urgent need to propose a new type of power device with high channel electron mobility and high power density.
  • the present invention proposes a high power density tunneling semiconductor device based on heterojunction and its manufacturing process.
  • This structure uses graphene and silicon carbide substrates to form a heterogeneous structure while maintaining the same breakdown voltage. Quality knot.
  • the Fermi level of graphene moves up into the conduction band, and the electron concentration in the N-type drift region increases to form an accumulation layer.
  • the width of the heterojunction barrier becomes narrower, and band tunneling occurs.
  • electrons in the valence band of graphene tunnel through the heterojunction barrier into the conduction band of the N-type drift region.
  • the cell size of the device of the present invention is smaller than that of conventional silicon carbide power device cells, which greatly increases the number of cells per unit area, effectively reduces the specific on-resistance of the device, increases the power density of the device, and at the same time reduces It reduces the sub-threshold swing of the device, greatly simplifies the manufacturing process, and reduces the device cost.
  • the present invention adopts the following technical solution: a high power density tunneling semiconductor device based on heterojunction and a manufacturing process thereof.
  • the high power density tunneling power semiconductor device based on heterojunction has an axially symmetric structure,
  • N-drift region It includes an N+ substrate, a drain metal is provided below it, and an N-drift region is provided above it; it is characterized in that a pair of graphene source regions are arranged at intervals above the N-drift region, and a source is provided on the graphene source region.
  • the N-drift region is provided with a gate dielectric layer that partially overlaps the graphene source region.
  • the gate dielectric layer is provided with a polysilicon gate.
  • the polysilicon gate is provided with a passivation layer.
  • the polysilicon gate and the gate dielectric layer are flush.
  • the polysilicon gate and the source metal are spaced apart.
  • a heterojunction is formed at the contact between the graphene source region and the N-drift region.
  • a triple contact surface is formed between the graphene source region, the N-type region drift region and the gate dielectric layer. Tunneling occurs at the contact surface.
  • the graphene source region is arranged in the groove, and the P+ type region is provided in the N-type drift region below the graphene source region.
  • the graphene source region is disposed on the upper surface of the N-type drift region, and the P+ type region is disposed in the N-type drift region below the graphene source region.
  • the graphene source region is disposed on the upper surface of the N-type drift region.
  • a P+ type region is provided in the N-type drift region below the graphene source region, and a second P+ type region is provided in the N-type drift region below the gate dielectric layer.
  • the second P+ type region is connected to the graphene source region. There is a certain distance between areas.
  • the N+ type substrate and N- type drift region are not limited by materials. Silicon carbide, gallium oxide, silicon, diamond or other materials that can form the heterojunction tunneling power semiconductor device substrate and drift region can be used. , the doping concentration of the N+ type substrate and N- type drift region is also not limited.
  • the graphene source region is not limited by material, and graphene, molybdenum disulfide, polysilicon, metal or other materials that can form the source region of a heterojunction tunneling power semiconductor device can be used.
  • the thickness of the gate dielectric layer is not limited, and the gate dielectric layer is not limited by material. Silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or other gate dielectrics that can form heterojunction tunneling power semiconductor devices can be used. layer material.
  • a method for manufacturing a high-power-density tunneling semiconductor device based on heterojunction including the following steps:
  • Step 1 Attach silicon carbide to the surface of the N+ type substrate to form an N-type drift region
  • Step 2 Use an etching process to form a trench on the surface of the N-type drift region
  • Step 3 Use a doping process to form a P+ type shielding layer at the bottom of the trench;
  • Step 4 Form a layer of graphene source region on the bottom of the trench
  • Step 5 Use a deposition process to form a gate dielectric layer on the upper surface of the N-type drift region
  • Step 6 Use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer and form a polysilicon gate;
  • Step 7 Use a deposition process to form an isolation passivation layer above the polysilicon gate
  • Step 8 Finally, form the source metal on the upper surface of the graphene source region, and make the drain metal on the other surface of the N+ type substrate.
  • the source of the device of the present invention is made of graphene material, and voltage is applied through the gate to obtain lower sub-threshold swing and higher on-state current characteristics.
  • the gate When a negative voltage is applied to the gate, electrons in the channel region are repelled and the electron concentration is reduced, which increases the energy band of the N-drift region below the gate. Moreover, the gap between the conduction band and the valence band of graphene is opened, and the heterojunction barrier width becomes larger, which greatly suppresses the occurrence of tunneling effect and bipolar effect, making the power semiconductor device have smaller leakage current in the off state. .
  • the device is in the reverse withstand voltage state, and the homogeneous PN junction formed by the P+ type region and the N-type drift region is in the reverse withstand voltage state as shown in Figure 4, in which the depletion layer distribution is shown as the dotted line 10.
  • the present invention has the following advantages:
  • the source of the device of the present invention uses graphene material.
  • the conduction band and valence band of the graphene material are symmetrical and only intersect at the vertex of the Brillouin zone, that is, at a point on the Fermi surface. It has obvious controllable electrons. Bandgap. According to the symmetry of the energy band of graphene, doping or applying an external electric field can destroy the symmetry of the energy band, thereby opening the band gap, and the work function of graphene is adjustable. Therefore, graphene has semiconductor energy band characteristics. When zero voltage is applied to the gate, the device is in a closed state, and the intrinsic carrier concentration of graphene is low and presents a high resistance state.
  • the graphene material used in the source electrode of the device of the present invention has a low doping concentration and is almost in an intrinsic state.
  • the intrinsic carrier concentration of graphene is low, it presents a high resistance state and the leakage current is small when the reverse withstand voltage is applied.
  • the thermal conductivity of the graphene material used in the source of the device of the present invention is six times that of silicon carbide and the thickness is extremely thin. Therefore, compared with traditional power devices, the device of the present invention has better heat dissipation characteristics.
  • the device of the present invention uses the heterojunction formed by the graphene material and the N-drift region to replace the PN homojunction formed by the ion implantation doping process of conventional silicon carbide power semiconductor devices.
  • the heterojunction barrier is lower and the freewheeling current is larger.
  • the work function of graphene can be changed by doping and other means to obtain a heterojunction diode with an adjustable heterojunction barrier, which further maximizes the ability of the device of the present invention in the freewheeling state.
  • the source of the device of the present invention uses graphene material.
  • the graphene material and the N-drift region form a heterojunction. Under the control of the gate voltage, the tunneling effect occurs.
  • the channel is the graphene source and N-type drift. area contact and the triple contact of the gate insulating layer.
  • the P-type base region and N+-type source can only be formed through an ion implantation and doping process, and then the inversion layer conductive channel is formed through gate control. However, the ion implantation doping process will damage the surface of the N-type drift region, resulting in low electron mobility.
  • the channel of the device of the present invention is formed by graphene and a high-concentration electron accumulation region. It does not require an ion implantation process to form the electron inversion layer conductive channel, and does not cause damage to the channel area. It causes damage to the surface of the N-drift region, greatly simplifies the manufacturing process, reduces device costs, and greatly increases the number of cells per unit area.
  • the graphene source region, the N-type region drift region and the gate dielectric layer are in contact to form a triple contact surface.
  • the tunneling effect occurs at the triple contact surface, resulting in high channel density and strong current capability.
  • the device of the present invention is compatible with traditional device processes, and graphene can be produced in a large area with low process difficulty.
  • the device of the present invention is provided with a P+ type region below the graphene source region.
  • the P+ type region and the N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction.
  • the electric field peak when there is no P+ type region is at the heterojunction boundary formed by the graphene source region and the N-type drift region.
  • the reverse leakage current is large and the device breakdown voltage is small.
  • the electric field peak is at the PN junction boundary formed by the P+ type region and the N-type drift region, which improves the avalanche capability of the device, reduces the reverse bias leakage current, and increases the device breakdown voltage.
  • Figure 1 is a front view of the structure of a conventional silicon carbide power semiconductor device
  • FIG. 2 is a front view of a semiconductor device cell according to the first embodiment of the present invention.
  • Figure 3 is a schematic diagram of a forward current path according to the first embodiment of the present invention.
  • Figure 4 is a schematic diagram of the reverse state depletion layer distribution according to the first embodiment of the present invention.
  • Figure 5 is a front view of a semiconductor device cell according to a second embodiment of the present invention.
  • FIG. 6 is a front view of a semiconductor device cell according to a third embodiment of the present invention.
  • FIG. 7 is a front view of a semiconductor device cell according to a fourth embodiment of the present invention.
  • FIG 8 is a front view of a semiconductor device cell according to a fifth embodiment of the present invention.
  • the high power density tunneling power semiconductor device based on heterojunction has an axially symmetric structure and includes: N+ type substrate 1, in N+ type A drain metal 8 is connected to the lower surface of the substrate 1.
  • An N-type drift region 2 is provided on the upper surface of the N+-type substrate 1.
  • a pair of P+-type regions 9 are provided in the N-type drift region 2.
  • a pair of graphene source regions 3 are provided on the upper surface of the drift region 2.
  • a source metal 4 is symmetrically provided on the upper surface of the graphene source region 3.
  • a gate dielectric layer 5 is provided on the upper surfaces of the N-type drift region 2 and the graphene source region 3.
  • a polysilicon gate 6 is provided on the upper surface of the gate dielectric layer 5 , and a passivation layer 7 is provided on the upper surface of the polysilicon gate 6 .
  • a groove is carved on the upper surface of the N-type drift region 2 so that the N-type drift region 2 is divided into two parts, the N-type drift region 2.1 and the N-type drift region 2.2. The bottom of the groove is the upper surface of the N-type drift region 2.1.
  • a pair of P+ type regions 9 are provided, and a pair of graphene source regions 3 are symmetrically arranged in the groove on the upper surface of the N-type drift region 2.
  • the present invention adopts the following method to prepare:
  • Step 1 Take an N+ type substrate 1 and attach silicon carbide to one surface of the N+ type substrate 1 to form an N- type drift region 2;
  • Step 2 Use an etching process to form a trench on the surface of the N-type drift region 2;
  • Step 3 Use a doping process to form a P+ type shielding layer 9 at the bottom of the trench;
  • Step 4 Form a layer of graphene source region 3 on the bottom of the trench;
  • Step 5 Use a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;
  • Step 6 Use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;
  • Step 7 Use a deposition process to form an isolation passivation layer 7 above the polysilicon gate 6; finally, form a source metal 4 on the upper surface of the graphene source region 3, and make a drain metal 8 on the other surface of the N+ type substrate 1 .
  • the P+ type region and the N-type drift region form a PN junction
  • the graphene source region and the N-type drift region form a heterojunction.
  • the area of the heterojunction is increased through the groove process.
  • the electrons in the graphene valence band tunnel through the heterojunction barrier and enter the conduction band of the N-type drift region. Create an electric current.
  • the current path 11 is shown in Figure 3.
  • the depletion layer 10 is under the graphene and does not affect the current path 11.
  • the electric field peak when there is no P+ type region is located at the heterojunction boundary formed by the graphene source region and the N-type drift region.
  • the reverse leakage current is large and the device breakdown voltage is small.
  • the depletion layer 10 when there is a P+ type region, the depletion layer 10 completely covers the graphene source region 3, shielding the electric field at the heterojunction interface, and the electric field peak is transferred to the PN formed by the P+ type region and the N-type drift region.
  • the reverse bias leakage current is reduced, the avalanche capability of the device is improved, and the breakdown voltage of the device is increased.
  • the cell size of the device of the present invention is not limited by the doping process and the JFET area, so the cell size of the device of the present invention is much smaller than that of conventional silicon carbide power devices.
  • the high power density tunneling power semiconductor device based on heterojunction has an axially symmetric structure and includes: N+ type substrate 1, in N+ type A drain metal 8 is connected to the lower surface of the substrate 1, an N-type drift region 2 is provided on the upper surface of the N+ type substrate 1, and a pair of P+ type regions 9 are provided in the upper surface of the N-type drift region 2.
  • a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2.
  • a source metal 4 is symmetrically arranged on the upper surface of the graphene source region 3.
  • the upper surfaces of the N-type drift region 2 and the graphene source region 3 are symmetrically arranged.
  • a gate dielectric layer 5 There is a gate dielectric layer 5, a polysilicon gate 6 is disposed on the upper surface of the gate dielectric layer 5, and a passivation layer 7 is disposed above the polysilicon gate 6.
  • a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2.
  • the N-type drift region 2 is provided with a gate dielectric 5 that partially overlaps the graphene source region 3.
  • the polysilicon gate 6 is flush with the gate dielectric layer 5.
  • the graphene A heterojunction is formed at the contact surface between the source region 3 and the N-type drift region 2 .
  • the present invention adopts the following method to prepare:
  • Step 1 Take an N+ type substrate 1 and attach silicon carbide to the other surface of the N+ type substrate 1 to form an N- type drift region 2;
  • Step 2 Use a doping process to form a P+ type shielding layer 9 in the N-type drift region 2;
  • Step 3 Form a layer of graphene source region 3 on the N-type drift region 2;
  • Step 4 Use a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;
  • Step 5 Use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;
  • Step 6 Use a deposition process to form an isolation passivation layer 7 above the polysilicon gate 6; finally, form a source metal 4 on the upper surface of the graphene source region 3, and make a drain metal 8 on the other surface of the N+ type substrate 1 .
  • This structure uses graphene and silicon carbide substrates to form a heterojunction while keeping the breakdown voltage constant.
  • a positive voltage is applied to the gate, the Fermi level of graphene moves upward and enters the conduction band, while N- The electron concentration in the type drift region increases to form an accumulation layer.
  • the heterojunction barrier width narrows, and a tunneling effect occurs at the triple contact point of the graphene source region, the N-type region drift region and the gate dielectric layer.
  • the graphene The electrons in the valence band tunnel through the heterojunction barrier into the conduction band of the N-type drift region.
  • the P+ type region and the N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction.
  • the electric field peak without the P+ type region is located between the graphene source region and the N-type drift region.
  • the reverse leakage current is large and the device breakdown voltage is small.
  • the electric field peak is transferred to the PN junction boundary formed by the P+ type region and the N-type drift region, which improves the avalanche capability of the device, reduces the reverse bias leakage current, and increases the device breakdown voltage. .
  • the cell size of the device of the present invention is smaller than that of conventional silicon carbide power device cells, which greatly increases the number of cells per unit area, effectively reduces the specific on-resistance of the device, increases the power density of the device, and simultaneously reduces The device has sub-threshold swing, greatly simplifies the manufacturing process, and reduces device cost.
  • the high power density tunneling power semiconductor device based on heterojunction has an axially symmetric structure and includes: N+ type substrate 1, in N+ type A drain metal 8 is connected to the lower surface of the substrate 1.
  • An N-type drift region 2 is provided on the upper surface of the N+ type substrate 1.
  • a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2.
  • a source metal 4 is symmetrically arranged on the upper surface of the graphene source region 3
  • a gate dielectric layer 5 is provided on the upper surface of the N-type drift region 2 and the graphene source region 3
  • a polysilicon gate 6 is disposed on the upper surface of the gate dielectric layer 5, and the polysilicon
  • a passivation layer 7 is provided above the gate 6 .
  • a pair of graphene source regions 3 are symmetrically arranged on the surface of the N-type drift region 2. There is a certain distance between the pair of graphene source regions 3.
  • the N-type drift region 2 is provided with a pair of graphene source regions 3 that partially overlaps with the graphene source region 3.
  • the gate dielectric layer 5, the polysilicon gate 6 and the gate dielectric layer 5 are flush, there is a certain distance between the polysilicon gate 6 and the source metal 4, and an anomaly is formed at the contact surface between the graphene source region 3 and part of the N-type drift region 2 Quality knot.
  • the present invention adopts the following method to prepare:
  • Step 1 Take an N+ type substrate 1 and attach silicon carbide to the other surface of the N+ type substrate 1 to form an N- type drift region 2;
  • Step 2 Form a layer of graphene source region 3 on the N-type drift region 2;
  • Step 3 Use a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;
  • Step 4 Use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;
  • Step 5 Use a deposition process to form an isolation passivation layer 7 above the polysilicon gate 6; finally, form a source metal 4 on the upper surface of the graphene source region 3, and make a drain metal 8 on the other surface of the N+ type substrate 1 .
  • Graphene and silicon carbide substrates are used to form a heterojunction.
  • the Fermi level of graphene moves upward and enters the conduction band.
  • the electron concentration in the N-type drift region increases to form an accumulation layer.
  • the width of the heterojunction barrier becomes narrower, and the band tunneling effect occurs at the triple contact point of the graphene source region, the N-type region drift region and the gate dielectric layer.
  • the electrons in the graphene valence band tunnel through the heterojunction potential.
  • the barrier enters the conduction band of the N-type drift region.
  • the cell size of the device is not limited by the doping process and the JFET region. Therefore, the cell size of the device of the present invention is larger than that of conventional silicon carbide power devices.
  • the cells are small, which greatly increases the cell density of the device, effectively reduces the specific on-resistance of the device, increases the power density of the device, and reduces the sub-threshold swing of the device. It also greatly simplifies the manufacturing process and reduces the cost of the device. cost.
  • the high power density tunneling power semiconductor device based on heterojunction has an axially symmetric structure and includes: N+ type substrate 1, in N+ type A drain metal 8 is connected to the lower surface of the substrate 1. An N-type drift region 2 is provided on the upper surface of the N+ type substrate 1. A pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2.
  • a source metal 4 is symmetrically arranged on the upper surface of the graphene source region 3
  • a gate dielectric layer 5 is provided on the upper surface of the N-type drift region 2 and the graphene source region 3
  • a polysilicon gate 6 is disposed on the upper surface of the gate dielectric layer 5, and the polysilicon
  • a passivation layer 7 is provided above the gate 6 .
  • a groove is carved on the upper surface of the N-type drift region 2.
  • a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2. There is a certain distance between the pair of graphene source regions 3.
  • the N-type drift region 2 is provided with a gate dielectric layer 5 that partially overlaps the graphene source region 3.
  • the polysilicon gate 6 is flush with the gate dielectric layer 5. There is a certain distance between the polysilicon gate 6 and the source metal 4.
  • the graphene source region 3 is A heterojunction in the power device is formed at the contact surface of part of the N-type drift region 2 .
  • the present invention adopts the following method to prepare:
  • Step 1 Take an N+ type substrate 1 and attach silicon carbide to the other surface of the N+ type substrate 1 to form an N- type drift region 2;
  • Step 2 Use an etching process to form a trench on the surface of the N-type drift region 2;
  • Step 3 Form a layer of graphene source region 3 on the bottom of the trench;
  • Step 4 Use a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;
  • Step 5 Use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;
  • Step 6 Use a deposition process to form an isolation passivation layer 7 above the polysilicon gate 6; finally, form a source metal 4 on the upper surface of the graphene source region 3, and make a drain metal 8 on the other surface of the N+ type substrate 1 .
  • a heterojunction is formed using graphene and silicon carbide substrates, and the area of the heterojunction is increased through a groove process.
  • the Fermi level of graphene shifts and enters the conduction band.
  • N- The electron concentration in the type drift region increases to form an accumulation layer.
  • the heterojunction barrier width becomes narrower, and the band tunneling effect occurs at the triple contact surface of the graphene source region, the N-type region drift region and the gate dielectric layer.
  • the electrons in the valence band of graphene tunnel through the heterojunction barrier into the conduction band of the N-type drift region.
  • This structure has a larger area where the band tunneling effect occurs and a higher current density.
  • the cell size of the device is not limited by the doping process and the JFET region. Therefore, the cell size of the device of the present invention is larger than that of conventional silicon carbide power devices.
  • the cells are small, which greatly increases the cell density of the device, effectively reduces the specific on-resistance of the device, increases the power density of the device, and reduces the sub-threshold swing of the device. It also greatly simplifies the manufacturing process and reduces the cost of the device. cost.
  • the high power density tunneling power semiconductor device based on heterojunction has an axially symmetric structure and includes: N+ type substrate 1 , a drain metal 8 is connected to the lower surface of the N+ type silicon carbide substrate 1, an N-type drift region 2 is provided on the upper surface of the N+ type substrate 1, and an N-type drift region 2 is symmetrically provided on the upper surface of the N-type drift region 2.
  • the source metal 4 is symmetrically arranged on the upper surface of the graphene source region 3.
  • a gate dielectric layer 5 is disposed on the upper surface of the N-type drift region 2 and the graphene source region 3.
  • a polysilicon gate 6 is disposed on the upper surface of the gate dielectric layer 5.
  • a passivation layer 7 is disposed above the polysilicon gate 6.
  • In the N-type drift region 2 is provided with a pair of P+ type regions 9, and a P+ type region 10 is provided in the N-type drift region 2 below the gate dielectric layer 5.
  • a groove is carved on the upper surface of the N-type drift region 2, and a pair of P+ type regions 9 are provided at the bottom of the groove.
  • a pair of graphene source regions 3 and a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2. There is a certain distance between them.
  • the N-type drift region 2 is provided with a gate dielectric layer 5 that partially overlaps the graphene source region 3.
  • the polysilicon gate 6 is flush with the gate dielectric layer 5.
  • the polysilicon gate 6 is flush with the source metal 4. There is a certain distance between them.
  • a heterojunction is formed at the contact surface between the graphene source region 3 and the N-type drift region 2.
  • the graphene source region 3, the N-type drift region 2 and the gate dielectric layer 5 are in contact, forming a Triple contact point, which is surrounded by the depletion layer of P+ type region 10 and N- drift region 2.
  • the distance is larger than the width of the depletion layer of the P+ type region 9 and the N- drift region 2 when a positive voltage is applied to the polysilicon gate 6. At this time, the depletion layer does not cover the triple contact surface. Contact point.
  • the present invention adopts the following method to prepare:
  • Step 1 Take an N+ type substrate 1 and attach silicon carbide to the other surface of the N+ type substrate 1 to form an N- type drift region 2;
  • Step 2 Use an etching process to form a trench on the surface of the N-type drift region 2;
  • Step 3 Use a doping process to form a P+ type shielding layer 9 at the bottom of the trench, and dope the upper surface of the N-type drift region 2 with Group III elements to form a P+ type shielding layer 10;
  • Step 4 Form a layer of graphene source region 3 on the bottom of the trench;
  • Step 5 Use a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;
  • Step 6 Use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;
  • Step 7 Use a deposition process to form an isolation passivation layer 7 above the polysilicon gate 6; finally, form a source metal 4 on the upper surface of the graphene source region 3, and make a drain metal 8 on the other surface of the N+ type substrate 1 .
  • Graphene and silicon carbide substrates are used to form a heterojunction, and a positive voltage is applied through the gate to move the Fermi level of graphene upward into the conduction band.
  • the electron concentration in the N-type drift region increases to form an accumulation layer.
  • the electron accumulation region narrows the depletion layer between the P+ type region and the N-drift region below the gate dielectric layer, and no longer covers the triple contact point.
  • sufficient positive pressure is applied to the gate, and the band tunneling effect occurs at the triple contact surface of the graphene source region, the N-type region drift region and the gate dielectric layer. The electrons in the graphene valence band tunnel through the heterojunction potential.
  • the barrier enters the conduction band of the N-type drift region.
  • the depletion layer between the P+ type region and the N- drift region under the gate dielectric layer covers the triple contact point.
  • the P+ region 9 shifts the electric field peak from the heterojunction boundary to the PN junction boundary, improving the avalanche capability of the device, reducing the reverse bias leakage current, and increasing the breakdown voltage.
  • the P+ type region 10 The electric field of the gate dielectric layer 5 is shielded and the reliability of the gate oxide of the device is improved.
  • This structure improves the gate oxide reliability of the device, reduces the gate-drain capacitance, and improves the switching characteristics without sacrificing the forward conductivity capability of the high-power-density tunneling power semiconductor device based on heterojunction.

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Abstract

本发明公开一种基于异质结的高功率密度隧穿半导体器件及其制造工艺，器件元胞结构包括：N+衬底，其下设有漏极金属，其上设有N-漂移区；在N-漂移区内对称设有一对沟槽，槽底设有P+区，在槽内设有石墨烯源区，石墨烯源区上设有源极金属，N-漂移区上设有与石墨烯源区部分交叠的栅介质层，栅介质层上设有多晶硅栅，多晶硅栅上设有钝化层，石墨烯源区与N-漂移区形成异质结。本发明器件结构对注入工艺要求低，元胞尺寸小，单位面积元胞数量多，大幅提升了器件的功率密度，有效降低器件的比导通电阻、亚阈值摆幅，简化了制造工艺，降低了器件成本。器件反偏耐压时，P+区使电场峰值从异质结边界处转移到PN结边界处，提高了器件雪崩能力，增大了击穿电压。

Description

基于异质结的高功率密度隧穿半导体器件及其制造工艺 技术领域
本发明主要涉及高压功率半导体器件领域，具体来说，是一种基于异质结的高功率密度隧穿半导体器件及其制造工艺，适用于汽车电子、轨道交通、光伏逆变、航天、航空、石油勘探、核能、雷达与通信等高温、高频、大功率、强辐射等极端环境并存的应用领域。
背景技术
功率半导体器件在电力电子行业中起着举足轻重的作用，在汽车、家用电器、高铁和电网中有着广泛的应用。然而传统的功率器件有着很多缺点，如：元胞尺寸大、导通电阻大、界面态密度高、制造工艺复杂和掺杂工艺会对半导体表面产生损伤等缺点。
石墨烯材料的导带、价带对称，并且只在布里渊区的顶点处相交即相交于费米面上的一点，具有明显的可控电子带隙。根据石墨烯材料能带对称的特点，掺杂或施加外场都可以破坏能带对称性，进而打开带隙并且可以控制带隙的大小。石墨烯材料具有半导体能带的特征同时具有金属高电导率特性。石墨烯材料的迁移率高、热导率高、高温稳定性强、可以大面积制作等特点符合功率半导体器件的需求。
图1所示的是常规的碳化硅功率半导体器件，包括：N+型衬底1，在N+型衬底1的一侧连接有漏极金属10，在N+型衬底1的另一侧设有N-型漂移区2，在N-型漂移区2中对称设置一对P型基区3，N+型源区5和P+型体接触区4，在N-型漂移区2的表面设有栅氧层8，在栅氧层8的表面设有多晶硅栅9，在多晶硅栅9的上方设有钝化层6，在N+型源区5和P+型体接触区4连接有源极金属7。常规碳化硅功率半导体器件工作原理是当有足够大的正电压施加在多晶硅栅上时，P型基区3与栅氧层8的界面会产生一个反型沟道，电子可以通过沟道从N+型源区5注入到N-型漂移区2。P型基区3和N+型源区5需要掺杂来形成，然而碳化硅器件元胞尺寸受到掺杂工艺和JFET区宽度限制，导致元胞宽度极限是4-6um，无法进一步缩小，，从而影响了器件的元胞密度和器件的正向电流能力。此外，碳化硅材料的离子注入工艺还会造成N-型漂移区2表面损伤，导致N-型漂移区2表面存在大量的界面态陷阱使得反型沟道载流子有效迁移率较小，导通电阻较高。同时传统的半导体器件基于载流子热注入工作机理，亚阈值摆幅在常温下最低只能达到60mV/decade。所以急需提出一种新型的高沟道电子迁移率和高功 率密度的功率器件。
发明内容
本发明针对上述问题，提出了一种基于异质结的高功率密度隧穿半导体器件及其制造工艺，该结构在保持击穿电压不变的基础上，使用石墨烯和碳化硅衬底形成异质结。当栅极施加正压时，石墨烯费米能级上移进入到导带，同时N-型漂移区电子浓度升高形成积累层，此时异质结势垒宽度变窄，发生带带隧穿效应，石墨烯价带的电子隧穿过异质结势垒进入到N-型漂移区的导带中。
同时，本发明器件的元胞尺寸比常规的碳化硅功率器件元胞小，在单位面积内大幅提升了元胞数量，有效降低了器件的比导通电阻，提升了器件的功率密度，同时降低了器件亚阈值摆幅，并且极大简化了制造工艺，降低了器件成本。
本发明采用如下技术方案：一种基于异质结的高功率密度隧穿半导体器件及其制造工艺，所述基于异质结的高功率密度隧穿功率半导体器件为轴对称结构，
包括N+衬底，其下设有漏极金属，其上设有N-漂移区；其特征在于，N-漂移区上方设有一对间隔设置的石墨烯源区，石墨烯源区上设有源极金属，N-漂移区上设有与石墨烯源区部分交叠的栅介质层，栅介质层上设有多晶硅栅，多晶硅栅上设有钝化层，多晶硅栅和栅介质层齐平，多晶硅栅与源极金属间隔设置，石墨烯源区与N-漂移区的接触处形成异质结，石墨烯源区、N-型区漂移区和栅介质层之间形成三重接触面，在三重接触面处发生隧穿效应。
进一步的，所述N-型漂移区上表面存在两个间隔的槽，石墨烯源区设置于槽内，石墨烯源区下方的N-型漂移区内设置P+型区。
进一步的，所述石墨烯源区设置于N-型漂移区的上表面，石墨烯源区下方的N-型漂移区内设置P+型区。
进一步的，所述石墨烯源区设置于N-型漂移区的上表面。
进一步的，所述N-型漂移区上表面存在两个间隔的槽，石墨烯源区设置于槽内。
进一步的，所述石墨烯源区下方的N-型漂移区内设置P+型区，栅介质层下方的N-型漂移区内设置一个第二P+型区，第二P+型区与石墨烯源区之间有一定距离。
进一步的，所述N+型衬底和N-型漂移区不受材料限制，可使用碳化硅、氧化镓、硅、金刚石或其他可形成异质结隧穿功率半导体器件衬底和漂移区的材料，所述N+型衬底和N-型漂移区的掺杂浓度也不受限制。
进一步的，所述石墨烯源区不受材料限制，可使用石墨烯、二硫化钼、多晶硅、金属或其他可形成异质结隧穿功率半导体器件源区的材料。
进一步的，所述栅介质层的厚度不受限制，并且栅介质层不受材料限制，可使用氧化硅、氧化铝、氧化铪、氧化锆或其他可形成异质结隧穿功率半导体器件栅介质层的材料。
一种基于异质结的高功率密度隧穿半导体器件的制造方法，包括如下步骤：
步骤1：在N+型衬底的表面上附上碳化硅以形成N-型漂移区；
步骤2：使用刻蚀工艺在N-型漂移区上的表面形成沟槽；
步骤3：使用掺杂工艺在沟槽底部形成P+型屏蔽层；
步骤4：在沟槽底部上形成一层石墨烯源区；
步骤5：使用沉积工艺在N-型漂移区上表面形成栅介质层；
步骤6：使用沉积工艺在栅介质层上表面沉积多晶硅并形成多晶硅栅；
步骤7：用沉积工艺在多晶硅栅上方形成隔离钝化层；
步骤8：最后，在石墨烯源区上表面形成源极金属，在N+型衬底的另一个表面上制作漏极金属。
本发明器件源极采用石墨烯材料，通过栅极施加电压，获得更低的亚阈值摆幅和更高的开态电流特性。
原理：当有足够大的正电压施加在栅极上时，N-型漂移区与栅氧化层的界面也会积累大量电子，会减小沟道区电阻和降低栅极下方的N-型漂移区的能带，N-型漂移区的能带的降低导致异质结势垒宽度变窄，更容易发生石墨烯源区的价带电子穿过禁带到达N-型漂移区导带的带带隧穿机制，使得该功率半导体器件在开态下产生如图3所示的I-V特性，其中电流路径是11，耗尽层分布为虚线10所示。
当负电压施加在栅极上时，沟道区的电子被排斥，电子浓度降低，提高了栅极下方的N-漂移区的能带。并且石墨烯的导带和价带间隙打开，异质结势垒宽度变大，极大地抑制了隧穿效应和双极效应的发生，使得该功率半导体器件在关态下有更小的漏电流。此时器件处于反向耐压状态，P+型区和N-型漂移区形成的同质PN结处于如图4所示的反向耐压状态，其中耗尽层分布为虚线10所示。
与现有技术相比，本发明具有如下优点：
(1)本发明器件源极采用石墨烯材料，石墨烯材料的导带和价带对称，并且只在 布里渊区的顶点处相交即相交于费米面上的一点，具有明显的可控电子带隙。根据石墨烯能带对称的特点，掺杂或施加外电场场都可以破坏能带对称性，进而打开带隙，并且石墨烯功函数可调。因此，石墨烯具有半导体能带特征。当栅极加零压时，器件处于关闭状态，石墨烯本征载流子浓度低，呈现高阻态，。当栅极加正压时，石墨烯费米能级上移，进入到导带，异质结势垒高度降低，异质结势垒宽度变窄，发生带带隧穿效应，产生正向隧穿电流。
(2)本发明器件源极采用的石墨烯材料掺杂浓度低，几乎处于本征状态，石墨烯本征载流子浓度低时呈现高阻状态，反向耐压时漏电流小。
(3)本发明器件源极采用的石墨烯材料热导率是碳化硅六倍且厚度极薄，所以相比传统功率器件，本发明器件具有更好的散热特性。
(4)当有足够大的正电压施加在栅极上时，本发明器件的N型漂移区与栅氧层的界面会积累大量电子，减小了沟道区电阻，又因为石墨烯沟道载流子迁移率在理想状态下是200000cm 2/(V·s)，所以沟道电阻极低，使得本发明器件在开态下有极好的正向I-V特性。
(5)在续流状态下，本发明器件采用石墨烯材料和N-漂移区形成的异质结代替了常规碳化硅功率半导体器件由离子注入掺杂工艺掺杂形成的PN同质结，由于异质结势垒更低，续流电流更大，同时可通过掺杂等手段改变石墨烯功函数获得异质结势垒可调的异质结二极管，进一步发挥了本发明器件在续流状态下的优势。
(6)本发明器件源极采用石墨烯材料，石墨烯材料和N-漂移区形成异质结，在栅极电压的控制下发生隧穿效应，沟道为石墨烯源极、N-型漂移区接触面以及栅绝缘层的三重接触面。而常规碳化硅MOS，由于碳化硅材料特性限制，只能通过离子注入掺杂工艺形成P型基区和N+型源极，然后通过栅极控制形成反型层导电沟道。但是离子注入掺杂工艺会损伤N-型漂移区表面，导致电子迁移率低。与常规功率半导体器件相比，本发明器件的沟道是由石墨烯和高浓度的电子积累区形成，不需要通过离子注入工艺来形成电子反型层导电沟道，不会对沟道区的N-漂移区表面造成损伤，并且极大简化了制造工艺，降低了器件成本，同时在单位面积内大幅提升了元胞数量。
(7)石墨烯源区、N-型区漂移区和栅介质层的三者接触，形成三重接触面，在三重接触面处发生隧穿效应，沟道密度大，电流能力强。
(8)本发明器件与传统器件工艺兼容，且石墨烯可以大面积制作，工艺难度小。
(9)本发明器件在石墨烯源区下方设有P+型区，P+型区与N-型漂移区形成PN结，石墨烯源区与N-型漂移区形成异质结。当器件反偏耐压时，没有P+型区时的电场峰值在石墨烯源区与N-型漂移区形成的异质结边界处，反向漏电流大，器件击穿电压小。当有P+型区时的电场峰值在P+型区与N-型漂移区形成的PN结边界处，提高了器件的雪崩能力，减小了反偏漏电流，增大了器件击穿电压。
附图说明
图1是常规碳化硅功率半导体器件结构主视图；
图2是根据本发明第一实施例的半导体器件元胞的主视图；
图3是根据本发明第一实施例的正向电流路径示意图；
图4是根据本发明第一实施例的反向状态耗尽层分布示意图；
图5是根据本发明第二实施例的半导体器件元胞的主视图；
图6是根据本发明第三实施例的半导体器件元胞的主视图；
图7是根据本发明第四实施例的半导体器件元胞的主视图；
图8是根据本发明第五实施例的半导体器件元胞的主视图。
具体实施方式
下面结合说明书附图对本发明作详细说明。
实施例1：
参照图2，一种基于异质结的高功率密度隧穿半导体器件，所述基于异质结的高功率密度隧穿功率半导体器件为轴对称结构，包括：N+型衬底1，在N+型衬底1的下表面连接有漏极金属8，在N+型衬底1的上表面设有N-型漂移区2，N-型漂移区2内设置一对P+型区9，在N-型漂移区2上表面设置一对石墨烯源区3，石墨烯源区3的上表面对称设置源极金属4，N-型漂移区2和石墨烯源区3上表面设有栅介质层5，栅介质层5上表面设有多晶硅栅6，多晶硅栅6上表面设有钝化层7。在N-型漂移区2上表面刻槽使得N-型漂移区2分为两部分N-型漂移区2.1和N-型漂移区2.2，在槽底即N-型漂移区2.1的上表面内设置一对P+型区9，并且在N-型漂移区2上表面的槽内对称设置一对石墨烯源区3，一对石墨烯源区3之间有一定距离，N-型漂移区2.2上设有与石墨烯源区3部分交叠的栅介质层5，多晶硅栅6和栅介质层5齐平，多晶硅栅6与源极金属4之间有一定距离，石墨烯源区3与N-型漂移区2的接触面处形成的异质结。
本发明采用如下方法来制备：
步骤1：取一个N+型衬底1，在N+型衬底1的一个表面上附上碳化硅以形成N-型漂移区2；
步骤2：使用刻蚀工艺在N-型漂移区2上的表面形成沟槽；
步骤3：使用掺杂工艺在沟槽底部形成P+型屏蔽层9；
步骤4：在沟槽底部上形成一层石墨烯源区3；
步骤5：使用沉积工艺在N-型漂移区2上表面形成栅介质层5；
步骤6：使用沉积工艺在栅介质层5上表面沉积多晶硅并形成多晶硅栅6；
步骤7：用沉积工艺在多晶硅栅6上方形成隔离钝化层7；最后，在石墨烯源区3上表面形成源极金属4，在N+型衬底1的另一个表面上制作漏极金属8。
该结构P+型区与N-型漂移区形成PN结，石墨烯源区与N-型漂移区形成异质结。在保持击穿电压不变的基础上，通过刻槽工艺增大了异质结的面积。当栅极施加正压时，石墨烯费米能级上移进入到导带，同时N-型漂移区电子浓度升高形成积累层，此时异质结势垒宽度变窄，在石墨烯源区、N-型区漂移区和栅介质层的三重接触面处发生了带带隧穿效应，石墨烯价带的电子隧穿过异质结势垒进入到N-型漂移区的导带中形成电流。电流路径11如图3所示，耗尽层10在石墨烯下方，不影响电流路径11。当器件反偏耐压时，没有P+型区时的电场峰值位于石墨烯源区与N-型漂移区形成的异质结边界处，反向漏电流大，器件击穿电压小。参照图4，当有P+型区时，耗尽层10完全覆盖了石墨烯源区3，屏蔽了异质结界面的电场，电场峰值被转移至P+型区与N-型漂移区形成的PN结边界处，减小了反偏漏电流，提高了器件的雪崩能力，增大了器件击穿电压。同时，由于本发明器件掺杂工艺简单且掺杂区域小使得本发明器件的元胞尺寸不受到掺杂工艺和JFET区的限制，所以本发明器件的元胞尺寸远小于常规的碳化硅功率器件，在单位面积内大幅提升了元胞数量，有效降低了器件的比导通电阻、提升了器件的功率密度，同时降低器件亚阈值摆幅、并且极大简化了制造工艺，降低了器件成本。
实施例2：
参照图5，一种基于异质结的高功率密度隧穿半导体器件，所述基于异质结的高功率密度隧穿功率半导体器件为轴对称结构，包括：N+型衬底1，在N+型衬底1的下表面连接有漏极金属8，在N+型衬底1的上表面设有N-型漂移区2，在N-型漂移区2的上表面内设置一对P+型区9，在N-型漂移区2的上表面对称设置一对石墨烯源区3，石墨烯源区3的上表面对称设置源极金属4，N-型漂移区2和石墨烯源区3上表面设有栅 介质层5，栅介质层5上表面设有多晶硅栅6，多晶硅栅6上方设有钝化层7。N-型漂移区2的上表面内设有一对P+型区9，在N-型漂移区2上表面对称设置一对石墨烯源区3，一对石墨烯源区3之间有一定距离，N-型漂移区2上设有与石墨烯源区3部分交叠的栅介质5，多晶硅栅6和栅介质层5齐平，多晶硅栅6与源极金属4之间有一定距离，石墨烯源区3与N-型漂移区2的接触面处形成异质结。
本发明采用如下方法来制备：
步骤1：取一个N+型衬底1，在N+型衬底1的另一个表面上附上碳化硅以形成N-型漂移区2；
步骤2：使用掺杂工艺在N-型漂移区2内形成P+型屏蔽层9；
步骤3：在N-型漂移区2上形成一层石墨烯源区3；
步骤4：使用沉积工艺在N-型漂移区2上表面形成栅介质层5；
步骤5：使用沉积工艺在栅介质层5上表面沉积多晶硅并形成多晶硅栅6；
步骤6：用沉积工艺在多晶硅栅6上方形成隔离钝化层7；最后，在石墨烯源区3上表面形成源极金属4，在N+型衬底1的另一个表面上制作漏极金属8。
该结构在保持击穿电压不变的基础上，使用石墨烯和碳化硅衬底形成异质结，当栅极施加正压时石墨烯费米能级上移，进入到导带，同时N-型漂移区电子浓度升高形成积累层，此时异质结势垒宽度变窄，在石墨烯源区、N-型区漂移区和栅介质层的三重接触点处发生隧穿效应，石墨烯价带的电子隧穿过异质结势垒进入到N-型漂移区的导带中。P+型区与N-型漂移区形成PN结，石墨烯源区与N-型漂移区形成异质结，当器件反偏耐压时，没有P+型区时的电场峰值位于石墨烯源区与N-型漂移区形成的异质结边界处，反向漏电流大，器件击穿电压小。当有P+型区时的电场峰值被转移至P+型区与N-型漂移区形成的PN结边界处，提高了器件的雪崩能力，减小了反偏漏电流，增大了器件击穿电压。同时，本发明器件的元胞尺寸比常规的碳化硅功率器件元胞小，在单位面积内大幅提升了元胞数量，有效降低了器件的比导通电阻、提升了器件的功率密度，同时降低器件亚阈值摆幅、并且极大简化了制造工艺，降低了器件成本。
实施例3：
参照图6，一种基于异质结的高功率密度隧穿半导体器件，所述基于异质结的高功率密度隧穿功率半导体器件为轴对称结构，包括：N+型衬底1，在N+型衬底1的下表面连接有漏极金属8，在N+型衬底1的上表面设有N-型漂移区2，在N-型漂移区2的 上表面对称设置一对石墨烯源区3，石墨烯源区3的上表面对称设置源极金属4，N-型漂移区2和石墨烯源区3上表面设有栅介质层5，栅介质层5上表面设有多晶硅栅6，多晶硅栅6上方设有钝化层7。在N-型漂移区2上表面对称设置一对石墨烯源区3，一对石墨烯源区3之间有一定距离，N-型漂移区2上设有与石墨烯源区3部分交叠的栅介质层5，多晶硅栅6和栅介质层5齐平，多晶硅栅6与源极金属4之间有一定距离，石墨烯源区3与部分N-型漂移区2的接触面处形成异质结。
本发明采用如下方法来制备：
步骤1：取一个N+型衬底1，在N+型衬底1的另一个表面上附上碳化硅以形成N-型漂移区2；
步骤2：在N-型漂移区2上形成一层石墨烯源区3；
步骤3：使用沉积工艺在N-型漂移区2上表面形成栅介质层5；
步骤4：使用沉积工艺在栅介质层5上表面沉积多晶硅并形成多晶硅栅6；
步骤5：用沉积工艺在多晶硅栅6上方形成隔离钝化层7；最后，在石墨烯源区3上表面形成源极金属4，在N+型衬底1的另一个表面上制作漏极金属8。
使用石墨烯和碳化硅衬底形成异质结，当栅极施加正压时石墨烯费米能级上移，进入到导带，同时N-型漂移区电子浓度升高形成积累层，此时异质结势垒宽度变窄，在石墨烯源区、N-型区漂移区和栅介质层的三重接触点处发生带带隧穿效应，石墨烯价带的电子隧穿过异质结势垒进入到N-型漂移区的导带中。
同时，由于本实施例无需注入掺杂工艺即可形成三端口功率器件，器件的元胞尺寸不受到掺杂工艺和JFET区的限制，所以本发明器件的元胞比常规的碳化硅功率器件元胞小，大幅提升了器件的元胞密度，有效降低了器件的比导通电阻，增大了器件的功率密度，同时降低了器件亚阈值摆幅，并且极大简化了制造工艺，降低了器件成本。
实施例4：
参照图7，一种基于异质结的高功率密度隧穿半导体器件，所述基于异质结的高功率密度隧穿功率半导体器件为轴对称结构，包括：N+型衬底1，在N+型衬底1的下表面连接有漏极金属8，在N+型衬底1的上表面设有N-型漂移区2，在N-型漂移区2的上表面对称设置一对石墨烯源区3，石墨烯源区3的上表面对称设置源极金属4，N-型漂移区2和石墨烯源区3上表面设有栅介质层5，栅介质层5上表面设有多晶硅栅6，多晶硅栅6上方设有钝化层7。在N-型漂移区2上表面刻槽，一对石墨烯源区3在N- 型漂移区2的槽内对称设置，一对石墨烯源区3之间有一定距离，N-型漂移区2上设有与石墨烯源区3部分交叠的栅介质层5，多晶硅栅6和栅介质层5齐平，多晶硅栅6与源极金属4之间有一定距离，石墨烯源区3与部分N-型漂移区2的接触面处形成在功率器件中的异质结。
本发明采用如下方法来制备：
步骤1：取一个N+型衬底1，在N+型衬底1的另一个表面上附上碳化硅以形成N-型漂移区2；
步骤2：使用刻蚀工艺在N-型漂移区2上的表面形成沟槽；
步骤3：在沟槽底部上形成一层石墨烯源区3；
步骤4：使用沉积工艺在N-型漂移区2上表面形成栅介质层5；
步骤5：使用沉积工艺在栅介质层5上表面沉积多晶硅并形成多晶硅栅6；
步骤6：用沉积工艺在多晶硅栅6上方形成隔离钝化层7；最后，在石墨烯源区3上表面形成源极金属4，在N+型衬底1的另一个表面上制作漏极金属8。
使用石墨烯和碳化硅衬底形成异质结，并且通过刻槽工艺来增大异质结的面积，当栅极施加正压时石墨烯费米能级移，进入到导带，同时N-型漂移区电子浓度升高形成积累层，此时异质结势垒宽度变窄，在石墨烯源区、N-型区漂移区和栅介质层的三重接触面处发生了带带隧穿效应，石墨烯价带的电子隧穿过异质结势垒进入到N-型漂移区的导带中。该结构发生带带隧穿效应的面积更大，电流密度更大。
同时，由于本实施例无需注入掺杂工艺即可形成三端口功率器件，器件的元胞尺寸不受到掺杂工艺和JFET区的限制，所以本发明器件的元胞比常规的碳化硅功率器件元胞小，大幅提升了器件的元胞密度，有效降低了器件的比导通电阻，增大了器件的功率密度，同时降低了器件亚阈值摆幅，并且极大简化了制造工艺，降低了器件成本。
实施例5：
参照图8，一种基于异质结的高功率密度隧穿半导体器件及其制造工艺，所述基于异质结的高功率密度隧穿功率半导体器件为轴对称结构，包括：N+型衬底1，在N+型碳化硅衬底1的下表面连接有漏极金属8，在N+型衬底1的上表面设有N-型漂移区2，在N-型漂移区2的上表面对称设置一对石墨烯源区3，石墨烯源区3的上表面对称设置源极金属4。N-型漂移区2和石墨烯源区3上表面设有栅介质层5，栅介质层5上表面设有多晶硅栅6，多晶硅栅6上方设有钝化层7，在N-型漂移区2设有一对P+型区9， 在栅介质层5下方的N-型漂移区2内设置一个P+型区10。在N-型漂移区2上表面刻槽，在槽底设有一对P+型区9，在N-型漂移区2的槽内对称设置一对石墨烯源区3，一对石墨烯源区3之间有一定距离，N-型漂移区2上设有与石墨烯源区3部分交叠的栅介质层5，多晶硅栅6和栅介质层5齐平，多晶硅栅6与源极金属4之间有一定距离，石墨烯源区3与N-型漂移区2的接触面处形成异质结，石墨烯源区3、N-型区漂移区2和栅介质层5的三者接触，形成三重接触点，该接触点被P+型区10与N-漂移区2的耗尽层包住。P+型区10与石墨烯源区3之间有一定距离，该距离的大小比多晶硅栅6施加负压或者零压时的P+型区10与N-漂移区2的耗尽层宽度小，此时耗尽层包住三重接触面，同时该距离的大小比多晶硅栅6施加正压时的P+型区9与N-漂移区2的耗尽层宽度大，此时耗尽层不包住三重接触点。
本发明采用如下方法来制备：
步骤1：取一个N+型衬底1，在N+型衬底1的另一个表面上附上碳化硅以形成N-型漂移区2；
步骤2：使用刻蚀工艺在N-型漂移区2上的表面形成沟槽；
步骤3：使用掺杂工艺在沟槽底部形成P+型屏蔽层9，在N-型漂移区2上表面掺杂三族元素形成P+型屏蔽层10；
步骤4：在沟槽底部上形成一层石墨烯源区3；
步骤5：使用沉积工艺在N-型漂移区2上表面形成栅介质层5；
步骤6：使用沉积工艺在栅介质层5上表面沉积多晶硅并形成多晶硅栅6；
步骤7：用沉积工艺在多晶硅栅6上方形成隔离钝化层7；最后，在石墨烯源区3上表面形成源极金属4，在N+型衬底1的另一个表面上制作漏极金属8。
使用石墨烯和碳化硅衬底形成异质结，通过栅极施加正压使石墨烯费米能级上移，进入到导带，同时N-型漂移区电子浓度升高形成积累层。电子积累区使得栅介质层下方的P+型区与N-漂移区之间的耗尽层变窄，不再包住三重接触点。这时栅极施加足够的正压，石墨烯源区、N-型区漂移区和栅介质层的三重接触面处产生带带隧穿效应，石墨烯价带的电子隧穿过异质结势垒进入到N-型漂移区的导带中。当栅极施加负压或者零压时栅介质层下方的P+型区与N-漂移区之间的耗尽层包住三重接触点。当器件反偏时，P+区9使电场峰值从异质结边界处转移到PN结边界处，提高了器件雪崩能力，减小了反偏漏电流，增大了击穿电压，P+型区10屏蔽了栅介质层5的电场，提高了器件 的栅氧可靠性。
该结构在不牺牲基于异质结的高功率密度隧穿功率半导体器件的正向导电能力的情况下，提升了器件栅氧可靠性，降低了栅漏电容，提高了开关特性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种基于异质结的高功率密度隧穿半导体器件，为轴对称结构，包括N+衬底，其下设有漏极金属，其上设有N-漂移区；其特征在于，N-漂移区上方设有一对间隔设置的石墨烯源区，石墨烯源区上设有源极金属，N-漂移区上设有与石墨烯源区部分交叠的栅介质层，栅介质层上设有多晶硅栅，多晶硅栅上设有钝化层，多晶硅栅与源极金属间隔设置，石墨烯源区与N-漂移区的接触处形成异质结，石墨烯源区、N-型区漂移区和栅介质层之间形成三重接触面，在三重接触面处发生隧穿效应。
  2. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述N-型漂移区(2)上表面存在两个间隔的槽，石墨烯源区(3)设置于槽内，石墨烯源区(3)下方的N-型漂移区(2)内设置P+型区(9)。
  3. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述石墨烯源区(3)设置于N-型漂移区(2)的上表面，石墨烯源区(3)下方的N-型漂移区(2)内设置P+型区(9)。
  4. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述石墨烯源区(3)设置于N-型漂移区(2)的上表面。
  5. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述N-型漂移区(2)上表面存在两个间隔的槽，石墨烯源区(3)设置于槽内。
  6. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述石墨烯源区(3)下方的N-型漂移区(2)内设置P+型区(9)，栅介质层(5)下方的N-型漂移区(2)内设置一个第二P+型区(10)，第二P+型区(10)与石墨烯源区(3)之间有一定距离。
  7. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述N+型衬底(1)和N-型漂移区(2)不受材料限制，可使用碳化硅、氧化镓、硅、金刚石或其他可形成异质结隧穿功率半导体器件衬底和漂移区的材料，所述N+型衬底(1)和N-型漂移区(2)的掺杂浓度也不受限制。
  8. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件，其特征在于，所述石墨烯源区(3)不受材料限制，可使用石墨烯、二硫化钼、多晶硅、金属或其他可形成异质结隧穿功率半导体器件源区的材料。
  9. 根据权利要求1所述的一种基于异质结的高功率密度隧穿半导体器件及其制造工艺，其特征在于，栅介质层(5)的厚度不受限制，并且栅介质层(5)不受材料限制， 可使用氧化硅、氧化铝、氧化铪、氧化锆或其他可形成异质结隧穿功率半导体器件栅介质层的材料。
  10. 一种基于异质结的高功率密度隧穿半导体器件的制造方法，其特征在于，包括如下步骤：
    步骤1：在N+型衬底(1)的表面上附上碳化硅以形成N-型漂移区(2)；
    步骤2：使用刻蚀工艺在N-型漂移区(2)上的表面形成沟槽；
    步骤3：使用掺杂工艺在沟槽底部形成P+型屏蔽层(9)；
    步骤4：在沟槽底部上形成一层石墨烯源区(3)；
    步骤5：使用沉积工艺在N-型漂移区(2)上表面形成栅介质层(5)；
    步骤6：使用沉积工艺在栅介质层(5)上表面沉积多晶硅并形成多晶硅栅(6)；
    步骤7：用沉积工艺在多晶硅栅(6)上方形成隔离钝化层(7)；
    步骤8：最后，在石墨烯源区(3)上表面形成源极金属(4)，在N+型衬底(1)的另一个表面上制作漏极金属(8)。
PCT/CN2022/110104 2022-04-02 2022-08-03 基于异质结的高功率密度隧穿半导体器件及其制造工艺 WO2023184812A1 (zh)

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