CN111312802A - 低开启电压和低导通电阻的碳化硅二极管及制备方法 - Google Patents

低开启电压和低导通电阻的碳化硅二极管及制备方法 Download PDF

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CN111312802A
CN111312802A CN202010126013.9A CN202010126013A CN111312802A CN 111312802 A CN111312802 A CN 111312802A CN 202010126013 A CN202010126013 A CN 202010126013A CN 111312802 A CN111312802 A CN 111312802A
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gate dielectric
silicon carbide
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邓小川
路晓飞
徐晓杰
李旭
李轩
孙燕
张波
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University of Electronic Science and Technology of China
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Abstract

本发明提供一种低开启电压和低导通电阻的碳化硅二极管及其制作方法，包括阴极金属电极、阴极金属电极上方的N+衬底、N+衬底上方的N‑漂移区；N‑漂移区上方的P型屏蔽埋层、P型屏蔽埋层内部的P+欧姆接触区、P+欧姆接触区上方的阳极金属电极、P型屏蔽埋层上方的槽栅介质层、槽栅介质层内部的多晶硅槽栅、槽栅介质层之间的N+源区、N+源区之间上方的平面栅介质层、平面栅介质层内部的多晶硅平面栅，阳极金属电极覆盖槽栅介质层、多晶硅槽栅、N+源区、平面栅介质层、多晶硅平面栅。本发明通过将三沟道的积累型沟道MOSFET与JFET串联结合而形成超势垒二极管，具有开启电压低、导通电阻小、反向耐压高、泄漏电流小等特点。

Description

低开启电压和低导通电阻的碳化硅二极管及制备方法
技术领域
本发明属于功率半导体技术领域，具体是一种低开启电压和低导通电阻的碳化硅二极管。
背景技术
碳化硅(Silicon Carbide)材料作为第三代宽禁带半导体材料的代表之一，具有禁带宽度大、临界击穿电场高、热导率高和电子饱和漂移速度高等特点，使其在大功率、高温及高频电力电子领域具有广阔的应用前景。
二极管是使用最早的电子器件，目前随着电子器件的革新换代，在高频高压应用领域，PiN功率二极管和肖特基功率二极管应用最为广泛。PiN二极管有着高耐压、低反向泄漏电流等优点，但PiN二极管内建电势较高，开启电压高；此外PiN做为一种双极器件，电导调制效应在漂移区中产生的大量少数载流子极大提高器件导通能力，降低导通损耗；相反地也降低了器件的关断速度，限制了二极管向高频化方向发展。肖特基二极管正向开启电压小，做为单极器件没有少子存储效应，开关速度快，但是反向泄漏电流大，很难应用于高压大电流领域。
为解决传统二极管开启电压高、肖特基二极管泄漏电流大等问题，本发明提出了一种具有三个积累型沟道的低开启电压和低导通电阻的碳化硅二极管结构。当器件两端不加偏压时，在栅氧化层下面的N-漂移区中会形成一层耗尽层，同时P型屏蔽埋层与N-漂移区接触的区域也会形成耗尽层。由于P型埋层是高掺杂区域，因此耗尽层主要在N-漂移区中，此时器件导通路径完全夹断；当器件两端逐渐增加偏压时，器件栅氧化层下面材料的表面逐渐积累载流子形成导通沟道，同时P型埋层之间耗尽区变窄形成电流通路，器件开始导通。由于在单个平面积累沟道的基础上增加了两个垂直积累型沟道，因此增加了器件沟道密度，减小了导通电阻，从而降低了器件导通损耗。
发明内容
本发明的目的是针对以上所述存在的问题，提出一种低开启电压和低导通电阻的碳化硅二极管及其制备方法。其结构特点是将三沟道的积累型沟道MOSFET与JFET串联结合而形成一种低开启电压和低导通电阻的碳化硅二极管，所述二极管相较于传统超势垒二极管增加了两个槽栅垂直积累沟道，由原来的单一沟道结构变为三沟道结构，极大提高沟道密度，减小导通电阻，从而降低器件的导通损耗。所述二极管在零偏压情况下，平面栅氧化层下面的N-漂移区和靠近槽栅氧化层的N-漂移区都会形成耗尽区，P+埋层和N-漂移区接触区域也会形成耗尽区，器件完全夹断；在阳极逐渐增加偏压，靠近栅氧化层的N-漂移区会积累载流子而逐渐形成导电沟道，JFET区耗尽区也会逐渐变窄出现电流通路，器件导通，此时器件开启电压远小于PN结开启电压；阳极偏压继续增大至PN结开启电压，寄生PiN二极管导通，大量载流子注入N-漂移区进行电导调制，器件导通电阻减小。在反向阻断状态，P型屏蔽埋层和N-漂移区反偏而JFET区完全夹断，反向耐压主要由寄生PiN二极管承担，泄漏电流小耐压高。因此所述二极管具有开启电压低、导通电阻小、反向耐压高、泄漏电流小等优点。
为达到上述目的，本发明采用下述技术方案：
一种低开启电压和低导通电阻的碳化硅二极管，包括阴极金属电极1、阴极金属电极1上方的N+衬底2、N+衬底2上方的N-漂移区3；位于N-漂移区3上方的P型屏蔽埋层4、位于P型屏蔽埋层4内部的P+欧姆接触区5、位于P+欧姆接触区5上方的阳极金属电极6、位于P型屏蔽埋层4上方的槽栅介质层7、位于槽栅介质层7内部的多晶硅槽栅8、位于槽栅介质层7之间的N+源区9、位于N+源区9之间上方的平面栅介质层10、位于平面栅介质层10内部的多晶硅平面栅11，阳极金属电极6覆盖槽栅介质层7、多晶硅槽栅8、N+源区9、平面栅介质层10、多晶硅平面栅11。
作为优选方式，所述槽栅介质层7和平面栅介质层10为SiO2。
作为优选方式，N+衬底2、N-漂移区3、P型屏蔽埋层4、P+欧姆接触区5和N+源区9的材料均为碳化硅。
作为优选方式，所述多晶硅槽栅8和多晶硅平面栅11为铝离子注入的P型多晶硅栅。
作为优选方式，所述P型屏蔽埋层4、P+欧姆接触区5和N+源区9均为多次离子注入形成。
作为优选方式，所述P+欧姆接触区5和N+源区9与阳极金属电极6均形成欧姆接触。
为实现上述发明目的，本发明还提供一种所述的一种低开启电压和低导通电阻的碳化硅二极管的制备方法，包括以下步骤：
第一步：清洗碳化硅外延片，刻蚀外延片形成P型屏蔽埋层离子注入窗口；
第二步：注入铝离子形成P型屏蔽埋层；
第三步：注入铝离子形成P+欧姆接触区；
第四步：注入氮离子形成N+源区并激活退火；
第五步：刻蚀栅槽并干氧氧化生成栅氧化层，随后在氮气氛围下的退火；
第六步：淀积多晶硅，进行铝离子注入、激活退火并对多晶硅进行图形化；
第七步：淀积金属形成欧姆接触；
第八步：正面阳极金属加厚；
第九步：背面淀积金属形成阴极电极。
所述器件栅介质层端为栅极，N+衬底端为阴极，N+源区和P+欧姆接触区为阳极；
本发明的有益效果为：本发明通过将三沟道的积累型沟道MOSFET与JFET串联结合而形成超势垒二极管，具有开启电压低、导通电阻小、反向耐压高、泄漏电流小等特点。
附图说明
图1是所述低开启电压和低导通电阻的碳化硅二极管结构示意图；
图2是本发明制备方法刻蚀外延片形成P型屏蔽埋层离子注入窗口示意图；
图3是本发明制备方法注入铝离子形成P型屏蔽埋层示意图；
图4是本发明制备方法注入铝离子形成P+欧姆接触区示意图；
图5是本发明制备方法注入氮离子形成N+源区示意图；
图6是本发明制备方法刻蚀栅槽并干氧氧化生成栅氧化层示意图；
图7是本发明制备方法淀积多晶硅并对多晶硅进行图形化示意图；
图8是本发明制备方法淀积金属形成欧姆接触示意图；
图9是本发明制备方法正面阳极金属加厚示意图；
图10是本发明制备方法背面淀积金属形成阴极电极示意图；
1为阴极金属电极，2为N+衬底，3为N-漂移区，4为P型屏蔽埋层，5为P+欧姆接触区，6为阳极金属电极，7为槽栅介质层，8为多晶硅槽栅，9为N+源区，10为平面栅介质层，11为多晶硅平面栅。
具体实施方式
以下说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
一种低开启电压和低导通电阻的碳化硅二极管，包括阴极金属电极1、阴极金属电极1上方的N+衬底2、N+衬底2上方的N-漂移区3；位于N-漂移区3上方的P型屏蔽埋层4、位于P型屏蔽埋层4内部的P+欧姆接触区5、位于P+欧姆接触区5上方的阳极金属电极6、位于P型屏蔽埋层4上方的槽栅介质层7、位于槽栅介质层7内部的多晶硅槽栅8、位于槽栅介质层7之间的N+源区9、位于N+源区9之间上方的平面栅介质层10、位于平面栅介质层10内部的多晶硅平面栅11，阳极金属电极6覆盖槽栅介质层7、多晶硅槽栅8、N+源区9、平面栅介质层10、多晶硅平面栅11。
所述槽栅介质层7和平面栅介质层10为SiO2。
N+衬底2、N-漂移区3、P型屏蔽埋层4、P+欧姆接触区5和N+源区9的材料均为碳化硅。
所述多晶硅槽栅8和多晶硅平面栅11为铝离子注入的P型多晶硅栅。
所述P型屏蔽埋层4、P+欧姆接触区5和N+源区9均为多次离子注入形成。
所述P+欧姆接触区5和N+源区9与阳极金属电极6均形成欧姆接触。
如图2～图10所示，本实施例还提供一种所述的一种低开启电压和低导通电阻的碳化硅二极管的制备方法，包括以下步骤：
第一步：清洗碳化硅外延片，刻蚀外延片形成P型屏蔽埋层离子注入窗口；
第二步：注入铝离子形成P型屏蔽埋层；
第三步：注入铝离子形成P+欧姆接触区；
第四步：注入氮离子形成N+源区并激活退火；
第五步：刻蚀栅槽并干氧氧化生成栅氧化层，随后在氮气氛围下的退火；
第六步：淀积多晶硅，进行铝离子注入、激活退火并对多晶硅进行图形化；
第七步：淀积金属形成欧姆接触；
第八步：正面阳极金属加厚；
第九步：背面淀积金属形成阴极电极。
所述器件栅介质层端为栅极，N+衬底端为阴极，N+源区和P+欧姆接触区为阳极；
上述说明仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

1.一种低开启电压和低导通电阻的碳化硅二极管，其特征在于：包括阴极金属电极(1)、阴极金属电极(1)上方的N+衬底(2)、N+衬底(2)上方的N-漂移区(3)；位于N-漂移区(3)上方的P型屏蔽埋层(4)、位于P型屏蔽埋层(4)内部的P+欧姆接触区(5)、位于P+欧姆接触区(5)上方的阳极金属电极(6)、位于P型屏蔽埋层(4)上方的槽栅介质层(7)、位于槽栅介质层(7)内部的多晶硅槽栅(8)、位于槽栅介质层(7)之间的N+源区(9)、位于N+源区(9)之间上方的平面栅介质层(10)、位于平面栅介质层(10)内部的多晶硅平面栅(11)，阳极金属电极(6)覆盖槽栅介质层(7)、多晶硅槽栅(8)、N+源区(9)、平面栅介质层(10)、多晶硅平面栅(11)。
2.根据权利要求1所述的一种低开启电压和低导通电阻的碳化硅二极管，其特征在于：所述槽栅介质层(7)和平面栅介质层(10)为SiO2。
3.根据权利要求1所述的一种低开启电压和低导通电阻的碳化硅二极管，其特征在于：N+衬底(2)、N-漂移区(3)、P型屏蔽埋层(4)、P+欧姆接触区(5)和N+源区(9)的材料均为碳化硅。
4.根据权利要求1所述的一种低开启电压和低导通电阻的碳化硅二极管，其特征在于：所述多晶硅槽栅(8)和多晶硅平面栅(11)为铝离子注入的P型多晶硅栅。
5.根据权利要求1所述的一种低开启电压和低导通电阻的碳化硅二极管，其特征在于：所述P型屏蔽埋层(4)、P+欧姆接触区(5)和N+源区(9)均为多次离子注入形成。
6.根据权利要求1所述的一种低开启电压和低导通电阻的碳化硅二极管，其特征在于：所述P+欧姆接触区(5)和N+源区(9)与阳极金属电极(6)均形成欧姆接触。
7.根据权利要求1至6任意一项所述的一种低开启电压和低导通电阻的碳化硅二极管的制备方法，其特征在于，包括以下步骤：
第一步：清洗碳化硅外延片，刻蚀外延片形成P型屏蔽埋层离子注入窗口；
第二步：注入铝离子形成P型屏蔽埋层；
第三步：注入铝离子形成P+欧姆接触区；
第四步：注入氮离子形成N+源区并激活退火；
第五步：刻蚀栅槽并干氧氧化生成栅氧化层，随后在氮气氛围下的退火；
第六步：淀积多晶硅，进行铝离子注入、激活退火并对多晶硅进行图形化；
第七步：淀积金属形成欧姆接触；
第八步：正面阳极金属加厚；
第九步：背面淀积金属形成阴极电极。
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