CN114975612A - 具有低电磁干扰噪声的SiC沟槽栅IGBT器件及制备方法 - Google Patents
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Abstract
本发明提供一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件及制备方法，属于功率半导体器件技术领域。主要用于在不提高器件生产成本、不增加额外工艺流程、不牺牲器件其他性能的前提下，提升栅极电阻对IGBT开启过程的控制能力，降低器件电压突变dV/dt及电流突变dI/dt噪声。与传统沟槽栅SiC IGBT元胞结构相比，本发明新型SiC元胞结构通过在部分P+欧姆接触区和N+源区上覆盖氧化层和多晶硅栅，在不影响米勒电容CGC的前提下，增加器件的栅极到发射极寄生氧化层电容CGE，有效抑制栅极自充电效应，在IGBT开启过程中实现低损耗及低电磁干扰噪声，降低IGBT模块产生的传导干扰及辐射干扰，增强电力系统运行可靠性。
Description
技术领域
本发明属于功率半导体器件技术领域，具体涉及一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件。
背景技术
作为第三代宽禁带半导体材料的代表之一，碳化硅(Silicon Carbide，SiC)材料具有比硅材料更宽的禁带宽度(3倍)，更高的临界电场(10倍)、更高的载流子饱和漂移速度(2倍)、更高的热导率(2.5倍)等优点，是制备高压电力电子器件绝佳的材料，在大功率、高温、高压及抗辐照电力电子领域有广阔的应用前景。
具有电导调制效应的SiC IGBT器件集成了MOS场控结构的高可控性和双极型结构开态大电流能力两方面优点，具有导通损耗低、阻断电压高、开关速度高及开关损耗低等特性。SiC IGBT主要有平面栅和沟槽栅两种。SiC平面栅IGBT相邻P阱区间存在JFET效应，使其正向导通电压显著增大；SiC沟槽栅IGBT导电沟道垂直，无需在表面制作导电沟道，且不存在相邻P阱区之间的JFET结构，相比于SiC平面栅IGBT，元胞尺寸更紧凑，沟道密度和近表面载流子浓度更高，正向导通压降更低，损耗更低。
随着母线电压的增加和开关频率的提高，电路系统对沟槽栅IGBT低电磁干扰(EMI)噪声的要求也随之提高。在沟槽栅IGBT的开启过程中，栅电容的充电电流除栅极驱动电流外，还包括由非平衡少子积累在栅氧附近产生的自充电位移电流，自充电位移电流越大，沟槽栅IGBT器件开启过程产生的EMI噪声(dVCE/dt、dICE/dt噪声和续流二极管反向恢复dVKA/dt噪声)就越大，栅电阻Rg对IGBT开启过程的控制能力逐渐减弱。
在沟槽栅IGBT设计中，一种方案是通过降低非平衡少子积累在栅氧附近的速率或降低栅-集电极电容CGC来减小自充电位移电流，进而达到抑制EMI噪声的目的，但该方案可能导致器件正向导通压降等参数的退化；另一种方案是保持栅-集电极电容CGC不变，增加栅-发射极电容CGE实现抑制EMI噪声的目的，但已有降低CGC和CGE比值的器件结构需要复杂的工艺过程实现。
因此，现亟需一种SiC沟槽栅IGBT器件结构，能在不提高器件生产成本、不增加额外工艺流程、不牺牲器件其他性能的前提下，增加器件的栅-发射极电容CGE，降低SiC沟槽栅IGBT器件的EMI噪声，防止电路发生串扰，增强电力系统运行时的可靠性。
发明内容
本发明的目的是提出一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，通过在部分N+接触区和P+接触区上覆盖氧化层和多晶硅栅，增加栅极与发射极的重叠面积，起到增加CGE电容的作用，并且由于N+接触区和P+接触下方存在接地的Pbase区，起到屏蔽作用，不会导致米勒电容CGC的增加，进而满足不提高器件生产成本、不增加额外工艺流程、不牺牲器件其他性能的前提下，降低器件EMI噪声，防止电路发生串扰，增强电力系统运行时可靠性的要求。
为实现上述发明目的，本发明技术方案如下：
一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，包括：P型衬底10、位于P型衬底上方的N型缓冲层9、位于N型缓冲层9上方的N型漂移层8、位于N型漂移层8上方的电荷存储层CSL7、位于电荷存储层CSL7内部的P型屏蔽层Pshield6，位于电荷存储层CSL7上方的P型基区Pbase5、位于P型基区Pbase5上方的P+接触区4和N+接触区3、P型屏蔽层Pshield6上方和器件顶部都设有氧化层2，氧化层2上方设有多晶硅栅1；所述多晶硅层栅1和氧化层2覆盖P+接触区3和N+接触区4顶部的部分区域；P+接触区3和N+接触区4表面被多晶硅层栅1和氧化层2部分覆盖，集电极11位于器件下方且与P型衬底10形成欧姆接触，发射极12位于器件上方且与部分N+接触区3和P+接触区4形成欧姆接触。
作为优选方式，P+接触区3和N+接触区4表面被多晶硅层栅1和氧化层2覆盖的区域面积、与未被多晶硅层栅1和氧化层2覆盖的区域面积的比值选自1:1、2:1、1:2、3:1、1:3、4:1、1:4、5:1、1:5其中一种。可根据降低EMI噪声的需求和工艺能力采取任意大于零的比值，覆盖面积越大，降低器件EMI噪声的能力越强。
作为优选方式，在P+接触区3和N+接触区4表面上方、多晶硅层栅1下方的氧化层2的厚度，等于器件体内氧化层2的厚度。若厚度相等，器件的工艺流程更简便。
作为优选方式，在P+接触区3和N+接触区4表面上方、多晶硅层栅1下方的氧化层2的厚度，不等于器件体内氧化层2的厚度。若厚度不相等，在器件设计时可以根据需求调整CGE的大小。
作为优选方式，所述氧化层2为SiO2或高K介质。
作为优选方式，所述器件中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时N型掺杂变为P型掺杂。
作为优选方式，所述器件材料为SiC材料。
本发明还提供一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件的制备方法，包括以下步骤：
第一步：清洗外延片，在漂移区上外延生长电荷存储层CSL，并进行平坦化；如图3所示；
第二部：以氧化层为注入阻挡层，离子注入形成P型基区Pbase区、P+接触区和N+接触区；如图4所示；
第三步：刻蚀沟槽；如图5所示；
第四步：槽底离子注入形成P型屏蔽层Pshield；如图6所示；
第五步：干氧氧化生成栅氧化层；如图7所示；
第六步：淀积多晶硅并进行表面平坦化；如图8所示；
第七步：光刻图形化多晶硅和氧化层；如图9所示；
第八步：淀积场氧化层；如图10所示；
第九步：光刻通孔，淀积金属，并形成欧姆接触电极。如图11所示。
所述器件多晶硅为栅极，P型衬底端为集电极，N+接触区和P+接触区为发射极。
本发明的有益效果：通过在部分N+接触区和P+接触区上覆盖氧化层和多晶硅栅，增加栅极与发射极的重叠面积，增加器件的CGE并保持CGC不变，在不提高器件生产成本、不增加额外工艺流程、不牺牲器件其他性能的前提下，达到降低器件EMI噪声、降低IGBT模块产生的传导干扰及辐射干扰、防止电路发生串扰、增强电力系统运行时的可靠性的目的。
附图说明
图1是传统SiC沟槽栅IGBT的器件结构示意图；
图2是本发明提出的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件结构示意图；
图3是本发明实施例1的制备方法中外延生长CSL层后元胞剖面图和元胞俯视图；
图4是本发明实施例1的制备方法中离子注入形成Pbase、N+接触区和P+接触区后元胞剖面图和元胞俯视图；
图5是本发明实施例1的制备方法中刻蚀沟槽后元胞剖面图和元胞俯视图；
图6是本发明实施例1的制备方法中槽底离子注入形成Pshield区后元胞剖面图和元胞俯视图；
图7是本发明实施例1的制备方法中干氧氧化后元胞剖面图和元胞俯视图；
图8是本发明实施例1的制备方法中淀积多晶硅并进行表面平坦化后元胞剖面图和元胞俯视图；
图9是本发明实施例1的制备方法中光刻图形化多晶硅栅和氧化层后元胞剖面图和元胞俯视图；
图10是本发明实施例1的制备方法中淀积氧化硅后元胞剖面图和元胞俯视图；
图11是本发明实施例1的制备方法中光刻通孔并淀积金属形成欧姆接触后元胞剖面图和元胞俯视图。
1为多晶硅栅，2为氧化层，3为N+接触区，4为P+接触区，5为P型基区Pbase，6为P型屏蔽层Pshield，7为电荷存储层CSL，8为N型漂移层，9为N型缓冲层，10为P型衬底，11为集电极，12为发射极。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，所提出的实施例仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如图2所示，本实施例中的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，
P型衬底10、位于P型衬底上方的N型缓冲层9、位于N型缓冲层9上方的N型漂移层8、位于N型漂移层8上方的电荷存储层CSL7、位于电荷存储层CSL7内部的P型屏蔽层Pshield6，位于电荷存储层CSL7上方的P型基区Pbase5、位于P型基区Pbase5上方的P+接触区4和N+接触区3、P型屏蔽层Pshield6上方和器件顶部都设有氧化层2，氧化层2上方设有多晶硅栅1；所述多晶硅层栅1和氧化层2覆盖P+接触区3和N+接触区4顶部的部分区域；P+接触区3和N+接触区4表面被多晶硅层栅1和氧化层2部分覆盖，集电极11位于器件下方且与P型衬底10形成欧姆接触，发射极12位于器件上方且与部分N+接触区3和P+接触区4形成欧姆接触。
优选的，P+接触区3和N+接触区4表面被多晶硅层栅1和氧化层2覆盖的区域面积、与未被多晶硅层栅1和氧化层2覆盖的区域面积的比值选自1:1、2:1、1:2、3:1、1:3、4:1、1:4、5:1、1:5其中一种。可根据降低EMI噪声的需求和工艺能力采取任意大于零的比值，覆盖面积越大，降低器件EMI噪声的能力越强。
优选的，在P+接触区3和N+接触区4表面上方、多晶硅层栅1下方的氧化层2的厚度，等于器件体内氧化层2的厚度。若厚度相等，器件的工艺流程更简便。
优选的，在P+接触区3和N+接触区4表面上方、多晶硅层栅1下方的氧化层2的厚度，不等于器件体内氧化层2的厚度。若厚度不相等，在器件设计时可以根据需求调整CGE的大小。
所述氧化层2为SiO2或高K介质。
在其他实施例中，所述器件中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时N型掺杂变为P型掺杂。
所述器件材料为SiC材料或为其他半导体材料。
本发明的工作原理为：
在器件开启过程中，一方面，当器件的VGE大于器件的阈值电压VTH，SiC沟槽栅IGBT导通，此时栅极自充电效应使VGE迅速增加，导致较高的dICE/dt；另一方面，由于电路中寄生电感的存在，导致续流二极管的dVKA/dt远高于SiC沟槽栅IGBT的dVCE/dt，进而引起较大的EMI噪声。
本发明通过在部分P+欧姆接触区和N+欧姆接触区上覆盖氧化层和多晶硅栅，增加SiC沟槽栅IGBT器件的栅-发射极电容CGE，抑制栅极自充电效应，避免开启过程出现较大的dICE/dt和dVCE/dt，降低EMI噪声；同时，由于N+接触区和P+接触下方存在接地的Pbase区，起到屏蔽作用，不会导致米勒电容CGC的增加，进而防止器件开启损耗的增加。
且本发明可通过更改P+欧姆接触区和N+欧姆接触区上覆盖氧化层和多晶硅栅的面积以及氧化层的厚度，对栅-发射极电容CGE的大小进行调整。
本实施例还提供一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件的制备方法，包括以下步骤：
第一步：清洗外延片，在漂移区上外延生长电荷存储层CSL，并进行平坦化；
第二部：以氧化层为注入阻挡层，离子注入形成P型基区Pbase区、P+接触区和N+接触区；
第三步：刻蚀沟槽；
第四步：槽底离子注入形成P型屏蔽层Pshield；
第五步：干氧氧化生成栅氧化层；
第六步：淀积多晶硅并进行表面平坦化；
第七步：光刻图形化多晶硅和氧化层；
第八步：淀积场氧化层；
第九步：光刻通孔，淀积金属，并形成欧姆接触电极。
所述器件多晶硅为栅极，P型衬底端为集电极，N+接触区和P+接触区为发射极。
Claims (7)
1.一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，其特征在于包括：P型衬底(10)、位于P型衬底上方的N型缓冲层(9)、位于N型缓冲层(9)上方的N型漂移层(8)、位于N型漂移层(8)上方的电荷存储层CSL(7)、位于电荷存储层CSL(7)内部的P型屏蔽层Pshield(6)，位于电荷存储层CSL(7)上方的P型基区Pbase(5)、位于P型基区Pbase(5)上方的P+接触区(4)和N+接触区(3)、P型屏蔽层Pshield(6)上方和器件顶部都设有氧化层(2)，氧化层(2)上方设有多晶硅栅(1)；所述多晶硅层栅(1)和氧化层(2)覆盖P+接触区(3)和N+接触区(4)顶部的部分区域；P+接触区(3)和N+接触区(4)表面被多晶硅层栅(1)和氧化层(2)部分覆盖，集电极(11)位于器件下方且与P型衬底(10)形成欧姆接触，发射极(12)位于器件上方且与部分N+接触区(3)和P+接触区(4)形成欧姆接触。
2.根据权利要求1所述的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，其特征在于：P+接触区(3)和N+接触区(4)表面被多晶硅层栅(1)和氧化层(2)覆盖的区域面积、与未被多晶硅层栅(1)和氧化层(2)覆盖的区域面积的比值选自1:1、2:1、1:2、3:1、1:3、4:1、1:4、5:1、1:5其中一种。
3.根据权利要求1所述的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，其特征在于：在P+接触区(3)和N+接触区(4)表面上方、多晶硅层栅(1)下方的氧化层(2)的厚度，等于器件体内氧化层(2)的厚度。
4.根据权利要求1～3任意一项所述的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，其特征在于：所述氧化层(2)为SiO2或高K介质。
5.根据权利要求1～3任意一项所述的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，其特征在于：所述器件中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时N型掺杂变为P型掺杂。
6.根据权利要求1～5任意一项所述的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件，其特征在于：所述器件材料为SiC材料。
7.权利要求1～5任意一项所述的一种具有低电磁干扰噪声的SiC沟槽栅IGBT器件的制备方法，其特征在于包括以下步骤：
第一步：清洗外延片，在漂移区上外延生长电荷存储层CSL，并进行平坦化；
第二部：以氧化层为注入阻挡层，离子注入形成P型基区Pbase区、P+接触区和N+接触区；
第三步：刻蚀沟槽；
第四步：槽底离子注入形成P型屏蔽层Pshield；
第五步：干氧氧化生成栅氧化层；
第六步：淀积多晶硅并进行表面平坦化；
第七步：光刻图形化多晶硅和氧化层；
第八步：淀积场氧化层；
第九步：光刻通孔，淀积金属，并形成欧姆接触电极。
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