WO2024113414A1 - 基于高k介质的碳化硅沟槽型MOSFET及其制作方法 - Google Patents

基于高k介质的碳化硅沟槽型MOSFET及其制作方法 Download PDF

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WO2024113414A1
WO2024113414A1 PCT/CN2022/138638 CN2022138638W WO2024113414A1 WO 2024113414 A1 WO2024113414 A1 WO 2024113414A1 CN 2022138638 W CN2022138638 W CN 2022138638W WO 2024113414 A1 WO2024113414 A1 WO 2024113414A1
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layer
dielectric
trench
type
well
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French (fr)
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程新红
刘少煜
郑理
俞跃辉
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中国科学院上海微系统与信息技术研究所
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the technical field of semiconductors and relates to a silicon carbide trench MOSFET based on a high-k dielectric and a manufacturing method thereof.
  • silicon carbide As silicon-based devices have approached the material performance limit in the semiconductor field, silicon carbide (SiC), as a new wide-bandgap semiconductor material, is considered to have great development potential in the field of power electronics, and is widely used in both rectifiers and switch tubes.
  • SiC silicon carbide
  • switch tubes vertical power MOSFET has become the most popular academic research and industrialization object because of its wide application in DC-DC converters and three-phase inverters.
  • SiC vertical power MOSFETs are divided into planar gate type and trench gate type MOSFETs according to different gate structures.
  • Figure 1 shows a schematic diagram of the cross-sectional structure of a conventional planar gate type MOSFET. Due to the presence of a JFET region under the gate oxide layer 101 of the planar gate structure, it is difficult to reduce the on-resistance within the range of medium and low voltage (650V-3300V) devices, and the area utilization is insufficient. In view of the disadvantages of the planar gate structure, research and development in this field has gradually shifted to the trench gate structure. As the name suggests, please refer to Figure 2, which shows a schematic diagram of the cross-sectional structure of a trench gate type MOSFET.
  • the trench gate refers to a trench 102 pre-prepared at the gate structure of the MOSFET, and the gate oxide layer 101 is subsequently prepared by thermal oxidation or thin film deposition.
  • the trench gate structure improves the area utilization of the device and reduces the specific contact resistance, the silicon carbide trench preparation process is still not mature, and there are very few manufacturers that can achieve both yield and performance. Therefore, except for a few companies that have achieved industrialization, most manufacturers' trench silicon carbide MOSFET research and development is still at the laboratory sample stage.
  • the trench gate structure also has some disadvantages in principle, such as the electric field concentration of the gate oxide layer at the corner of the device trench during reverse withstand voltage, and the difficulty in controlling the quality of the gate oxide on the trench sidewall.
  • the object of the present invention is to provide a silicon carbide trench MOSFET based on high-k dielectric and a method for manufacturing the same, so as to solve the problems in the prior art of electric field concentration in the gate oxide layer at the trench corners of the trench gate structure during reverse withstand voltage and difficulty in controlling the quality of the gate oxide on the trench sidewalls.
  • the present invention provides a method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric, comprising the following steps:
  • N-type source region is located on the upper surface layer of the P-well, and at least a portion of the P-type body contact region is located in the P-well and adjacent to the N-type source region in a horizontal direction;
  • the high-k dielectric layer covers the inner wall and bottom surface of the trench and extends to a portion of the upper surface of the N-type source region;
  • Source ohmic contact layer Forming a source ohmic contact layer on the upper surface of the P-type body contact region, wherein the source ohmic contact layer also extends to the upper surface of the N-type source region and is adjacent to the high-k dielectric layer;
  • a source metal layer is formed, wherein the source metal layer covers the source ohmic contact layer and the gate electrode layer.
  • the sacrificial oxide layer is removed.
  • a trench surface pretreatment step is further included, and the pretreatment method includes at least one of oxygen plasma surface treatment and ammonia plasma surface treatment.
  • the method further includes a step of planarizing the gate electrode layer, and the method of planarizing the gate electrode layer includes at least one of chemical mechanical polishing and back etching.
  • a step of forming a field oxide layer is further included, wherein the field oxide layer covers the trench and a portion of the source region.
  • the bottom surface of the P-type body contact region is higher than the bottom surface of the P-well, or the bottom surface of the P-type body contact region is lower than the bottom surface of the P-well; or the bottom surface of the P-type body contact region is flush with the bottom surface of the P-well.
  • the P-type body contact region is continuous or discontinuous.
  • the gate electrode layer is a polysilicon layer; or, the gate electrode layer is a metal layer, and a material of the metal layer includes at least one of TiN and TaN.
  • the thickness of the epitaxial layer is in the range of 6 ⁇ m to 50 ⁇ m
  • the doping concentration of the epitaxial layer is in the range of 1 ⁇ 10 13 cm -3 to 1 ⁇ 10 17 cm -3
  • the doping type of the epitaxial layer includes N-type doping
  • the doping ions of the epitaxial layer include nitrogen ions.
  • the high-k dielectric layer includes at least one of an AlSiO layer, a HfAlO layer, a SiO2/Al2O3 composite layer and a SiO2/HfO2 composite layer.
  • the present invention also provides a high-k dielectric-based silicon carbide trench MOSFET, comprising:
  • a substrate an epitaxial layer being formed on an upper surface of the substrate
  • a P well located on the upper surface of the epitaxial layer
  • N-type source region and a P-type body contact region wherein the N-type source region is located on the upper surface layer of the P-well, and at least a portion of the P-type body contact region is located in the P-well and adjacent to the N-type source region in a horizontal direction;
  • a high-k dielectric layer covering the inner wall and bottom surface of the trench and extending to a portion of the upper surface of the N-type source region;
  • a gate electrode layer located in the trench
  • a source ohmic contact layer located on the upper surface of the P-type body contact region, and the source ohmic contact layer also extends to the upper surface of the N-type source region and is adjacent to the high-k dielectric layer;
  • a source metal layer covers the source ohmic contact layer and the gate electrode layer.
  • the high-k dielectric layer includes at least one of an AlSiO layer, a HfAlO layer, a SiO 2 /Al 2 O 3 composite layer and a SiO 2 /HfO 2 composite layer.
  • the bottom surface of the P-type body contact region is higher than the bottom surface of the P-well, or the bottom surface of the P-type body contact region is lower than the bottom surface of the P-well; or the bottom surface of the P-type body contact region is flush with the bottom surface of the P-well.
  • the P-type body contact region is continuous or discontinuous.
  • the silicon carbide trench MOSFET based on high-k dielectric of the present invention and the manufacturing method thereof include the following steps: providing a substrate, an epitaxial layer is formed on the upper surface of which; forming a P well in the epitaxial layer; forming an N-type source region and a P-type body contact region based on the P well, the N-type source region is located between two adjacent P-type body contact regions in the first horizontal direction, and the N-type source region is located in the P well; forming a groove based on the N-type source region, the groove runs through the N-type source region and the P well; depositing a high-k dielectric layer in the groove, the high-k dielectric layer also covering a portion of the upper surface of the N-type source region; forming a gate electrode layer in the groove; forming a source ohmic contact layer on the upper surface of the P-type body contact region, the source ohmic contact layer also covering a portion of the surface of the N-type source region and connecting
  • the manufacturing method of the present invention mainly adopts a high-K dielectric with a large dielectric constant and uniform and stable growth as a gate dielectric layer, effectively improving the problems of electric field concentration of the gate oxide layer at the trench corner of the traditional trench MOSFET device during reverse withstand voltage and difficulty in controlling the quality of the gate oxide layer on the trench side wall, thereby improving the performance of the device and having a simple manufacturing method, which can achieve large-scale production.
  • FIG. 1 is a schematic diagram showing a cross-sectional structure of a conventional planar MOSFET.
  • FIG. 2 is a schematic diagram showing a cross-sectional structure of a conventional trench MOSFET.
  • FIG. 3 is a flow chart showing the steps of a method for manufacturing a high-k dielectric silicon carbide trench MOSFET according to the present invention.
  • FIG. 4 is a schematic cross-sectional view of a structure obtained after executing step S1 in the method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric of the present invention.
  • FIG. 5 is a schematic cross-sectional view of a structure obtained after executing step S2 in the method for manufacturing a high-k dielectric silicon carbide trench MOSFET according to the present invention.
  • FIG. 6 is a schematic cross-sectional view of a structure obtained after executing step S3 in the method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a structure obtained after executing step S4 in the method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric of the present invention.
  • FIG. 8 is a schematic cross-sectional view of a structure obtained after executing step S5 in the method for manufacturing a high-k dielectric silicon carbide trench MOSFET according to the present invention.
  • FIG. 9 is a schematic cross-sectional view of a structure obtained after executing step S6 in the method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a structure obtained after forming a poplar oxide layer in the method for manufacturing a silicon carbide trench MOSFET based on a high-K dielectric of the present invention.
  • FIG. 11 is a schematic cross-sectional view of a structure obtained after executing step S7 in the method for manufacturing a high-k dielectric silicon carbide trench MOSFET according to the present invention.
  • FIG. 12 is a schematic cross-sectional view of a structure obtained after executing step S8 in the method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric of the present invention.
  • FIG. 13 is a schematic diagram showing the three-dimensional structure of a high-k dielectric silicon carbide trench MOSFET in Example 2 of the present invention.
  • FIG. 14 is a schematic diagram showing the three-dimensional structure of a high-k dielectric silicon carbide trench MOSFET in Example 3 of the present invention.
  • FIG. 15 is a schematic three-dimensional structure diagram of a partial structure in FIG. 14 .
  • FIG. 16 is a schematic top view of the structure shown in FIG. 15 .
  • FIG. 17 is a schematic diagram showing a partial cross-sectional structure of two adjacent silicon carbide trench MOSFETs based on high-k dielectric in Embodiment 3.
  • FIG. 17 is a schematic diagram showing a partial cross-sectional structure of two adjacent silicon carbide trench MOSFETs based on high-k dielectric in Embodiment 3.
  • This embodiment provides a method for manufacturing a high-k dielectric silicon carbide trench 6-type MOSFET. Please refer to FIG. 3 , which is a flowchart of the steps of the manufacturing method of this embodiment, including the following steps:
  • S3 forming an N-type source region and a P-type body contact region, wherein the N-type source region is located on the upper surface layer of the P-well, and at least a portion of the P-type body contact region is located in the P-well and adjacent to the N-type source region in a horizontal direction;
  • S7 forming a source ohmic contact layer on the upper surface of the P-type body contact region, wherein the source ohmic contact layer further extends to the upper surface of the N-type source region and is adjacent to the high-k dielectric layer;
  • step S1 is performed to provide a substrate, wherein an epitaxial layer is formed on the upper surface of the substrate 1.
  • the substrate is located on a wafer, and the surface where the epitaxial layer 2 is located is the front side of the wafer. Subsequent steps are performed on the front side of the wafer.
  • the substrate 1 is an N-type doped silicon carbide substrate 1.
  • the material of the epitaxial layer 2 is silicon carbide
  • the thickness of the epitaxial layer 2 ranges from 6 ⁇ m to 50 ⁇ m
  • the doping concentration of the epitaxial layer 2 ranges from 1 ⁇ 10 13 cm -3 to 1 ⁇ 10 17 cm -3
  • the doping type of the epitaxial layer 2 includes N-type doping
  • the doping ions of the epitaxial layer 2 include nitrogen ions.
  • the manufacturing method of this embodiment further includes a cleaning step, which is performed before forming the P well 3.
  • the cleaning method includes an RCA standard cleaning method, and the cleaning liquid used includes H 2 SO 4 +H 2 O 2 , HF (buffered oxide etchant) and deionized water, etc.
  • the purpose of cleaning is to remove impurities that may exist on the surface of the wafer and improve the yield, performance and reliability of the device.
  • step S2 execute step S2 to form a P well 3 on the upper surface of the epitaxial layer 2.
  • the method for forming the P well 3 includes ion implantation.
  • the ion implantation to form the P well 3 can be performed under high temperature or room temperature conditions. Under room temperature conditions, photoresist is used as a mask, while under high temperature conditions, SiO2 or SiNx needs to be used as a hard mask to achieve patterning.
  • step S3 is performed to form an N-type source region and a P-type body contact region, wherein the N-type source region 5 is located on the upper surface layer of the P-well 3, and at least a portion of the P-type body contact region 4 is located in the P-well 3 and is adjacent to the N-type source region 5 in the horizontal direction.
  • the method for forming the P-type body contact region 4 and the N-type source region 5 includes an ion implantation method, wherein the ion implantation to form the P-type body contact region 4 is performed under high temperature conditions, ranging from 450° C.
  • the ion implantation to form the N-type source region 5 is performed under the same conditions as the conditions for forming the P-well 3, that is, it can be performed under high temperature or room temperature conditions, and in addition, the implantation angle range when the ion implantation to form the P-well 3, the P-type body contact region 4 and the N-type source region 5 includes 0° to 7°.
  • the temperature for forming the P-type body contact region 4 is 500° C.
  • a first annealing step is performed, the time range of the first annealing step is 60min to 120min, including but not limited to 80min and 100min, the temperature range of the first annealing step is 1600°C to 1800°C, including but not limited to 1650°C and 1750°C, the purpose of the first annealing step is high-temperature activation, and the specific steps are: after covering the front and back sides of the wafer with a carbon film, placing the wafer under 1600°C to 1800°C conditions, annealing for 60min to 120min, removing the carbon film, and cleaning the front and back sides of the wafer.
  • the bottom surface of the P-type body contact region 4 is higher than the bottom surface of the P-well 3, or the bottom surface of the P-type body contact region 4 is lower than the bottom surface of the P-well 3; or the bottom surface of the P-type body contact region 4 is flush with the bottom surface of the P-well 3.
  • the depth of the P-type body contact region 4 is selected based on actual needs.
  • the P-type body contact region 4 is formed by deep P-type ion implantation, that is, by controlling the process parameters during ion implantation, the depth of the P-type body contact region 4 is greater so as to achieve a better shielding effect on the dielectric electric field at the bottom of the trench 6.
  • the doping ions of the P-well 3 and the P-type body contact region 4 include aluminum ions
  • the doping ions of the N-type source region 5 include nitrogen ions.
  • the P-type body contact region 4 is continuous or discontinuous.
  • the P-type body contact region 4 is continuous in the extension direction of the trench 6, which is a continuous type, and the P-type body contact region 4 is separated by the N-type source region 5 and the P-well 3 in the extension direction of the trench 6, which is a discontinuous type.
  • a trench is formed.
  • the trench 6 penetrates the N-type source region 5 and the P-well 3 , and extends downward into the epitaxial layer 2 .
  • step S5 is performed to form a high-k dielectric layer.
  • the high-k dielectric layer 7 covers the inner wall and bottom surface of the trench 6 and extends to a portion of the upper surface of the N-type source region 5 .
  • the following steps are also included: rounding the bottom of the groove 6; forming a sacrificial oxide layer (not shown in the figure) on the sidewall and bottom of the groove 6 by thermal oxidation; and removing the sacrificial oxide layer.
  • the angle between the side and bottom of the groove 6 is a right angle, and the surface of the groove 6 after etching is relatively rough, which is not conducive to the subsequent bonding of the high-k dielectric layer 7 deposited with the surface of the groove 6.
  • the above two steps can make the rough surface of the groove 6 smooth and flat, which is conducive to reducing the interface state of the high-k dielectric/silicon carbide substrate 1 interface.
  • a surface pretreatment step of the groove 6 is also included.
  • the pretreatment method includes at least one of oxygen plasma surface treatment and ammonia plasma surface treatment. The above two methods are used for the pretreatment step in this embodiment.
  • the purpose of the pretreatment step is to clean and passivate the bottom surface and side walls of the groove 6, change the dangling bond state on its surface, and be more conducive to the uniformity and reliability of the subsequent dielectric.
  • the oxygen plasma surface treatment is used to clean surface impurities, and the ammonia plasma surface treatment can passivate the dielectric surface and change the dangling bond distribution on the silicon nitride surface, so that the H dangling bonds are conducive to the subsequent dielectric film formation and avoid uneven dielectric deposition caused by excessive island aggregation.
  • the method of depositing the high-k dielectric layer 7 includes chemical vapor deposition and atomic layer deposition.
  • the high-k dielectric layer 7 is deposited by atomic layer deposition. Since the high-k dielectric layer 7 is applied to the trench 6-gate MOSFET, the uniformity of the dielectric is required to be relatively strict, and the use of chemical vapor deposition may not achieve a more ideal effect.
  • the material types of the high-k dielectric layer 7 include aluminum-based and hafnium-based high-k dielectrics.
  • the dielectric constants of pure Al 2 O 3 and HfO 2 are 9-10 and 17-25, respectively, and the bandgap widths are 8.7eV-8.8eV and 6eV-7eV, respectively.
  • their dielectric constants are compared with SiO 2 (dielectric constant is 3.9), which can greatly reduce the electric field strength on the dielectric side at the corner of the groove 6.
  • the high-k dielectric layer 7 includes at least one of an AlSiO layer, an HfAlO layer, a SiO 2 /Al 2 O 3 composite layer, and a SiO 2 /HfO 2 composite layer.
  • silicon oxide is not a high-k dielectric
  • the addition of silicon will help balance the bandgap deviation between the dielectric/silicon carbide and reduce leakage current. Although this behavior will also reduce the dielectric constants of aluminum-based and hafnium-based dielectrics, it will eventually be higher than pure SiO 2 and will not affect its withstand voltage and electric field capabilities.
  • a second annealing step is performed.
  • the time range of the second annealing step is 30s to 3min, including but not limited to 1min and 2min.
  • the temperature range of the second annealing step is 550°C to 900°C, including but not limited to 650°C and 800°C.
  • the function of the second annealing step is to make the layered structure formed by the deposited high-k dielectric material eventually form a gate dielectric layer.
  • the gate electrode layer 8 includes at least one of a polysilicon layer and a metal layer.
  • the material of the metal layer includes at least one of TiN and TaN.
  • the steps of forming the polysilicon layer are as follows: depositing polysilicon on the front side of the wafer and filling the entire groove 6, and after the deposition is completed, using a back etching method to etch all the subsequent portions of the gate electrode layer 8 that contact the outside of the through hole, and the polysilicon in the entire groove 6 is concave (not shown in the figure).
  • a step of planarizing the gate electrode layer 8 is also included.
  • the method of planarizing the gate electrode layer 8 includes at least one of chemical mechanical polishing (CMP) and etch-back.
  • CMP is used to planarize the gate electrode layer 8 to improve the interface state of the gate electrode layer 8.
  • a step of forming a field oxide layer 9 is also included.
  • FIG. 10 shows a cross-sectional schematic diagram of the structure obtained after the field oxide layer is formed.
  • the field oxide layer 9 covers the groove 6 and a portion of the source region.
  • the specific steps are to deposit the field oxide layer 9 on the front side of the wafer, and after the deposition is completed, the field oxide layer on the surface of the active region is removed by selective etching by photolithography, so as to expose the N-type source region 5 and the P-type body contact region 4, so as to facilitate the subsequent formation of the source ohmic contact layer 10 in this region.
  • a thin oxide layer is deposited as a pre-protective layer for the gate electrode layer 8 , and is prepared by thermal oxidation of polysilicon, thereby further improving the protective effect on the gate electrode layer 8 .
  • step S7 is performed to form a source ohmic contact layer 10 on the upper surface of the P-type body contact region 4 .
  • the source ohmic contact layer 10 also extends to the upper surface of the N-type source region 5 and is adjacent to the high-k dielectric layer 7 .
  • the method for forming the source ohmic contact layer 10 includes depositing Ni, Al, Ti stacked metal or alloy on the front side of the wafer by sputtering or electron beam evaporation, and patterning by lift-off process. Subsequently, high temperature annealing at 850°C to 1000°C is used to realize the ohmic contact area.
  • the high temperature annealing step here is the third annealing step, and the specific temperature includes but is not limited to 900°C and 950°C.
  • step S8 is performed to form a source metal layer 11, wherein the source metal layer 11 covers the source ohmic contact layer 10 and the gate electrode layer 8.
  • Forming the source metal layer 11 includes depositing a metal material on the front side of the wafer and patterning the metal material by etching.
  • the material of the source metal layer 11 includes at least one of Al, Ti and Ag.
  • all the process steps described above are processes performed on the front side of the wafer, and similar processes are also required on the back side of the wafer to form structures such as the drain ohmic contact metal layer and the drain metal layer.
  • the method for manufacturing a silicon carbide trench MOSFET based on a high-k dielectric in this embodiment mainly uses a high-k dielectric with a large dielectric constant and uniform and stable growth material properties as a gate dielectric layer, which effectively improves the problems of electric field concentration in the gate oxide layer at the trench corners of traditional trench MOSFET devices during reverse withstand voltage and difficulty in controlling the maintenance quality of the trench sidewalls, improves the performance of the device, and the manufacturing method is simple, which can achieve large-scale production.
  • the present embodiment provides a silicon carbide trench MOSFET based on a high-k dielectric, which is prepared based on the method in the first embodiment or other suitable methods.
  • FIG13 is a schematic diagram of the three-dimensional structure of the MOSFET of the present embodiment (only half is shown), specifically including a substrate 1, an epitaxial layer 2, a P-well 3, a P-type body contact region 4, an N-type source region 5, a trench 6 (not marked), a high-k dielectric layer 7, a gate electrode layer 8, a source ohmic contact layer 10 and a source metal layer 11, wherein an epitaxial layer 2 is formed on the upper surface of the substrate 1; the P-well 3 is located on the upper surface layer of the epitaxial layer 2; the N-type source region 5 is located on the upper surface layer of the P-well 3, and the P-type body contact At least a portion of the contact area 4 is located in the P-well 3 and is adjacent to the N-type source area 5 in the horizontal direction; the groove 6 penetrates the N
  • the MOSFET also includes a field oxide layer 9, which covers the groove 6 (not marked) and a portion of the source region.
  • the field oxide layer 9 is located on the exposed surfaces of the gate dielectric layer 7 and the gate electrode layer 8.
  • the high-k dielectric layer 7 includes at least one of an AlSiO layer, a HfAlO layer, a SiO 2 /Al 2 O 3 composite layer and a SiO 2 /HfO 2 composite layer.
  • the bottom surface of the P-type body contact region 4 is higher than the bottom surface of the P-well 3, or the bottom surface of the P-type body contact region 4 is lower than the bottom surface of the P-well 3; or the bottom surface of the P-type body contact region 4 is flush with the bottom surface of the P-well 3. In this embodiment, the bottom surface of the P-type body contact region 4 is higher than the bottom surface of the P-well 3.
  • the P-type body contact region 4 is continuous or discontinuous.
  • the P-type body contact region 4 is continuous in the extension direction of the groove 6, which is a continuous type, and the P-type body contact region 4 is separated by the N-type source region 5 and the P-well 3 in the extension direction of the groove 6, which is a discontinuous type.
  • the P-type body contact region 4 includes a continuous type. In order to ensure that the P-type body contact region 4 has a better shielding effect on the dielectric electric field on the bottom surface of the groove 6, a continuous P-type body contact region 4 is required.
  • the high-k dielectric-based silicon carbide trench MOSFET of this embodiment can effectively improve the problems of electric field concentration in the gate oxide layer at the trench corners of traditional trench MOSFET devices during reverse withstand voltage and the difficulty in controlling the quality of trench sidewall maintenance, thereby improving device performance.
  • the present embodiment provides a silicon carbide trench 6-type MOSFET based on a high-k dielectric, which is prepared based on the method in the first embodiment or other suitable methods.
  • FIG. 14 is a schematic diagram of the three-dimensional structure of the MOSFET of the present embodiment (only half is shown), specifically including a substrate 1, an epitaxial layer 2, a P-well 3, a P-type body contact region 4, an N-type source region 5, a trench 6 (not marked), a high-k dielectric layer 7, a gate electrode layer 8, a source ohmic contact layer 10 and a source metal layer 11, wherein an epitaxial layer 2 is formed on the upper surface of the substrate 1; the P-well 3 is located on the upper surface layer of the epitaxial layer 2; the N-type source region 5 is located on the upper surface layer of the P-well 3, and the P-type body contact At least a portion of the contact area 4 is located in the P-well 3 and is adjacent to the N-type source area 5 in the horizontal direction; the groove 6 penetrates
  • the MOSFET also includes a field oxide layer 9, which covers the groove 6 (not marked) and a portion of the source region.
  • the field oxide layer 9 is located on the exposed surfaces of the gate dielectric layer 7 and the gate electrode layer 8.
  • the high-k dielectric layer 7 includes at least one of an AlSiO layer, a HfAlO layer, a SiO 2 /Al 2 O 3 composite layer and a SiO 2 /HfO 2 composite layer.
  • the bottom surface of the P-type body contact region 4 is higher than the bottom surface of the P-well 3, or the bottom surface of the P-type body contact region 4 is lower than the bottom surface of the P-well 3; or the bottom surface of the P-type body contact region 4 is flush with the bottom surface of the P-well 3. In this embodiment, the bottom surface of the P-type body contact region 4 is lower than the bottom surface of the P-well 3.
  • the P-type body contact region 4 is continuous or discontinuous.
  • the P-type body contact region 4 is continuous in the extension direction of the trench 6, which is a continuous type, and the P-type body contact region 4 is separated by the N-type source region 5 and the P-well 3 in the extension direction of the trench 6, which is a discontinuous type.
  • the P-type body contact region 4 is a discontinuous type.
  • a discontinuous P-type body contact region 4 design can also achieve a better shielding effect.
  • Figure 15 shows a three-dimensional structural schematic diagram of the local structure of the MOSFET of this embodiment
  • Figure 16 shows a top view of the structure shown in Figure 15.
  • the discontinuous P-type body contact region 4 design means that the P well 3 and the N-type source region 5 are completely connected, and the P-type body contact region 4 is designed to be a rectangular discontinuous shape.
  • Figure 17 is a top-down schematic diagram of two adjacent cells.
  • the N-type source regions 5 of cell A and cell B are connected, and there is no need to consider additional spacing. It is only necessary to ensure that there is sufficient contact area with the ohmic contact area. Therefore, the size of the device cell can be further reduced. Under the premise of ensuring the electric field strength of the groove 6, the area utilization rate and energy density are improved, which is beneficial to improving the device performance.
  • the high-k dielectric-based silicon carbide trench MOSFET of this embodiment can effectively improve the problems of electric field concentration in the gate oxide layer at the trench corners of traditional trench MOSFET devices during reverse withstand voltage and difficulty in controlling the quality of the gate oxide layer on the trench sidewalls, thereby improving device performance.
  • the silicon carbide trench MOSFET based on high-k dielectric of the present invention and the manufacturing method thereof include the following steps: providing a substrate, wherein an epitaxial layer is formed on the upper surface of the substrate; forming a P-well on the upper surface of the epitaxial layer; forming an N-type source region and a P-type body contact region, wherein the N-type source region is located on the upper surface of the P-well, and at least a portion of the P-type body contact region is located in the P-well and is adjacent to the N-type source region in the horizontal direction; forming a groove, wherein the groove penetrates the N-type source region and the P-well and extends downward into the epitaxial layer; forming a high-k dielectric layer, wherein the high-k dielectric layer covers the inner wall and the bottom surface of the groove and extends to a portion of the upper surface of the N-type source region; forming a gate electrode layer in the groove; forming a source ohmic contact layer on the following steps
  • the manufacturing method of the present invention mainly adopts a high-k dielectric material with a large dielectric constant and uniform and stable growth as a gate dielectric layer, effectively improving the problems of electric field concentration of the gate oxide layer at the corner of the trench of the traditional trench MOSFET device during reverse withstand voltage and the difficulty in controlling the quality of the gate oxide on the side wall of the trench, improving the performance of the device, and the manufacturing method is simple, and large-scale production can be achieved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

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Abstract

本发明提供一种基于高k介质的碳化硅沟槽型MOSFET及其制作方法，包括：提供一衬底，其上表面形成有外延层；形成P阱于外延层的上表层；形成位于P阱的上表层的N型源区及至少一部分位于P阱中并与N型源区在水平方向上邻接的P型体接触区；形成沟槽；形成高k介质层覆盖沟槽内壁与底面并延伸至N型源区的部分上表面；形成栅电极层于沟槽中；形成源极欧姆接触层于P型体接触区的上表面还延伸至N型源区的上表面与高k介质层邻接；形成覆盖源极欧姆接触层与栅电极层的源极金属层。本发明的制作方法能够有效改善沟槽型MOSFET器件的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁栅氧层质量难以控制的问题，提高器件的性能。

Description

基于高k介质的碳化硅沟槽型MOSFET及其制作方法 技术领域
本发明属于半导体技术领域，涉及一种基于高k介质的碳化硅沟槽型MOSFET及其制作方法。
背景技术
由于硅基器件在半导体领域已经逼近材料性能极限，碳化硅(SiC)作为一种新型宽禁带半导体材料，被认为在电力电子领域有着巨大的发展潜力，不论是整流器还是开关管都有着广泛应用。在开关管中，垂直型功率MOSFET因为在DC-DC变换器，三相逆变器中的广泛应用，成为了目前最为热门的学术研究及产业化对象。
目前SiC垂直功率MOSFET按照栅结构的不同区分为平面栅型和沟槽栅型MOSFET。请参阅图1，显示为常规平面栅型MOSFET剖面结构示意图，由于平面栅结构的栅氧层101下方存在JFET区，中低压(650V-3300V)器件范围内导通电阻难以降低，面积利用率不足。针对平面栅结构的劣势，本领域的研发逐渐向着沟槽栅结构转移，顾名思义，请参阅图2，显示为沟槽栅型MOSFET剖面结构示意图，沟槽栅指MOSFET的栅结构处预先制备一个沟槽102，后续通过热氧化或薄膜沉积的方式制备栅氧化层101。沟槽栅结构虽然提升了器件的面积利用率，降低了比接触电阻，但由于碳化硅沟槽制备工艺仍不算成熟，能够实现良率性能兼顾的制造厂家十分稀少，所以基本除少数公司实现产业化，大多数厂家的沟槽碳化硅MOSFET研发仍停留在实验室样管阶段。除了工艺问题外，沟槽栅结构在原理上也存在一些弊端，如器件沟槽拐角处栅氧层在反向耐压时电场集中、沟槽侧壁栅氧质量难以控制等。
因此，如何提供一种基于高k介质的碳化硅沟槽型MOSFET及其制作方法，以实现有效改善沟槽栅结构的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁栅氧质量难以控制等问题，成为本领域技术人员亟待解决的一个重要技术问题。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于高k介质的碳化硅沟槽型MOSFET及其制作方法，用于解决现有技术中沟槽栅结构的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁栅氧质量难以控制的问题。
为实现上述目的及其他相关目的，本发明提供一种基于高k介质的碳化硅沟槽型MOSFET的制作方法，包括以下步骤：
提供一衬底，所述衬底的上表面形成有外延层；
形成P阱于所述外延层的上表层；
形成N型源区及P型体接触区，所述N型源区位于所述P阱的上表层，所述P型体接触区的至少一部分位于所述P阱中并与所述N型源区在水平方向上邻接；
形成沟槽，所述沟槽贯穿所述N型源区及所述P阱，并向下延伸进所述外延层中；
形成高k介质层，所述高k介质层覆盖所述沟槽的内壁与底面，并延伸至所述N型源区的部分上表面；
形成栅电极层于所述沟槽中；
形成源极欧姆接触层于所述P型体接触区的上表面，所述源极欧姆接触层还延伸至所述N型源区的上表面与所述高k介质层邻接；
形成源极金属层，所述源极金属层覆盖所述源极欧姆接触层与所述栅电极层。
可选地，在形成所述高k介质层之前，还包括以下步骤：
对所述沟槽的底部进行圆角化处理；
通过热氧化法在所述沟槽的侧壁与底面形成牺牲氧化层；
去除所述牺牲氧化层。
可选地，在形成所述高k介质层之前，还包括沟槽表面预处理步骤，所述预处理的方法包括氧等离子体表面处理及氨等离子体表面处理中的至少一种。
可选地，在形成所述栅电极层后，还包括平坦化所述栅电极层的步骤，所述平坦化所述栅电极层的方法包括化学机械抛光及回刻蚀中的至少一种。
可选地，在形成所述源极欧姆接触层之前，还包括形成场氧化层的步骤，所述场氧化层遮盖所述沟槽，并遮盖所述源区的一部分。
可选地，所述P型体接触区的底面高于所述P阱的底面，或者所述P型体接触区的底面低于所述P阱的底面；或者所述P型体接触区的底面齐平于所述P阱的底面。
可选地，在所述沟槽的水平延伸方向上，所述P型体接触区为连续型或间断型。
可选地，所述栅电极层为多晶硅层；或者，所述栅电极层为金属层，所述金属层的材料包括TiN及TaN中的至少一种。
可选地，所述外延层的厚度范围是6μm～50μm，所述外延层的掺杂浓度范围是1×10 13cm -3～1×10 17cm -3，所述外延层的掺杂类型包括N型掺杂，所述外延层的掺杂离子包括氮离子。
可选地，所述高k介质层包括AlSiO层、HfAlO层、SiO2/Al2O3复合层及SiO2/HfO2复 合层中的至少一种。
本发明还提供一种基于高k介质的碳化硅沟槽型MOSFET，包括：
衬底，所述衬底的上表面形成有外延层；
P阱，位于所述外延层的上表层；
N型源区及P型体接触区，所述N型源区位于所述P阱的上表层，所述P型体接触区的至少一部分位于所述P阱中并与所述N型源区在水平方向上邻接；
沟槽，所述沟槽贯穿所述N型源区及所述P阱，并向下延伸进所述外延层中；
高k介质层，覆盖所述沟槽的内壁与底面，并延伸至所述N型源区的部分上表面；
栅电极层，位于所述沟槽中；
源极欧姆接触层，位于所述P型体接触区的上表面，所述源极欧姆接触层还延伸至所述N型源区的上表面与所述高k介质层邻接；
源极金属层，覆盖所述源极欧姆接触层与所述栅电极层。
可选地，所述高k介质层包括AlSiO层、HfAlO层、SiO 2/Al 2O 3复合层及SiO 2/HfO 2复合层中的至少一种。
可选地，所述P型体接触区的底面高于所述P阱的底面，或者所述P型体接触区的底面低于所述P阱的底面；或者所述P型体接触区的底面齐平于所述P阱的底面。
可选地，在所述沟槽的水平延伸方向上，所述P型体接触区为连续型或间断型。
如上所述，本发明的基于高k介质的碳化硅沟槽型MOSFET及其制作方法，包括以下步骤：提供一衬底，其上表面形成有外延层；形成P阱于外延层；基于P阱形成N型源区及P型体接触区，N型源区在第一水平方向上位于相邻两P型体接触区之间，N型源区位于P阱中；基于N型源区形成沟槽，沟槽贯穿N型源区及P阱；沉积高k介质层于沟槽，高k介质层还覆盖部分N型源区的上表面；形成栅电极层于沟槽中；形成源极欧姆接触层于P型体接触区的上表面，源极欧姆接触层还覆盖部分N型源区的表面与高k介质层连接；沉积源极金属层，源极金属层覆盖源极欧姆接触层与栅电极层。本发明的制作方法主要采用介电常数大及生长均匀稳定的材料特性材料的高K介质作为栅介质层，有效改善传统沟槽型MOSFET器件的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁栅氧层质量难以控制的问题，提高器件的性能并且制作方法简单，能够实现大规模生产。
附图说明
图1显示为常规平面型MOSFET的剖面结构示意图。
图2显示为常规沟槽型MOSFET的剖面结构示意图。
图3显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法步骤流程图。
图4显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S1后所得结构的剖面示意图。
图5显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S2后所得结构的剖面示意图。
图6显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S3后所得结构的剖面示意图。
图7显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S4后所得结构的剖面示意图。
图8显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S5后所得结构的剖面示意图。
图9显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S6后所得结构的剖面示意图。
图10显示为本发明的基于高K介质的碳化硅沟槽型MOSFET的制作方法中形成杨氧化层后所得结构的剖面示意图。
图11显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S7后所得结构的剖面示意图。
图12显示为本发明的基于高k介质的碳化硅沟槽型MOSFET的制作方法中执行步骤S8后所得结构的剖面示意图。
图13显示为本发明的基于高k介质的碳化硅沟槽型MOSFET于实施例二中的立体结构示意图。
图14显示为本发明的基于高k介质的碳化硅沟槽型MOSFET于实施例三中的立体结构示意图。
图15显示为图14中局部结构的立体结构示意图。
图16显示为图15所示结构的俯视示意图。
图17显示为相邻两个实施例三中基于高k介质的碳化硅沟槽型MOSFET局部结构剖面示意图。
元件标号说明
101                   栅氧层
102                   沟槽
1                     衬底
2                      外延层
3                      P阱
4                      P型体接触区
5                      N型源区
6                      沟槽
7                      高k介质层
8                      栅电极层
9                      场氧化层
10                     源极欧姆接触层
11                     源极金属层
S1～S8                 步骤
A、B                   元胞
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图3至图17。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本实施例提供一种基于高k介质的碳化硅沟槽6型MOSFET的制作方法，请参阅图3，显示为本实施例的制作方法的步骤流程图，包括以下步骤：
S1：提供一衬底，所述衬底的上表面形成有外延层；
S2：形成P阱于所述外延层的上表层；
S3：形成N型源区及P型体接触区，所述N型源区位于所述P阱的上表层，所述P型体接触区的至少一部分位于所述P阱中并与所述N型源区在水平方向上邻接；
S4：形成沟槽，所述沟槽贯穿所述N型源区及所述P阱，并向下延伸进所述外延层2中；
S5：形成高k介质层，所述高k介质层覆盖所述沟槽的内壁与底面，并延伸至所述N型 源区的部分上表面；
S6：形成栅电极层于所述沟槽中；
S7：形成源极欧姆接触层于所述P型体接触区的上表面，所述源极欧姆接触层还延伸至所述N型源区的上表面与所述高k介质层邻接；
S8：形成源极金属层，所述源极金属层覆盖所述源极欧姆接触层与所述栅电极层8。
首先，请参阅图4，执行步骤S1，提供一衬底，所述衬底1的上表面形成有外延层。所述衬底位于晶圆上，所述外延层2所在的面为晶圆的正面，后续步骤均于晶圆正面进行。本实施例中所述衬底1为N型掺杂碳化硅衬底1。
作为示例，所述外延层2的材料为碳化硅，所述外延层2的厚度范围是6μm～50μm，所述外延层2的掺杂浓度范围是1×10 13cm -3～1×10 17cm -3，所述外延层2的掺杂类型包括N型掺杂，所述外延层2的掺杂离子包括氮离子。
作为示例，本实施例的制作方法还包括清洗步骤，所述清洗步骤在形成所述P阱3前进行，清洗方法包括RCA标准清洗方法，采用的清洗液包括H 2SO 4+H 2O 2、HF(缓冲氧化物刻蚀液)以及去离子水等。清洗的目的是为了去除晶圆表面可能存在的杂质污染，提高器件的成品率、性能和可靠性。
请参阅图5，执行步骤S2，形成P阱3于所述外延层2的上表层，形成所述P阱3的方法包括离子注入法，离子注入形成所述P阱3可在高温或常温条件下进行，常温条件下使用光刻胶作为掩膜，而高温条件下需要采用SiO 2或SiN x作为硬掩膜实现图形化。
请参阅图6，执行步骤S3，形成N型源区及P型体接触区，所述N型源区5位于所述P阱3的上表层，所述P型体接触区4的至少一部分位于所述P阱3中并与所述N型源区5在水平方向上邻接。形成所述P型体接触区4及所述N型源区5的方法包括离子注入法，离子注入形成所述P型体接触区4在高温条件下进行，温度范围是450℃～550℃，使用SiO 2或SiN x作为硬掩膜实现图形化，离子注入形成所述N型源区5与形成所述P阱3的条件相同，即可在高温或者常温条件下进行，此外，离子注入形成所述P阱3、所述P型体接触区4及所述N型源区5时的注入角度范围包括0～7°。本实施例中形成所述P型体接触区4的温度是500℃。
作为示例，形成所述N型源区5及所述P型体接触区4之后进行第一退火步骤，所述第一退火步骤的时间范围是60min～120min，包括但不限于80min、100min，所述第一退火步骤的温度范围是1600℃～1800℃，包括但不限于1650℃、1750℃，进行所述第一退火步骤的目的是高温激活，具体步骤为：在晶圆正反两面覆盖碳膜后，将晶圆置于1600℃～1800℃条件下，退火60min～120min，去除碳膜，清洁晶圆正反两面。
作为示例，所述P型体接触区4的底面高于所述P阱3的底面，或者所述P型体接触区 4的底面低于所述P阱3的底面；或者所述P型体接触区4的底面齐平于所述P阱3的底面，实际应用时所述P型体接触区的4深度基于实际需要进行选择。
作为示例，所述P型体接触区4采用深P型离子注入形成，即通过控制离子注入时的工艺参数是所述P型体接触区4的深度较大以达到后续对沟槽6底介质电场能够产生更好地屏蔽作用。
作为示例，所述P阱3及所述P型体接触区4的掺杂离子包括铝离子，所述N型源区5的掺杂离子包括氮离子。
作为示例，在后续形成的沟槽6的水平延伸方向上，所述P型体接触区4为连续型或间断型。所述P型体接触区4在沟槽6延伸方向上连续即为连续型，所述P型体接触区4在所述沟槽6延伸方向上被所述N型源区5及所述P阱3区隔开即为间断型。
请参阅图7，形成沟槽，所述沟槽6贯穿所述N型源区5及所述P阱3，并向下延伸进所述外延层2中。
请参阅图8，执行步骤S5，形成高k介质层，所述高k介质层7覆盖所述沟槽6的内壁与底面，并延伸至所述N型源区5的部分上表面。
作为示例，在形成所述高k介质层7之前，还包括以下步骤：对所述沟槽6的底部进行圆角化处理；通过热氧化法在所述沟槽6的侧壁与底面形成牺牲氧化层(图中未标识)；去除所述牺牲氧化层。由于刻蚀形成所述沟槽6时，所述沟槽6的侧面与底面的夹角为直角，并且刻蚀后沟槽6的表面较为粗糙，不利于后续沉积的高k介质层7与沟槽6表面的结合，采用上述两个步骤能够使所述沟槽6的粗糙表面变得光滑平整，有利于降低高k介质/碳化硅衬底1界面的界面态。
作为示例，在形成所述高k介质层7之前，还包括沟槽6表面预处理步骤，所述预处理的方法包括氧等离子体表面处理及氨等离子体表面处理中的至少一种，本实施例中的采用了上述两种方法进行预处理步骤，进行预处理步骤的目的是对所述沟槽6的底面及侧壁进行清洁和钝化，改变其表面的悬挂键状态，更有利于后续介质的均匀性和可靠性，其中，氧等离子体表面处理用于清洁表面杂质，氨等离子体表面处理能够钝化介质表面，改变氮化硅表面的悬挂键分布，使得H悬挂键利于后续介质成膜，避免过分的岛状聚集导致的介质沉积不均匀。
作为示例，沉积高k介质层7的方法包括化学气相沉积法和原子层沉积法，本实施例中采用原子层沉积法沉积所述高k介质层7，鉴于此处高k介质层7应用于沟槽6栅型MOSFET，对介质的均匀性要求较为严格，采用化学气相沉积法可能达不到较为理想的效果。
作为示例，所述高k介质层7的材料类型包括铝基和铪基高k介质。纯Al 2O 3和HfO 2的 介电常数分别为9～10和17～25，禁带宽度分别为8.7eV～8.8eV和6eV～7eV。显然的，他们的介电常数和比SiO 2(介电常数为3.9)相比，可以极大地减少沟槽6拐角处介质侧的电场强度。具体的，所述高k介质层7包括AlSiO层、HfAlO层、SiO 2/Al 2O 3复合层及SiO 2/HfO 2复合层中的至少一种。此处需要额外说明的是，虽然氧化硅并非高k介质，掺入硅会有利于平衡介质/碳化硅之间的禁带偏差，降低漏电流，虽然这一行为也会降低铝基和铪基介质的介电常数，但最终仍旧会比纯SiO 2高，不影响其耐压和耐电场能力。
作为示例，沉积多种材料组成的高k介质层7时，沉积不同材料的叠层结构或者将多种材料混合后再沉积所述高k介质层7，沉积高k介质层7后进行第二退火步骤，所述第二退火步骤的时间范围是30s～3min，包括但不限于1min、2min，所述第二退火步骤的温度范围是550℃～900℃，包括但不限于650℃、800℃。第二步退火步骤的作用是使沉积的高k介质材料形成的层状结构最终形成栅介质层。
请参阅图9，执行步骤S6，形成栅电极层8于所述沟槽6中。所述栅电极层8包括多晶硅层及金属层中的至少一种。当所述栅电极层8为金属层时，所述金属层的材料包括TiN及TaN中的至少一种。当所述栅电极层8为多晶硅层时，所述多晶硅层的形成步骤为：在晶圆正面沉积多晶硅并填充整个沟槽6，沉积结束后采用回刻刻蚀方法将后续所述栅电极层8接触通孔外的部分全部刻蚀，整个沟槽6内的多晶硅呈现凹型(图中未显示)。
作为示例，在形成所述栅电极层8后，还包括平坦化所述栅电极层8的步骤，所述平坦化所述栅电极层8的方法包括化学机械抛光(CMP)及回刻蚀(etch-back)中的至少一种，本实施例中采用CMP对所述栅电极层8进行平坦化处理，以改善所述栅电极层8的界面状态。
作为示例，在形成所述源极欧姆接触层10之前，还包括形成场氧化层9的步骤，请参阅图10，显示为形成场氧化层后所得结构的剖面示意图，所述场氧化层9遮盖所述沟槽6，并遮盖所述源区的一部分。具体步骤为在晶圆正面沉积所述场氧化层9，沉积结束后通过光刻选择性刻蚀将有源区表面的场氧化层去除，将所述N型源区5和所述P型体接触区4暴露出来，以便于后续在该区域内形成源极欧姆接触层10。
作为示例，沉积所述场氧化层9之前沉积薄层氧化层作为所述栅电极层8的预保护层，采用多晶硅热氧化的方式制备得到，进一步提高对所述栅电极层8的保护作用。
请参阅图11，执行步骤S7，形成源极欧姆接触层10于所述P型体接触区4的上表面，所述源极欧姆接触层10还延伸至所述N型源区5的上表面与所述高k介质层7邻接。
作为示例，形成所述源极欧姆接触层10的方法包括采用溅射或电子束蒸发等工艺在晶圆正面沉积Ni、Al、Ti叠层金属或合金，通过揭开-剥离(lift-off)工艺实现图形化。后续采用850℃～1000℃高温退火实现欧姆接触区，此处的高温退火步骤即为第三退火步骤，具体温度 包括但不限于900℃、950℃。
请参阅图12，执行步骤S8，形成源极金属层11，所述源极金属层11覆盖所述源极欧姆接触层10与所述栅电极层8。形成所述源极金属层11包括在晶圆正面沉积金属材料，通过刻蚀工艺形成图形化。所述源极金属层11的材料包括Al、Ti及Ag中的至少一种。
作为示例，上述所述的全部工艺步骤均是在晶圆的正面进行的工艺，在晶圆的背面也需要采取相似工艺以形成漏极的欧姆接触金属层和漏极金属层等结构。
本实施例的基于高k介质的碳化硅沟槽型MOSFET的制作方法，主要采用介电常数大及生长均匀稳定的材料特性材料的高K介质作为栅介质层，有效改善传统沟槽型MOSFET器件的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁赡养质量难以控制的问题，提高器件的性能并且制作方法简单，能够实现大规模生产。
实施例二
本实施例提供一种基于高k介质的碳化硅沟槽型MOSFET，基于实施例一中的方法或其他合适方法制备得到，请参阅图13，显示为本实施例的MOSFET的立体结构示意图(仅显示一半)，具体包括衬底1、外延层2、P阱3、P型体接触区4、N型源区5、沟槽6(未标识)、高k介质层7、栅电极层8、源极欧姆接触层10及源极金属层11，其中，所述衬底1的上表面形成有外延层2；所述P阱3位于所述外延层2的上表层；所述N型源区5位于所述P阱3的上表层，所述P型体接触区4的至少一部分位于所述P阱3中并与所述N型源区5在水平方向上邻接；所述沟槽6贯穿所述N型源区5及所述P阱3，并向下延伸进所述外延层2中；所述高k介质层7覆盖所述沟槽6的内壁与底面，并延伸至所述N型源区5的部分上表面；所述栅电极层8位于所述沟槽6中；所述源极欧姆接触层10位于所述P型体接触区4的上表面，所述源极欧姆接触层10还延伸至所述N型源区5的上表面与所述高k介质层7邻接；所述源极金属层11覆盖所述源极欧姆接触层10与所述栅电极层8。
作为示例，该MOSFET还包括场氧化层9，所述场氧化层9遮盖所述沟槽6(未标识)，并遮盖所述源区的一部分，本实施例中所述场氧化层9位于所述栅介质层7及所述栅电极层8的裸露表面。
作为示例，所述高k介质层7包括AlSiO层、HfAlO层、SiO 2/Al 2O 3复合层及SiO 2/HfO 2复合层中的至少一种。
作为示例，所述P型体接触区4的底面高于所述P阱3的底面，或者所述P型体接触区4的底面低于所述P阱3的底面；或者所述P型体接触区4的底面齐平于所述P阱3的底面。本实施例中，所述P型体接触区4的底面高于所述P阱3的底面。
作为示例，在所述沟槽6的水平延伸方向上，所述P型体接触区4为连续型或间断型， 所述P型体接触区4在所述沟槽6延伸方向上连续即为连续型，所述P型体接触区4在所述沟槽6延伸方向上被所述N型源区5及所述P阱3区隔开即为间断型。本实施例中所述P型体接触区4包括连续型，为了保证所述P型体接触区4对所述沟槽6底面上的介质电场产生更好的屏蔽效应，需要采用连续型的P型体接触区4。
本实施例的基于高k介质的碳化硅沟槽型MOSFET，能够有效改善传统沟槽型MOSFET器件的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁赡养质量难以控制的问题，提高器件的性能。
实施例三
本实施例提供一种基于高k介质的碳化硅沟槽6型MOSFET，基于实施例一中的方法或其他合适方法制备得到，请参阅图14，显示为本实施例的MOSFET的立体结构示意图(仅显示一半)，具体包括衬底1、外延层2、P阱3、P型体接触区4、N型源区5、沟槽6(未标识)、高k介质层7、栅电极层8、源极欧姆接触层10及源极金属层11，其中，所述衬底1的上表面形成有外延层2；所述P阱3位于所述外延层2的上表层；所述N型源区5位于所述P阱3的上表层，所述P型体接触区4的至少一部分位于所述P阱3中并与所述N型源区5在水平方向上邻接；所述沟槽6贯穿所述N型源区5及所述P阱3，并向下延伸进所述外延层2中；所述高k介质层7覆盖所述沟槽6的内壁与底面，并延伸至所述N型源区5的部分上表面；所述栅电极层8位于所述沟槽6中；所述源极欧姆接触层10位于所述P型体接触区4的上表面，所述源极欧姆接触层10还延伸至所述N型源区5的上表面与所述高k介质层7邻接；所述源极金属层11覆盖所述源极欧姆接触层10与所述栅电极层8。
作为示例，该MOSFET还包括场氧化层9，所述场氧化层9遮盖所述沟槽6(未标识)，并遮盖所述源区的一部分，本实施例中所述场氧化层9位于所述栅介质层7及所述栅电极层8的裸露表面。
作为示例，所述高k介质层7包括AlSiO层、HfAlO层、SiO 2/Al 2O 3复合层及SiO 2/HfO 2复合层中的至少一种。
作为示例，所述P型体接触区4的底面高于所述P阱3的底面，或者所述P型体接触区4的底面低于所述P阱3的底面；或者所述P型体接触区4的底面齐平于所述P阱3的底面。本实施例中，所述P型体接触区4的底面低于所述P阱3的底面。
作为示例，在所述沟槽6的水平延伸方向上，所述P型体接触区4为连续型或间断型，所述P型体接触区4在所述沟槽6延伸方向上连续即为连续型，所述P型体接触区4在所述沟槽6延伸方向上被所述N型源区5及所述P阱3区隔开即为间断型。本实施例中所述P型体接触区4为间断型。
具体的，由于为了保证深的P型体接触区4注入的屏蔽效应，需要实现连续的P型体接触区4设计，同时为保证N型源区5的注入有效，需要将不同元胞间的N型源区5打断，考虑光刻、刻蚀工艺的系统偏差，保留额外的尺寸余量。这样在版图设计时会导致元胞尺寸较大，不利于器件性能的优化。针对本实施例中栅介质层采用高k介质的高击穿电场和高介电常数特性，采用间断式P型体接触区4设计也能够达到较好的屏蔽效果。结合参阅图15及图16，图15显示为本实施例的MOSFET的局部结构的立体结构示意图，图16显示为图15所示结构的俯视图，间断式P型体接触区4设计即P阱3和N型源区5完全联通，P型体接触区4设计为矩形间断形状。请参阅图17，显示为相邻两个元胞的俯视示意图，元胞A和元胞B的N型源区5是联通的，不需要考虑额外的间隔，仅保证和欧姆接触区有足够的接触面积即可，因此可以进一步缩小器件元胞尺寸，在保证沟槽6电场强度的前提下提高了面积利用率和能量密度，有利于器件性能提升。
本实施例的基于高k介质的碳化硅沟槽型MOSFET，能够有效改善传统沟槽型MOSFET器件的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁栅氧层质量难以控制的问题，提高器件的性能。
综上所述，本发明的基于高k介质的碳化硅沟槽型MOSFET及其制作方法，包括以下步骤：提供一衬底，所述衬底的上表面形成有外延层；形成P阱于所述外延层的上表层；形成N型源区及P型体接触区，所述N型源区位于所述P阱的上表层，所述P型体接触区的至少一部分位于所述P阱中并与所述N型源区在水平方向上邻接；形成沟槽，所述沟槽贯穿所述N型源区及所述P阱，并向下延伸进所述外延层中；形成高k介质层，所述高k介质层覆盖所述沟槽的内壁与底面，并延伸至所述N型源区的部分上表面；形成栅电极层于所述沟槽中；形成源极欧姆接触层于所述P型体接触区的上表面，所述源极欧姆接触层还延伸至所述N型源区的上表面与所述高k介质层邻接；形成源极金属层，所述源极金属层覆盖所述源极欧姆接触层与所述栅电极层。本发明的制作方法主要采用介电常数大及生长均匀稳定的材料特性材料的高k介质作为栅介质层，有效改善传统沟槽型MOSFET器件的沟槽拐角处栅氧层在反向耐压时电场集中以及沟槽侧壁栅氧质量难以控制的问题，提高器件的性能并且制作方法简单，能够实现大规模生产。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (14)

  1. 一种基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于，包括以下步骤：
    提供一衬底，所述衬底的上表面形成有外延层；
    形成P阱于所述外延层的上表层；
    形成N型源区及P型体接触区，所述N型源区位于所述P阱的上表层，所述P型体接触区的至少一部分位于所述P阱中并与所述N型源区在水平方向上邻接；
    形成沟槽，所述沟槽贯穿所述N型源区及所述P阱，并向下延伸进所述外延层中；
    形成高k介质层，所述高k介质层覆盖所述沟槽的内壁与底面，并延伸至所述N型源区的部分上表面；
    形成栅电极层于所述沟槽中；
    形成源极欧姆接触层于所述P型体接触区的上表面，所述源极欧姆接触层还延伸至所述N型源区的上表面与所述高k介质层邻接；
    形成源极金属层，所述源极金属层覆盖所述源极欧姆接触层与所述栅电极层。
  2. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于，在形成所述高k介质层之前，还包括以下步骤：
    对所述沟槽的底部进行圆角化处理；
    通过热氧化法在所述沟槽的侧壁与底面形成牺牲氧化层；
    去除所述牺牲氧化层。
  3. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：在形成所述高k介质层之前，还包括沟槽表面预处理步骤，所述预处理的方法包括氧等离子体表面处理及氨等离子体表面处理中的至少一种。
  4. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：在形成所述栅电极层后，还包括平坦化所述栅电极层的步骤，所述平坦化所述栅电极层的方法包括化学机械抛光及回刻蚀中的至少一种。
  5. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：在形成所述源极欧姆接触层之前，还包括形成场氧化层的步骤，所述场氧化层遮盖所述沟槽，并遮盖所述源区的一部分。
  6. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于： 所述P型体接触区的底面高于所述P阱的底面，或者所述P型体接触区的底面低于所述P阱的底面；或者所述P型体接触区的底面齐平于所述P阱的底面。
  7. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：在所述沟槽的水平延伸方向上，所述P型体接触区为连续型或间断型。
  8. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：所述栅电极层为多晶硅层；或者，所述栅电极层为金属层，所述金属层的材料包括TiN及TaN中的至少一种。
  9. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：所述外延层的厚度范围是6μm～50μm，所述外延层的掺杂浓度范围是1×10 13cm -3～1×10 17cm -3，所述外延层的掺杂类型包括N型掺杂，所述外延层的掺杂离子包括氮离子。
  10. 根据权利要求1所述的基于高k介质的碳化硅沟槽型MOSFET的制作方法，其特征在于：所述高k介质层包括AlSiO层、HfAlO层、SiO 2/Al 2O 3复合层及SiO 2/HfO 2复合层中的至少一种。
  11. 一种基于高k介质的碳化硅沟槽型MOSFET，其特征在于，包括：
    衬底，所述衬底的上表面形成有外延层；
    P阱，位于所述外延层的上表层；
    N型源区及P型体接触区，所述N型源区位于所述P阱的上表层，所述P型体接触区的至少一部分位于所述P阱中并与所述N型源区在水平方向上邻接；
    沟槽，所述沟槽贯穿所述N型源区及所述P阱，并向下延伸进所述外延层中；
    高k介质层，覆盖所述沟槽的内壁与底面，并延伸至所述N型源区的部分上表面；
    栅电极层，位于所述沟槽中；
    源极欧姆接触层，位于所述P型体接触区的上表面，所述源极欧姆接触层还延伸至所述N型源区的上表面与所述高k介质层邻接；
    源极金属层，覆盖所述源极欧姆接触层与所述栅电极层。
  12. 根据权利要求11所述的基于高k介质的碳化硅沟槽型MOSFET，其特征在于，所述高k介质层包括AlSiO层、HfAlO层、SiO 2/Al 2O 3复合层及SiO 2/HfO 2复合层中的至少一种。
  13. 根据权利要求11所述的基于高k介质的碳化硅沟槽型MOSFET，其特征在于，所述P型体接触区的底面高于所述P阱的底面，或者所述P型体接触区的底面低于所述P阱的底面；或者所述P型体接触区的底面齐平于所述P阱的底面。
  14. 根据权利要求11所述的基于高k介质的碳化硅沟槽型MOSFET，其特征在于：在所述沟槽的水平延伸方向上，所述P型体接触区为连续型或间断型。
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