WO2020114072A1 - 沟槽型功率器件及其形成方法 - Google Patents

沟槽型功率器件及其形成方法 Download PDF

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WO2020114072A1
WO2020114072A1 PCT/CN2019/110318 CN2019110318W WO2020114072A1 WO 2020114072 A1 WO2020114072 A1 WO 2020114072A1 CN 2019110318 W CN2019110318 W CN 2019110318W WO 2020114072 A1 WO2020114072 A1 WO 2020114072A1
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layer
cell
trench
metal layer
polysilicon
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PCT/CN2019/110318
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English (en)
French (fr)
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肖婷
史波
曾丹
廖勇波
敖利波
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珠海格力电器股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a trench-type power device and a method of forming the same.
  • trench power devices have the characteristics of high integration, low on-resistance, fast switching speed and small switching loss, and are widely used in various power management and switching circuits.
  • the conduction loss is mainly affected by the on-resistance, the smaller the characteristic on-resistance, the smaller the conduction loss; and the switching loss is mainly affected by the gate charge, the smaller the gate charge, the smaller the switching loss. Therefore, reducing on-resistance and gate charge are two effective ways to reduce the power consumption of power devices. By reducing the power consumption of power devices, energy can be used more efficiently.
  • the characteristic on-resistance In the manufacturing process of semiconductor power devices, there are usually two ways to reduce the characteristic on-resistance: First, by increasing the unit cell density, the total effective width of the unit cell is increased, but after the unit cell density is increased, the corresponding gate charge will increase It is impossible to reduce both the on-resistance and the gate charge; the second is to increase the epitaxial wafer doping concentration and reduce the thickness of the epitaxial layer, but it will reduce the breakdown voltage between the source and drain.
  • the purpose of this application is to provide a trench-type power device and a method for forming the same to reduce switching losses.
  • a slot-type power device including a plurality of cells, each of which includes: a cell trench, and a polysilicon layer formed on the sidewall of the cell trench And a filling metal layer filled in the cell trench; wherein the filling metal layer, the polysilicon layer, and the inner wall of the cell trench are respectively insulated.
  • the cell includes an insulating gate oxide layer formed between the polysilicon layer and the cell trench sidewall; and formed between the polysilicon layer and the filling metal layer Insulating oxide layer.
  • the filling metal layer is in direct contact with the source metal layer or the drain metal layer.
  • the cell is disposed in a semiconductor substrate, the cell includes a doping region of the same and/or different conductivity type as the semiconductor substrate, the doping region passes through the metal material layer and the source The electrode metal layer or the drain metal layer is connected.
  • the metal material layer is insulated from the filler metal layer.
  • the metal material layer and the filling metal layer are insulated by an insulating gate oxide layer.
  • the metal material layer and the filler metal layer are made of the same material.
  • the cell is disposed in a semiconductor substrate, a well region is formed between the bottom of the cell trench and the semiconductor substrate, and between the filling metal layer and the well region Insulation setting.
  • a method for forming a trench-type power device is also provided in the present application, the device includes several cells, and the forming of the cells includes the following steps:
  • a filling metal layer is formed on the insulating oxide layer to fill the cell trench.
  • the method further includes ion implanting the bottom wall of the cell trench to form a well region.
  • the filling metal layer, oxide layer and well region filled in the cell trench form a field plate structure, which can effectively improve the electric field concentration at the bottom of the cell trench and effectively suppress the bottom electric field To improve device reliability.
  • FIG. 1 is a cross-sectional view of a trench-type power device according to the related art
  • FIG. 2 is a cross-sectional view of a trench-type power device according to the present application.
  • FIG. 3 is a distribution diagram of capacitance around a cell trench in a trench power device according to the present application.
  • FIG. 4 is a cross-sectional view of another trench-type power device according to the present application.
  • FIG. 5 is a diagram of electric field distribution around a cell trench in a trench power device according to the present application.
  • FIG. 6 is a flow chart of manufacturing a trench power device according to the present application.
  • FIG. 7-15 are cross-sectional views of various steps of the trench-type power device according to the present application.
  • FIG. 1 shows a cross-sectional view of a trench-type power device according to the related art.
  • the trench-type power device shown in FIG. 1 includes several cells, and each of the cells
  • the method includes: a cell trench and a polysilicon layer 33' completely filled in the cell trench; each cell also includes a body region 40' and a doped region 51' located at the periphery of the cell trench;
  • the polysilicon layer 33' is covered with an insulating oxide layer 34', and a metal electrode layer 70' is formed above the insulating oxide layer 34'.
  • FIG. 1 shows a cross-sectional view of a trench-type power device according to the related art.
  • the trench-type power device shown in FIG. 1 includes several cells, and each of the cells
  • the method includes: a cell trench and a polysilicon layer 33' completely filled in the cell trench; each cell also includes a body region 40' and a doped region 51' located at the periphery of the cell trench;
  • a polysilicon layer 33 ′ inside the cell trench and the semiconductor substrate 30 ′, body region 40 ′, and doped region 51 ′ located on the periphery are formed Larger reverse capacitances, the presence of these reverse capacitances will limit the improvement of the switching characteristics to a certain extent.
  • the trench-type power device includes a first metal electrode layer 10 and a first semiconductor type
  • the substrate 20 of the second semiconductor type, the substrate 30 of the second semiconductor type, and the buffer layer 30a of the second semiconductor type exist between the substrate 20 of the first semiconductor type and the substrate 30 of the second semiconductor type.
  • the second semiconductor type substrate 30 as a semiconductor substrate, a plurality of cells with repeated structures are formed.
  • Each cell includes a cell trench 31, a polysilicon layer 33 formed on the side wall of the cell trench, and a filling metal layer 35 filled in the cell trench.
  • the filling metal layer 35, the polysilicon layer 33, and the inner wall of the cell trench 31 are respectively insulated.
  • Cies, Coes, and Cres affect the turn-on and turn-off time and turn-on and turn-off delay time of the IGBT device, which affects the switching loss of the IGBT.
  • the calculation formula of Cies, Coes, and Cres is as follows:
  • FIG. 3 is a capacitance distribution diagram around the cell trench of the trench power device according to the present application. It can be seen from Figure 3 that Cgc (gate-collector capacitance, also called Miller capacitance) is effectively reduced; and within the same area, Cce (collector-emitter capacitance) will be relatively reduced. It can be concluded that Cies (input capacitance), Coes (output capacitance), and Cres (Miller capacitance) will all be reduced, and the parasitic capacitance will be reduced, which can effectively reduce switching losses. In addition, as can be seen from FIG.
  • Cgc gate-collector capacitance, also called Miller capacitance
  • Cce collector-emitter capacitance
  • the cell further includes an insulating gate oxide layer 32 formed between the polysilicon layer 33 and the sidewall of the cell trench 31; and the polysilicon layer 33 and the filling The insulating oxide layer 34 between the metal layers 35.
  • the insulating gate oxide layer 32 and the insulating oxide layer 34 can be selected from the conventional materials used in the trench-type power device, as long as the filling metal layer 35, the polysilicon layer 33, and the inner wall of the cell trench 31 can be realized It can be insulated separately.
  • the thickness of one side of the polysilicon layer 33 formed on the sidewall of the cell trench can be set reasonably according to the size of the single cell.
  • the polysilicon layer 33 has a thickness of 0.3 ⁇ m-1.5 ⁇ m on one side.
  • the thickness of the polysilicon layer 33 refers to the thickness perpendicular to the side wall direction of the cell trench 31.
  • the thickness ratio of the filling metal layer 35 to the polysilicon layer 33 on one side is 10:1 to 1:1 in a direction perpendicular to the sidewall of the cell trench 31.
  • the body region 40 formed in the substrate 30 of the second semiconductor type is included in each cell.
  • the body region 40 has a different conductivity type from the substrate 30 of the second semiconductor type.
  • Each cell also includes doped regions 51, 52 of the first semiconductor type and/or second semiconductor type formed in the body region 40 (doped regions are also referred to as implanted regions).
  • the exposed surfaces of the doped regions 51, 52 of the first semiconductor type and/or the second semiconductor type form part of the exposed surface of the cell.
  • the doped regions 51, 52 of the first semiconductor type and/or the second semiconductor type partially overlap.
  • the doped region 52 of the second semiconductor type may be disposed near the sidewall of the cell trench 31. In one embodiment, part of the surface of the doped region 52 of the second semiconductor type serves as a sidewall of the cell trench 31.
  • a metal material layer 60 is also formed on the surface of the second semiconductor-type substrate 30 where several cells are formed.
  • the doped regions 51 and 52 of the first semiconductor type and/or the second semiconductor type in each cell are in direct contact with the metal material layer 60.
  • the metal material layer 60 and the filling metal layer 35 are insulated.
  • the metal material layer 60 and the filling metal layer 35 are insulated and separated by an insulating gate oxide layer 32.
  • the materials of the metal material layer 60 and the filler metal layer 35 may be the same or different.
  • the metal material layer 60 and the filling metal layer 35 are made of the same material, for example, metal tungsten is selected.
  • a second metal electrode layer 70 is formed above the metal material layer 60, wherein the metal filling layer 35 is in direct contact with the second metal electrode layer 70.
  • the first metal electrode layer 10 and the second metal electrode layer 70 are each a source metal layer and a drain metal layer; the first semiconductor type and the second semiconductor type are each an N-type semiconductor and a P-type semiconductor;
  • a trench-type power device may be used for the first metal electrode layer 10 and the second metal electrode layer 70, as well as the material of the first semiconductor type and the material of the second semiconductor type.
  • a trench-type power device is provided. As shown in FIG. 4, this trench-type power device has similarities to the trench-type power device provided in the first embodiment. The main difference between the two structures is that, in this second embodiment, in addition to forming a polysilicon layer 33 on the side wall of the cell trench 31 and forming a filling metal layer 35 inside the cell trench 31, A well region 36 is formed between the bottom of the cell trench 31 and the semiconductor substrate (substrate 30 of the second semiconductor type), and the filling metal layer 35 is insulated from the well region 36.
  • FIG. 5 shows an electric field distribution diagram around the cell trench in the trench-type power device according to the second embodiment of the present application.
  • a polysilicon gate is formed only on the sidewalls of the trench, and then a filling metal layer (such as metal tungsten) is formed inside the cell trench to form a metal field plate filled with tungsten plugs;
  • the trench design structure can also reduce the surface electric field at the bottom of the cell trench; and. By forming a well region under the trench, it is beneficial to further reduce the effect of the electric field.
  • the thickness of the well region 36 is not greater than 10 ⁇ m, where the thickness of the well region refers to the thickness perpendicular to the bottom direction of the cell trench.
  • the ion implantation rate of the well region 36 at the bottom of the cell trench 31 can be reasonably selected according to the surface electric field at the bottom of the cell trench. In one embodiment, the ion implantation rate of the well region 36 at the bottom of the cell trench 31 is 1.0E13-3.5E17.
  • a method for forming a trench-type power device is provided. As shown in FIG. 6, the device includes several cells, and forming the cells includes the following steps:
  • a polysilicon layer is formed on the sidewall of the cell trench;
  • the method further includes ion implanting the bottom wall of the cell trench to form a well region.
  • an N-channel is taken as an example to describe in detail a method for forming a trench-type power device described in the patent of the present application. The steps are as follows:
  • a silicon substrate wafer including a substrate 20 of a first semiconductor type, a buffer sheet 30a of a second semiconductor type, and a substrate 30 of a second semiconductor type to form a structure as shown in FIG. 7; by a photolithography process Process the silicon substrate wafer to form the pattern of the cell trench structure of each cell; then use a reactive plasma etching process to etch the cell trench 31 on the silicon wafer with the cell trench pattern, Form the structure shown in Figure 8;
  • a thermal oxidation process is used to grow an insulating gate oxide layer 32 on the silicon substrate wafer on which the cell trench 31 is formed to form the structure shown in FIG. 9;
  • a chemical vapor deposition process is used to deposit a layer of polysilicon film on the surface of the insulating gate oxide layer 32 as the gate of the IGBT device to form the structure shown in FIG. 10;
  • a reactive plasma etching process is used to etch the polysilicon film to form a polysilicon layer on the sidewalls of the cell trench 31, also known as a polysilicon sidewall gate, to form the structure shown in FIG. 11;
  • implant ions in the bottom wall of the cell trench 31 to form a P-type well region implant ions in the periphery of the side wall of the cell trench 31 to form a P-type body region; in the P-type body
  • the implanted ions in the region form an N+ doped region and a P+ doped region to form the structure shown in FIG. 12;
  • a chemical vapor deposition process is used to deposit an oxide insulating layer 34 on the surface of the previously prepared structure as an electrical isolation layer, followed by contact hole pattern lithography, and a reactive plasma etching process for contact hole oxide layer etching Erosion to form the structure shown in Figure 13;
  • a layer of thick metal aluminum is deposited on the surface by a magnetron sputtering process, and the metal of the gate and emitter of the IGBT device is formed by photolithography and etching processes to form the structure shown in FIG. 15;
  • the process is basically the same as the aforementioned N-channel trench power devices, mainly in the choice of materials, the choice of implanted ions is different, these differences refer to conventional choices in the industry That's it.

Abstract

本申请公开了一种沟槽型功率器件及其形成方法，该器件包括有若干个元胞，每个所述元胞包括：元胞沟槽、形成于所述元胞沟槽侧壁上的多晶硅层、以及填充在所述元胞沟槽内的填充金属层；其中，所述填充金属层、所述多晶硅层、以及所述元胞沟槽的内壁之间分别绝缘设置。通过在元胞沟槽的侧壁上形成多晶硅(栅)，形成多晶硅-填充金属层-多晶硅的复合结构，有利于改善器件使用过程中的Cgc反向电容，改善芯片开关特性，同时能降低开关损耗。

Description

沟槽型功率器件及其形成方法
相关申请
本申请要求2018年12月03日申请的，申请号为201811467502.X，名称为“沟槽型功率器件及其形成方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及半导体的领域，具体而言，涉及一种沟槽型功率器件及其形成方法。
背景技术
业内人士都知道，沟槽功率器件具有高集成度、导通电阻低、开关速度快和开关损耗小的特点，被广泛应用于各类电源管理及开关转换电路中。随着各国对节能减排越来越重视，对功率器件的损耗及转换效率要求也越来越高。其中，导通损耗主要受导通电阻的影响，特征导通电阻越小，导通损耗越小；而开关损耗主要受栅极电荷影响，栅极电荷越小，开关损耗也越小。因此，降低导通电阻和栅极电荷是降低功率器件功耗的两个有效途径，通过降低功率器件的功耗可以更加高效地使用能源。
在半导体功率器件的制备过程中，降低特征导通电阻通常有两种方法：一是通过提高单胞密度，增加单胞的总有效宽度，但是，单胞密度提高后，相应的栅电荷会增加，无法做到既降低导通电阻又降低栅电荷；二是通过提高外延片掺杂浓度、减小外延层厚度来实现，但会降低源漏极之间的击穿电压。
发明内容
本申请的目的是提供一种沟槽型功率器件及其形成方法，以降低开关损耗。
为此，在本申请中提供了一种槽型功率器件，包括有若干个元胞，每个所述元胞包括：元胞沟槽、形成于所述元胞沟槽侧壁上的多晶硅层、以及填充在所述元胞沟槽内的填充金属层；其中，所述填充金属层、所述多晶硅层、以及所述元胞沟槽的内壁之间分别绝缘设置。
在其中一个实施例中，所述元胞包括形成在所述多晶硅层与所述元胞沟槽侧壁之间的绝缘栅氧化层；以及形成在所述多晶硅层和所述填充金属层之间的绝缘氧化层。
在其中一个实施例中，所述填充金属层与源极金属层或漏极金属层直接接触。
在其中一个实施例中，所述元胞设置在半导体基板内，所述元胞包括与所述半导体基 板导电类型相同和/或不同的掺杂区，所述掺杂区通过金属材料层与源极金属层或漏极金属层连接。
在其中一个实施例中，所述金属材料层与所述填充金属层绝缘间隔。
在其中一个实施例中，所述金属材料层与所述填充金属层之间通过绝缘栅氧化层绝缘设置。
在其中一个实施例中，所述金属材料层与所述填充金属层的材质相同。
在其中一个实施例中，所述元胞设置在半导体基板内，所述元胞沟槽的底部与所述半导体基板之间形成有阱区，且所述填充金属层与所述阱区之间绝缘设置。
同时，在本申请中还提供了一种沟槽型功率器件的形成方法，所述器件包括有若干个元胞，形成所述元胞包括以下步骤：
刻蚀形成元胞沟槽；
在所述元胞沟槽的内壁上生长绝缘栅氧化层；
在所述绝缘栅氧化层上，所述元胞沟槽的侧壁上形成多晶硅层；
在所述多晶硅层上，形成包覆所述多晶硅层的绝缘氧化层；和
在所述绝缘氧化层上形成填充金属层，充满所述元胞沟槽。
在其中一个实施例中，形成所述元胞的步骤中，在生长绝缘栅氧化层之前，还包括对元胞沟槽底壁进行离子注入，以形成阱区。
应用本申请的沟槽型功率器件及其形成方法，通过在元胞沟槽的侧壁上形成多晶硅(栅)，形成多晶硅-填充金属层-多晶硅的复合结构，有利于改善器件使用过程中的Cgc反向电容，改善芯片开关特性，同时能降低开关损耗。
此外，通过在元胞单元下部形成阱区，使得在元胞沟槽内填充的填充金属层、氧化层和阱区形成场板结构，能够有效改善元胞沟槽底部电场聚集，有效压制底部电场，提高器件可靠性。
附图说明
图1为根据相关技术的沟槽型功率器件剖面图；
图2为根据本申请的一种沟槽型功率器件剖面图；
图3为根据本申请的沟槽型功率器件中元胞沟槽周围的电容分布图；
图4为根据本申请的另一种沟槽型功率器件剖面图；
图5为根据本申请的沟槽型功率器件中元胞沟槽周围的电场分布图；
图6为根据本申请的沟槽型功率器件的制备流程图；
图7-15为根据本申请的沟槽型功率器件的各步骤剖面图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下通过实施例，并结合附图，对本申请的光伏组件清洁系统进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1所示，图1示出了一种根据相关技术的沟槽型功率器件剖面图，在图1所示的沟槽型功率器件中包括有若干个元胞，每个所述元胞包括：元胞沟槽和完整的填充在所述元胞沟槽内的多晶硅层33’；每个所述元胞还包括位于元胞沟槽外围的体区40’与掺杂区51’；其中所述多晶硅层33’上覆盖有绝缘氧化层34’，所述绝缘氧化层34’上方形成金属电极层70’。在图1所示的这种沟槽型功率器件中，位于元胞沟槽内部的多晶硅层33’与位于外围的半导体基板30’、体区40’、以及掺杂区51’之间会形成较大的反向电容，这些反向电容的存在将会在一定程度上限值开关特性的提升。
基于这种现状的存在，在申请的第一实施方式中，提供了一种沟槽型功率器件，如图2所示，该沟槽型功率器件包括第一金属电极层10、第一半导体类型的衬底20、第二半导体类型的衬底30、在第一半导体类型衬底20和第二半导体类型的衬底30之间存在第二半导体类型的缓冲层30a。在第二半导体类型的衬底30作为半导体基板中形成有若干个结构重复的元胞。在每个所述元胞包括：元胞沟槽31、形成于所述元胞沟槽侧壁上的多晶硅层33、以及填充在所述元胞沟槽内的填充金属层35。所述填充金属层35、所述多晶硅层33、以及所述元胞沟槽31的内壁之间分别绝缘设置。
在沟槽型功率器件中，Cies、Coes和Cres是影响IGBT器件的开通和关断时间，以及开通和关断延迟时间，从而影响IGBT的开关损耗，Cies、Coes和Cres的计算公式如下：
Cies＝Cge+Cgc
Coes＝Cce+Cgc
Cres＝Cgc
如图3所示，图3为根据本申请的沟槽型功率器件元胞沟槽周围的电容分布图。由图3可以看出，Cgc(门极-集电极电容，也称为米勒电容)有效降低；而且在相同面积内，Cce(集电极-发射极电容)会相对减少。由此可推出Cies(输入电容)、Coes(输出电容)、Cres(米勒电容)都会降低，寄生电容降低，能有效降低开关损耗。此外，由图3还可以看出，在本申请沟槽型功率器件中元胞沟槽底部Cgc电容没有了，总的Cgc降低，减少开关损耗；同时在相同面积中，受工艺条件限制，此沟槽结构比常规沟槽结构设计宽，相比 Cce电容也会减少。
如图2所示，所述元胞还包括形成在所述多晶硅层33与所述元胞沟槽31侧壁之间的绝缘栅氧化层32；以及形成在所述多晶硅层33和所述填充金属层35之间的绝缘氧化层34。绝缘栅氧化层32和绝缘氧化层34可选择沟槽型功率器件所采用的常规材料，只要能够实现将所述填充金属层35、所述多晶硅层33、以及所述元胞沟槽31的内壁之间分别绝缘设置即可。
根据本申请所述的沟槽型功率器件，形成在元胞沟槽侧壁上的多晶硅层33的单侧厚度可以根据单个元胞的尺寸合理设置。在一实施例中，所述多晶硅层33的单侧厚度为0.3μm-1.5μm。多晶硅层33的厚度是指垂直于元胞沟槽31侧壁方向的厚度。
根据本申请所述的沟槽型功率器件，只要在元胞沟槽31内填充所述填充金属层35即可在一定程度上实现本申请的目的。在一实施例中，沿垂直于元胞沟槽31侧壁的方向，所述填充金属层35与单侧所述多晶硅层33的厚度比为10:1-1:1。
如图2所示，在每个元胞中包括形成在以第二半导体类型的衬底30中的体区40。所述体区40具有与第二半导体类型的衬底30不同的导电类型。在每个元胞中还包括形成在体区40中的第一半导体类型和/或第二半导体类型的掺杂区51、52(掺杂区也称为注入区)。第一半导体类型和/或第二半导体类型的掺杂区51、52的部分表面裸露形成所述元胞的外露表面。当体区40中同时存在第一半导体类型和/或第二半导体类型的掺杂区51、52时，第一半导体类型和/或第二半导体类型的掺杂区51、52部分交叠。第二半导体类型的掺杂区52可靠近所述元胞沟槽31的侧壁设置。在一实施例中，所述第二半导体类型的掺杂区52的部分表面作为所述元胞沟槽31的侧壁。
如图2所示，在所述第二半导体类型的衬底30上形成有若干个元胞的表面上还形成有金属材料层60。每个元胞中的第一半导体类型和/或第二半导体类型的掺杂区51、52与所述金属材料层60直接接触。在一实施例中，所述金属材料层60与填充金属层35之间绝缘设置。在一实施例中，所述金属材料层60与填充金属层35之间通过绝缘栅氧化层32绝缘隔开。在本申请中，金属材料层60和填充金属层35的材质可以相同或不同。在一实施例中，金属材料层60和填充金属层35的材质相同，例如均选取金属钨。
如图2所示，在所述金属材料层60上方形成有第二金属电极层70，其中金属填充层35与第二金属电极层70直接接触。
在上述实施方式中，第一金属电极层10和第二金属电极层70互为源极金属层和漏极金属层；第一半导体类型和第二半导体类型互为N型半导体和P型半导体；其中对于第一金属电极层10和第二金属电极层70，以及第一半导体类型的材料和第二半导体类型的材 料采用沟槽型功率器件即可。
在本申请的第二实施方式中，提供了一种沟槽型功率器件，如图4所示，这种沟槽型功率器件具有与第一实施方式中所提供的沟槽型功率器件相似的结构，两者的主要区别在于，在该第二实施方式中，除了在元胞沟槽31的侧壁上形成多晶硅层33，在元胞沟槽31内部形成填充金属层35之外，所述元胞沟槽31的底部与所述半导体基板(第二半导体类型的衬底30)之间形成有阱区36，且所述填充金属层35与所述阱区36之间绝缘设置。
如图5所示，图5示出了根据本申请第二实施方式的沟槽型功率器件中元胞沟槽周围的电场分布图。如图5所示，仅在沟槽侧壁形成多晶硅栅极，然后在元胞沟槽的内部形成填充金属层(例如金属钨)，进而形成钨塞填充结构的金属场板；从而即使采用宽沟槽设计结构，也能够降低了该元胞沟槽底部的表面电场；而且。通过在沟槽下方形成阱区有利于进一步降低电场的作用。
在上述沟槽型功率器件中，只要在所述元胞沟槽31的底部与所述半导体基板(第二半导体类型的衬底30)之间形成有阱区36就能有在一定程度上降低电场的作用。在一实施例中，阱区36的厚度不大于10μm，其中阱区的厚度是指垂直于元胞沟槽的底部方向的厚度。对于位于所述元胞沟槽31的底部的阱区36的离子注入率可以根据元胞沟槽底部的表面电场可以进行合理选择。在一实施例中，位于所述元胞沟槽31的底部的阱区36的离子注入率为1.0E13-3.5E17。
在本申请的第三种实施方式中，提供了一种沟槽型功率器件的形成方法，如图6所示，所述器件包括有若干个元胞，形成所述元胞包括以下步骤：
S1、刻蚀形成元胞沟槽；
S2、在所述元胞沟槽的内壁上生长绝缘栅氧化层；
S3、在所述绝缘栅氧化层上，所述元胞沟槽的侧壁上形成多晶硅层；
S4、在所述多晶硅层上，形成包覆所述多晶硅层的绝缘氧化层；和
S5、在所述绝缘氧化层上形成填充金属层，充满所述元胞沟槽。
在一实施例中，形成所述元胞的步骤中，在生长绝缘栅氧化层之前，还包括对元胞沟槽底壁进行离子注入，以形成阱区。
接下来，结合附图7至15，以N沟道为例详细描述本申请专利所述的一种沟槽型功率器件的形成方法，其步骤为：
1)选择包括第一半导体类型的衬底20、第二半导体类型的缓冲片30a、以及第二半导体类型的衬底30的硅衬底晶圆，形成如图7所示结构；通过光刻工艺处理硅衬底晶圆以形成每个元胞的元胞沟槽结构的图形；接着采用反应等离子刻蚀工艺，在带有元胞沟槽图 形的硅片上刻蚀出元胞沟槽31，形成如图8所示的结构；
2)采用热氧化工艺在形成有元胞沟槽31的硅衬底晶圆上生长一层绝缘栅氧化层32，形成如图9所示的结构；
3)采用化学气相沉积工艺在绝缘栅氧化层32表面沉积一层多晶硅薄膜，作为IGBT器件的栅极，形成如图10所示的结构；
4)采用反应等离子刻蚀工艺，刻蚀多晶硅薄膜，在元胞沟槽31的侧壁上形成多晶硅层，也称为多晶硅侧壁栅极，形成如图11所示的结构；
5)采用离子注入工艺和热扩散工艺，在元胞沟槽31的底壁注入离子形成P型阱区；在元胞沟槽31的侧壁外围注入离子形成P型体区；在P型体区注入离子形成N+掺杂区和P+掺杂区，形成如图12所示的结构；
6)采用化学气相沉积工艺在前述制备的结构体的表面沉积一层氧化绝缘层34，作为电性隔离层，随后进行接触孔图形光刻，和采用反应等离子刻蚀工艺进行接触孔氧化层刻蚀，形成如图13所示的结构；
7)采用化学气相沉积工艺在前述制备的结构体的表面沉积一层金属钨薄膜，并填充到接触孔和沟槽栅结构中。随后采用刻蚀工艺，将表面多余的金属钨刻蚀，形成金属材料层60和填充金属层35，从而形成接触孔钨塞结构和沟槽栅钨塞场板结构，形成如图14所示的结构；
8)采用磁控溅射工艺在表面沉积一层厚金属铝，并通过光刻、刻蚀工艺，形成IGBT器件的栅极和发射极引出金属，形成如图15所示的结构；
9)进行背面减薄和标准的FS-IGBT背面工艺。
在形成P沟道的沟槽型功率器件中，工艺与前述N沟道的沟槽型功率器件基本相同，主要在于材料的选择，注入离子的选择有所区别，这些区别参照行业内的常规选择即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种沟槽型功率器件，其特征在于，包括有若干个元胞，每个所述元胞包括：
    元胞沟槽；
    形成于所述元胞沟槽侧壁上的多晶硅层；以及
    填充在所述元胞沟槽内的填充金属层；
    其中，所述填充金属层、所述多晶硅层、以及所述元胞沟槽的内壁之间分别绝缘设置。
  2. 根据权利要求1所述的器件，其特征在于，所述元胞还包括：
    形成在所述多晶硅层与所述元胞沟槽侧壁之间的绝缘栅氧化层；以及
    形成在所述多晶硅层和所述填充金属层之间的绝缘氧化层。
  3. 根据权利要求1所述的器件，其特征在于，所述填充金属层与源极金属层或漏极金属层直接接触。
  4. 根据权利要求3所述的器件，其特征在于，所述元胞设置在半导体基板内，所述元胞包括与所述半导体基板导电类型相同和/或不同的掺杂区，所述掺杂区通过金属材料层与源极金属层或漏极金属层连接。
  5. 根据权利要求3所述的器件，其特征在于，所述金属材料层与所述填充金属层绝缘间隔。
  6. 根据权利要求3所述的器件，其特征在于，所述金属材料层与所述填充金属层之间通过绝缘栅氧化层绝缘设置。
  7. 根据权利要求2所述的器件，其特征在于，所述金属材料层与所述填充金属层的材质相同，均为金属钨。
  8. 根据权利要求1所述的器件，其特征在于，所述元胞设置在半导体基板内，所述元胞沟槽的底部与所述半导体基板之间形成有阱区，且所述填充金属层与所述阱区之间绝缘设置。
  9. 一种沟槽型功率器件的形成方法，所述器件包括有若干个元胞，其特征在于，形成所述元胞包括以下步骤：
    刻蚀形成元胞沟槽；
    在所述元胞沟槽的内壁上生长绝缘栅氧化层；
    在所述绝缘栅氧化层上，所述元胞沟槽的侧壁上形成多晶硅层；
    在所述多晶硅层上，形成包覆所述多晶硅层的绝缘氧化层；和
    在所述绝缘氧化层上形成填充金属层，充满所述元胞沟槽。
  10. 根据权利要求9所述的方法，其特征在于，形成所述元胞的步骤中，在生长绝缘 栅氧化层之前，还包括对元胞沟槽底壁进行离子注入，以形成阱区。
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