WO2024060811A1 - 一种功率mosfet及其制备方法 - Google Patents

一种功率mosfet及其制备方法 Download PDF

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Publication number
WO2024060811A1
WO2024060811A1 PCT/CN2023/107982 CN2023107982W WO2024060811A1 WO 2024060811 A1 WO2024060811 A1 WO 2024060811A1 CN 2023107982 W CN2023107982 W CN 2023107982W WO 2024060811 A1 WO2024060811 A1 WO 2024060811A1
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layer
source
trench
gate
region
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PCT/CN2023/107982
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English (en)
French (fr)
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李平
马荣耀
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华润微电子（重庆）有限公司
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Publication of WO2024060811A1 publication Critical patent/WO2024060811A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a power MOSFET and a preparation method thereof.
  • SiC MOSFET Silicon carbide metal oxide semiconductor field effect transistor
  • SiC MOSFET Silicon carbide metal oxide semiconductor field effect transistor
  • a fast recovery diode needs to be connected in reverse parallel outside the power device as a freewheeling diode.
  • external diodes will undoubtedly increase the size of the system and introduce additional parasitic inductance.
  • the PN junction body diode also has a large turn-on voltage (near 3V at room temperature).
  • the MOSFET body diode Using it as a freewheeling diode will cause larger conduction losses. And because there are basal plane dislocations in SiC crystals, during bipolar operation, the recombination of electrons and holes will cause stacking faults to spread from the basal plane dislocations, thereby increasing the on-resistance of the device and reducing the reliability of the device. Therefore, in SiC MOSFETs, SiC parasitic body diodes are not suitable to be used as freewheeling diodes.
  • SiC MOSFETs are usually integrated with junction barrier diodes or Schottky barrier diodes, and low turn-on voltage junction barrier diodes or Schottky barrier diodes are used to transmit reverse current.
  • junction barrier diodes or Schottky barrier diodes low turn-on voltage junction barrier diodes or Schottky barrier diodes are used to transmit reverse current.
  • this type of diode It has large leakage, especially under high temperature conditions, which seriously affects the reliability of the device.
  • Heterojunction diodes can also be integrated into SiC MOSFETs to suppress the SiC body diode while maintaining a small off-state leakage current. However, making the heterojunction inside the device will increase process complexity and cost.
  • the solution of integrating a built-in metal oxide semiconductor (MOS) channel diode into a SiC MOSFET will not significantly increase the off-state leakage and process cost of the device, in order to make the integrated MOS channel diode have a lower turn-on voltage, Usually, the thickness of the gate oxide layer is reduced on one side of the MOS channel or an N-type layer with a lower epitaxial concentration is used, which will also affect the reliability of the device.
  • MOS metal oxide semiconductor
  • the purpose of the present invention is to provide a power MOSFET and a preparation method thereof to solve the problems in the prior art of high turn-on voltage of the integrated body diode and poor reliability of the device in the power MOSFET.
  • the present invention provides a power MOSFET, comprising:
  • a semiconductor structure including a first conductive type substrate and a first conductive type epitaxial layer stacked in sequence, the epitaxial layer including a first conductive type drift region and a first conductive type current transmission layer stacked in sequence;
  • a plurality of gate structures arranged at intervals are embedded in the current transmission layer
  • a source trench structure is located between two adjacent gate structures.
  • the side walls of the source trench structure are separated from the side walls of the gate structure by a preset distance.
  • the source trench structure An upper trench with a predetermined depth is provided above, and the sidewalls of the upper trench protrude from the sidewalls of the source trench structure in the direction toward the gate structure;
  • a second conductive type body region is located on the upper surface layer of the current transfer layer between the source trench structure and the gate structure, and the bottom of the upper trench exposes the body region;
  • a plurality of first conductivity type source regions and second conductivity type contact regions, the source regions and the contact regions are located on the upper surface layer of the body region and between the gate structure and the upper trench The source region is adjacent to the contact region, and the sidewall of the source region away from the contact region is adjacent to the sidewall of the gate structure;
  • a barrier layer is located at the bottom of the upper trench.
  • the barrier layer covers the exposed surface of the body region at the bottom of the upper trench.
  • the barrier layer is connected to the body region and the source trench.
  • the groove structure and the current transmission layer form a MOS channel diode;
  • a source electrode and a drain electrode the source electrode is electrically connected to the barrier layer, the source region, the contact region and the source trench structure, and the drain electrode is electrically connected to the substrate.
  • the gate structure includes a gate trench, a first dielectric layer and a gate conductive layer.
  • the first dielectric layer is located on the inner wall and bottom surface of the gate trench and wraps the gate conductive layer.
  • the source trench structure includes a source trench, a second dielectric layer and a source conductive layer.
  • the second dielectric layer is located on the inner wall and bottom surface of the source trench and wraps the source conductive layer. Side walls and bottom.
  • a second conductive type electric field shielding layer is provided in the current transmission layer directly below the gate structure and the source trench structure, and the bottom surface of the electric field shielding layer is in contact with the current transmission layer.
  • the bottom surfaces are separated by a preset distance, the upper surface of the electric field shielding layer is in contact with the bottom surface of the gate structure and the source trench structure, and two adjacent electric field shielding layers are arranged at intervals.
  • the conductive channel length of the MOS channel diode is adjusted by adjusting the depth of the bottom surface of the upper trench.
  • the barrier layer includes one of a first conductivity type doped layer and a metal barrier contact layer.
  • the barrier layer is the metal barrier contact layer, and the bottom surface of the upper trench is lower than the bottom surface of the contact area.
  • the barrier layer covers the exposed surface of the source trench structure at the bottom of the upper trench.
  • the barrier layer is the first conductivity type doping layer, and the lower surface of the barrier layer is lower than the lower surface of the contact region and is spaced a preset distance from the bottom surface of the body region, The sidewalls of the barrier layer and the sidewalls of the source trench structure adjacent.
  • the doping concentration of the barrier layer is higher than the doping concentration of the current transport layer.
  • the invention also provides a method for preparing a power MOSFET, which includes the following steps:
  • the semiconductor layer includes a first conductive type substrate and a first conductive type epitaxial layer, the epitaxial layer includes a first conductive type drift region and a first conductive type current transmission layer stacked in sequence;
  • a second conductive type body region with a predetermined thickness is formed on the upper surface layer of the current transfer layer, and a plurality of alternately arranged first conductive type source regions and second conductive type contact regions are formed on the upper surface layer of the body region, and the The side walls of the source region and the contact region are adjacent to each other;
  • the source trench structure is etched to obtain a trench located above the source trench structure, and the sidewalls of the upper trench protrude beyond the sides of the source trench structure in a direction toward the gate structure. a wall with the bottom of said upper trench exposing said body region;
  • a barrier layer is formed at the bottom of the upper trench.
  • the barrier layer covers the exposed surface of the body region at the bottom of the upper trench.
  • the barrier layer is connected to the body region and the source trench.
  • the groove structure and the current transmission layer form a MOS channel diode;
  • a source electrode electrically connected to the barrier layer, the source region, the contact region and the source trench structure is formed, and a drain electrode electrically connected to the substrate is formed.
  • the power MOSFET and its preparation method of the present invention are provided by arranging the source trench structure and the upper trench located above the source trench structure in front of two adjacent gate structures. And the sidewall of the upper trench extends toward the direction of the gate structure to a predetermined distance from the sidewall of the source trench structure, and the barrier layer is formed at the bottom of the upper trench, so The exposed surface of the body region covering the bottom surface of the channel is adjusted by adjusting the depth of the upper trench to reduce the distance between the bottom surface of the barrier layer and the bottom surface of the body region. Reducing the length of the conductive channel in the MOS diode structure composed of the barrier layer, the body region, and the source trench structure causes electrons to pass through the device due to the leakage-induced barrier reduction effect.
  • the potential barrier entering the barrier layer decreases as the length of the conductive channel decreases, thereby reducing the turn-on voltage of the diode, thereby reducing the conduction loss of the device; when the device is reversely conductive, due to The source electrically connected to the source trench structure is connected to a high voltage, causing the conductive channel of the MOS channel diode in the body region to open, allowing reverse current in the device to pass through the MOS channel
  • the conductive channel transmission in the diode reduces the reverse current flowing through the body region 15, inhibits the turn-on of the body diode in the device, and eliminates bipolar degradation.
  • the process of forming the source trench, the second dielectric layer and the conductive layer is compatible with the process of forming the gate structure, without the need for complex processes, the preparation process is simple, and has high industrial utilization value.
  • Figure 1 shows a schematic cross-sectional structural diagram of the power MOSFET of the present invention.
  • Figure 2 shows another schematic cross-sectional structural diagram of the power MOSFET of the present invention.
  • Figure 3 shows the barrier height variation curves of the MOS channel diode in the power MOSFET shown in Figure 1 for several different channel lengths.
  • FIG. 4 shows a process flow chart of the manufacturing method of the power MOSFET of the present invention.
  • FIG. 5 shows a schematic cross-sectional view of the semiconductor structure of the power MOSFET preparation method of the present invention.
  • FIG. 6 shows a schematic cross-sectional structural diagram of the power MOSFET preparation method after forming the source region and the contact region.
  • FIG. 7 shows a schematic cross-sectional structural diagram of the power MOSFET preparation method after forming an electric field shielding layer according to the present invention.
  • FIG. 8 is a schematic diagram showing a cross-sectional structure of a method for manufacturing a power MOSFET of the present invention after forming a gate structure.
  • FIG. 9 shows a schematic cross-sectional structural diagram after forming a barrier layer in the preparation method of the power MOSFET of the present invention.
  • FIG. 10 shows another schematic cross-sectional structural diagram after forming a barrier layer in the preparation method of the power MOSFET of the present invention.
  • Component label description 1 Semiconductor structure 11 substrate 12 epitaxial layers 121 Drift Zone 122 Current transfer layer 13 Gate structure 131 gate trench 132 First dielectric layer 133 gate conductive layer 14 source trench structure 141 source trench structure 142 Second dielectric layer 143 source conductive layer 15 body areas 151 source area 152 contact zone 16 barrier layer 161 First conductivity type doping layer 162 Metal Barrier Contact Layer 17 upper groove 18 Electric field shielding layer 2 source 3 drain
  • FIGS 1 and 2 are respectively a schematic cross-sectional structural diagram of one power MOSFET and a schematic cross-sectional structural diagram of another power MOSFET, including a semiconductor structure 1 and a gate structure 13 , the source trench structure 14, the second conductivity type body region 15, the first conductivity type source region 151, the second conductivity type contact region 152, the barrier layer 16, the source electrode 2 and the drain electrode 3, wherein the semiconductor
  • the structure 1 includes a first conductive type substrate 11 and a first conductive type epitaxial layer 12 stacked in sequence.
  • the epitaxial layer 12 includes a first conductive type drift region 121 and a first conductive type current transfer layer 122 stacked in sequence; a plurality of The gate structures 13 are arranged at intervals, and the gate structures 13 are embedded in the current transmission layer 122; the source trench structure 14 is located between two adjacent gate structures 13. The sidewalls of the source trench structure 14 are separated from the sidewalls of the gate structure 13 by a predetermined distance. An upper trench 17 of a predetermined depth is provided above the source trench structure 14. The upper trench The sidewalls of 17 protrude beyond the sidewalls of the source trench structure 14 in the direction toward the gate structure 13; the body region 15 is located between the source trench structure 14 and the gate structure 13.
  • the upper surface layer of the current transfer layer 122, the bottom of the upper trench 17 exposes the body region 15; the plurality of source regions 151 and the plurality of contact regions 152 are located on the upper surface layer of the body region 15 , and the source region 151 located between the gate structure 13 and the upper trench 17 is adjacent to the contact region 152, and the sidewall of the source region 151 away from the contact region 152 and the gate The sidewalls of the pole structure 13 are adjacent; the barrier layer 16 is located at the bottom of the upper trench 17, and the barrier layer 16 covers the exposed surface of the body region 15 at the bottom of the upper trench 17.
  • the barrier layer 16, the body region 15, the source trench structure 14 and the current transfer layer 122 form a MOS channel diode; the source 2, the barrier layer 16 and the source region 151 , the contact region 152 and the source trench structure 14 are electrically connected, and the drain electrode 3 is electrically connected to the substrate 11 .
  • the first conductivity type includes one of N-type or P-type
  • the second conductivity type includes one of N-type or P-type
  • the first conductivity type and the second conductivity type Types of conductivity types are opposite.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the substrate 11 is made of silicon carbide, silicon germanium, silicon or other suitable semiconductor materials.
  • the substrate 11 is made of silicon carbide.
  • the material of the epitaxial layer 12 includes silicon carbide, silicon germanium, silicon or other suitable semiconductor materials.
  • the material of the epitaxial layer 12 is silicon carbide.
  • the gate structure 13 includes a gate trench 131 , a first dielectric layer 132 and a gate conductive layer 133 .
  • the first dielectric layer 132 is located on the inner wall and bottom surface of the gate trench 131 and wraps the gate conductive layer 133 .
  • the depth and opening size of the gate trench 131 can be set according to the actual situation, and there is no limit here.
  • the depth refers to the bottom surface of the gate trench 131 to distance from the upper surface of the epitaxial layer 12 .
  • the first dielectric layer 132 includes a gate dielectric layer (not shown) and an interlayer dielectric layer (not shown) located above the gate trench 131.
  • the The thickness of the gate dielectric layer can be set according to actual conditions, and is no longer limited here; the thickness of the interlayer dielectric layer can be set according to actual conditions, and is no longer limited here.
  • the thickness of the gate dielectric layer is 50 nm, and since the voltage electrically connected to the gate conductive layer 133 in the power device is lower than the voltage of the source 2 , the thickness of the gate dielectric layer is less than 50 nm.
  • the thickness of the interlayer dielectric layer is specified to prevent device breakdown and thereby ensure device performance.
  • the material of the gate dielectric layer includes silicon oxide, silicon nitride or other suitable dielectric materials
  • the material of the interlayer dielectric layer includes silicon oxide, silicon nitride or other suitable dielectric materials.
  • the gate conductive layer 133 is made of polysilicon or other suitable conductive materials.
  • the source trench structure 14 includes a source trench 141, a second dielectric layer 142 and a source conductive layer 143.
  • the second dielectric layer 142 is located on the inner wall and bottom surface of the source trench 141 and wraps around the sidewall and bottom surface of the source conductive layer 143 .
  • the depth and opening size of the source trench 141 can be set according to the actual situation, and there is no limit here.
  • the depth refers to the distance from the bottom surface of the source trench 141 to The distance between the upper surfaces of the epitaxial layer 12 .
  • the thickness of the second dielectric layer 142 can be set according to actual conditions, and is no longer limited here.
  • the thickness of the second dielectric layer 142 is 50 nm.
  • the material of the second dielectric layer 142 includes silicon oxide, silicon nitride or other suitable dielectric materials.
  • the source conductive layer 143 is made of polysilicon or other suitable conductive materials.
  • a second conductivity type electric field shielding layer 18 is provided in the current transfer layer 122 directly below the gate structure 13 and the source trench structure 14 , and the bottom surface of the electric field shielding layer 18 is in contact with the The bottom surfaces of the current transfer layer 122 are spaced apart by a preset distance.
  • the upper surface of the electric field shielding layer 18 is in contact with the bottom surfaces of the gate structure 13 and the source trench structure 14 .
  • Two adjacent electric field shielding layers 18 They are arranged at intervals, that is, the upper surface of the electric field shielding layer 18 located directly below the gate structure 13 is in contact with the lower surface of the gate structure 13 , and the electric field shielding layer 18 located directly below the source trench structure 14 is in contact with the lower surface of the gate structure 13 .
  • the upper surface of the shielding layer 18 is in contact with the lower surface of the source trench structure 14 .
  • the electric field shielding layer 18 is used to reduce the electric field strength in the first dielectric layer 131 at the bottom of the gate structure 13 and the second dielectric layer 142 at the bottom of the source trench structure 14 to protect the first dielectric layer 132 and the second dielectric layer 142 .
  • the size and thickness of the electric field shielding layer 18 can be set according to the actual situation, and there is no limit here.
  • the thickness refers to the distance from the bottom surface of the electric field shielding layer 18 to the electric field.
  • the thickness of the electric field shielding layer 18 is 0.4 ⁇ m.
  • the doping concentration of the electric field shielding layer 18 is greater than the doping concentration of the current transmission layer 122. In order to ensure device performance and the doping concentration of the electric field shielding layer 18 is higher than the doping concentration of the current transmission layer 122, In the case of doping concentration, the doping concentration of the electric field shielding layer 18 can be set according to the actual situation, and is no longer limited here. In this embodiment, the doping concentration of the electric field shielding layer 18 is 1.0 ⁇ 10 19 cm -3 .
  • the thickness and size of the body region 15 can be set according to the actual situation, which is no longer limited here.
  • the doping concentration of the body region 15 can be set according to the actual situation, which is not limited here. Restriction.
  • the thickness of the body region 15 is 0.7 ⁇ m, and the doping concentration is 1.4 ⁇ 10 17 cm -3 .
  • the size and thickness of the source region 151 can be set according to the actual situation, and there is no limit here.
  • the thickness here refers to the upper surface of the source region 151 to the source region 151 distance between lower surfaces Leave. In this embodiment, the thickness of the source region 151 is 0.2 ⁇ m.
  • the doping concentration of the source region 151 can be set according to the actual situation, and is no longer limited here.
  • the doping concentration of the source region 151 is 1.0 ⁇ 10 19 cm -3 .
  • the size and thickness of the contact area 152 can be set according to the actual situation, and there is no limit here.
  • the thickness here refers to the upper surface of the contact area 152 to the contact area 152 The distance between the lower surfaces. In this embodiment, the thickness of the contact area 152 is 0.2 ⁇ m.
  • the doping concentration of the contact region 152 can be set according to actual conditions, and is not limited here.
  • the doping concentration of the contact region 152 is 1.0 ⁇ 10 19 cm -3 .
  • the arrangement of the upper trench 17 is used to reduce the conductive channel length of the MOS channel diode in the device.
  • the conductive channel length of the MOS channel diode is adjusted by adjusting the depth of the bottom surface of the upper trench 17 .
  • the MOS channel diode is composed of the barrier layer 16 and the body region 15, the source trench structure 14 and the current transmission layer 122.
  • the bottom surface of the upper trench 17 and the The distance between the body areas 15 is the conductive channel length of the MOS channel diode.
  • the depth of the upper groove 17 can be set according to actual conditions and is not limited here.
  • the barrier layer 16 includes one of a first conductive type doping layer 161 and a metal barrier contact layer 162, and may also be other suitable barrier structures.
  • the barrier layer 16 is used to contact the body region 15 to form a barrier, and then the interior of the device is formed by the barrier layer 16, the body region 15, the source trench structure 14 and The current transfer layer 122 forms the MOS channel diode structure.
  • the barrier layer 16 is the metal barrier contact layer 162, and the bottom surface of the upper trench 17 is lower than the bottom surface of the contact area 152, so as to reduce the conductive channel of the MOS channel diode.
  • the channel length uses the leakage-induced barrier reduction effect to reduce the barrier height of the MOS channel diode, thereby reducing the turn-on voltage of the MOS channel diode and reducing the conduction loss of the device.
  • the thickness of the metal barrier contact layer 162 can be adjusted according to actual conditions while ensuring the device performance.
  • the setting is not limited here.
  • the thickness here refers to the distance from the upper surface of the metal barrier contact layer 162 to the contact surface between the metal barrier contact layer 162 and the body region 15.
  • the distance between the upper surface of the barrier layer 16 and the bottom surface of the body region 15 can be set according to the actual situation, here No more restrictions.
  • the material of the metal barrier contact layer 162 can be selected according to the actual situation, and is no longer limited here.
  • the barrier layer 16 covers the exposed surface of the source trench structure 14 at the bottom of the upper trench 17 .
  • the barrier layer 16 is the metal barrier contact layer 162
  • the barrier layer 16 covering the upper surface of the source trench structure 14 can make the source electrode 2 and the source conductive.
  • the layer 143 is electrically connected, and then the source 2 is used to control the opening of the conductive channel in the MOS channel diode in the device, that is, to control the conductivity in the body region 15 in contact with the sidewall of the source trench structure 14
  • the opening of the channel can also reduce the number of device preparation process steps and reduce production costs.
  • the metal barrier contact layer 162 may not be electrically connected to the source trench structure 14 , and the source 2 is directly electrically connected to the source conductive layer 143 in the source trench structure 14 . , the resistance value of the electrical connection between the source electrode 2 and the source conductive layer 143 can be reduced.
  • the barrier layer 16 is the first conductivity type doping layer 161 , and the lower surface of the barrier layer 16 is lower than the lower surface of the contact region 152 and spaced apart from the bottom surface of the body region 15 At a predetermined distance, the sidewalls of the barrier layer 16 are adjacent to the sidewalls of the source trench structure 14 .
  • the lower surface of the barrier layer 16 is lower than the lower surface of the contact region 152 and the barrier layer 16 covers the exposed surface of the body region 15 at the bottom of the upper trench 17
  • the position of the upper surface of the barrier layer 16 can be set according to the actual situation, and is no longer limited here.
  • the thickness and size of the first conductive type doped layer 161 can be set according to actual conditions, and are no longer limited here.
  • the thickness and width of the first conductive type doped layer 161 are both 0.2 ⁇ m. The width here means that the first conductive type doped layer 161 is close to the gate structure 13 and the The distance between the two sidewalls of the source trench structure 14 .
  • the doping concentration of the barrier layer 16 is higher than that of the current transfer layer 122 , that is, the doping concentration of the first conductive type doped layer 161 is higher than that of the current transfer layer 122 . doping concentration.
  • the doping concentration of the first conductive type doping layer 161 is 1.0 ⁇ 10 19 cm -3 .
  • the first conductive type doping layer 161 forms an ohmic contact with the source electrode 2 to reduce the contact resistance of the MOS channel diode in the device.
  • the doping concentration of the first conductive type doping layer 161 can be set according to actual conditions, and is no longer limited here.
  • the material of the source electrode 2 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may also be other suitable conductive materials.
  • the material of the drain electrode 3 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may also be other suitable conductive materials.
  • the conductive channel length of the MOS channel diode in the device is reduced.
  • the leakage-induced barrier reduction effect as the conductive channel length is reduced, electrons pass through The height of the barrier entering the barrier layer 16 through the body region is reduced, thereby reducing the turn-on voltage of the MOS channel diode in the device.
  • the source 2 electrically connected to 14 is connected to a high voltage, causing the conductive channel of the MOS channel diode in the body region 15 to open, allowing the reverse current in the device to pass through the conductive channel in the MOS channel diode.
  • the reverse conduction capability of the device is improved, while the device has a larger breakdown voltage and lower gate charge characteristics, and does not degrade the device. other electrical properties.
  • the doping concentration of the substrate 11 in the device is 1.0 ⁇ 10 19 cm -3 and a thickness of 2 ⁇ m;
  • the drift region 121 has a doping concentration of 8.0 ⁇ 10 15 cm -3 and a thickness of 10 ⁇ m;
  • the current transfer layer 122 has a doping concentration of 6.0 ⁇ 10 16 cm -3 , the thickness is 2 ⁇ m;
  • the doping concentration of the electric field shielding layer 18 is 1.0 ⁇ 10 19 cm -3 , and the thickness is 0.4 ⁇ m;
  • the thickness of the gate dielectric layer and the second dielectric layer 142 is 50 nm;
  • the doping concentration of the body region 15 is 1.4 ⁇ 10 17 cm -3 , the thickness is 0.7 ⁇ m, and the width is 0.8 ⁇ m (the width here refers to the sidewall of the gate structure 13 to the sidewall 14 of the source trench structure
  • L Chd in the figure represents the conductive channel length of the MOS channel diode
  • the horizontal axis Y is the distance that the upper surface of the first conductive type doped layer 161 extends toward the epitaxial layer 12
  • 0 ⁇ m is the position of the upper surface of the first conductive type doped layer 161
  • 0.7 ⁇ m is the body.
  • the power MOSFET of this embodiment is configured by disposing a source trench structure 14 between two adjacent gate structures 13 , and the sidewalls of the gate structure 13 are in contact with the source trench structure 14 The sidewalls are spaced apart by a predetermined distance.
  • the source trench structure 14 includes the source trench 141, the second dielectric layer 142 and the source conductive layer 143, and is located in the source trench structure.
  • the upper trench 17 is provided above 14. The sidewalls of the upper trench 17 extend toward the gate structure 13 to a predetermined distance from the sidewalls of the source trench structure 14, and the upper trench 17 The bottom surface of the trench 17 exposes the body region 15, and the barrier layer 16 is provided at the bottom of the upper trench 17 to form the barrier layer 16, the body region 15, and the source electrode.
  • the MOS channel diode composed of the trench structure 14 and the current transfer layer 122 reduces the conductive channel length of the MOS channel diode by deepening the depth of the upper trench 17, and the drain barrier is reduced.
  • the effect causes the barrier height for electrons to pass through the body region 15 and enter the barrier layer 16 to be reduced, thereby reducing the turn-on voltage of the MOS channel diode.
  • the source conductive layer 143 in the source trench structure 14 is electrically connected to the source 2, when the device is reversely conductive, the source conductive layer 143 is connected to a high voltage, causing the source trench to be The conductive channel adjacent to the trench structure 14 and the body region 15 is opened, thereby allowing the device to transmit reverse current through the MOS channel diode, and at the same time, the current flowing through the body region 15 is reduced, inhibiting the body region. Turning on the body diode formed by the region 15 and the current transfer layer 122 eliminates the bipolar degradation of the device.
  • This embodiment provides a method for manufacturing a power MOSFET. As shown in Figure 4, which is a process flow chart of the method for manufacturing a power MOSFET, it includes the following steps:
  • S1 Provide a semiconductor layer, the semiconductor layer includes a first conductive type substrate and a first conductive type epitaxial layer, the epitaxial layer includes a first conductive type drift region and a first conductive type current transmission layer stacked in sequence;
  • S2 Form a second conductive type body region with a predetermined thickness on the upper surface layer of the current transmission layer, and form a plurality of alternately arranged first conductive type source regions and second conductive type contact regions on the upper surface layer of the body region, And the side walls of the source region and the contact region are adjacent to each other;
  • S3 Form a plurality of gate structures and source trench structures that are alternately arranged and spaced apart at a predetermined distance in the current transfer layer.
  • the gate structures penetrate the source region and the body region.
  • the source electrode The groove structure penetrates the body area and the contact area;
  • S4 Etch the source trench structure to obtain an upper trench located above the source trench structure.
  • the sidewalls of the upper trench protrude from the source trench in the direction toward the gate structure.
  • the sidewalls of the structure, the bottom of the upper trench exposing the body region;
  • S5 Form a barrier layer at the bottom of the upper trench.
  • the barrier layer covers the exposed surface of the body region at the bottom of the upper trench.
  • the barrier layer is connected with the body region and the source.
  • the pole trench structure and the current transmission layer form a MOS channel diode Tube;
  • S6 Form a source electrode electrically connected to the barrier layer, the source region, the contact region and the source trench structure, and form a drain electrode electrically connected to the substrate.
  • step S1 and step S2 are performed: providing a semiconductor structure 1 , the semiconductor structure 1 including a first conductive type substrate 11 and a first conductive type epitaxial layer 12 .
  • the layer 12 includes a first conductive type drift region 121 and a first conductive type current transmission layer 122 stacked in sequence; a second conductive type body region 15 with a predetermined thickness is formed on the upper surface of the current transmission layer 122.
  • a plurality of alternately arranged first conductivity type source regions 151 and second conductivity type contact regions 152 are formed on the surface layer of the region 15 , and the side walls of the source regions 151 and the contact regions 152 are adjacent to each other.
  • the thickness of the substrate 11 can be set according to the actual situation while ensuring device performance, and is no longer limited here; the substrate The doping concentration of 11 can be set according to the actual situation and is no longer limited here.
  • the doping concentration of the substrate 11 is 1.0 ⁇ 10 19 cm -3 and the thickness is 2 ⁇ m.
  • the thickness of the drift region 121 can be set according to the actual situation, and is no longer limited here; the doping concentration of the drift region 121 can be set according to the actual situation, and is no longer limited here. .
  • the doping concentration of the drift region 121 is 8.0 ⁇ 10 15 cm -3 and the thickness is 10 ⁇ m.
  • the thickness of the current transmission layer 122 can be set according to the actual situation, and is no longer limited here; the doping concentration of the current transmission layer 122 can be set according to the actual situation, which is not limited here. Restriction.
  • the doping concentration of the current transmission layer 122 is 6.0 ⁇ 10 16 cm -3 and the thickness is 2 ⁇ m.
  • FIG. 6 it is a schematic cross-sectional structural diagram after forming the body region 15 , the source region 151 and the contact region 152 .
  • the method of forming the body region 15 includes ion implantation or other suitable methods. .
  • the method of forming the source region 151 includes ion implantation or other suitable methods.
  • the method of forming the contact region 152 includes ion implantation or other suitable methods.
  • the step S4 and the step S5 forming a plurality of gate structures 13 and source electrodes that are alternately arranged and spaced apart by a predetermined distance in the current transmission layer.
  • Trench structure 14, the gate structure 13 penetrates the source region 151 and the body region 15, the source trench structure 14 penetrates the body region 15 and the contact region 152; etching the source
  • the electrode trench structure 14 is formed to obtain an upper trench 17 located above the source trench structure 14. The sidewalls of the upper trench 17 protrude beyond the source trench structure 14 in the direction toward the gate structure 13.
  • the sidewalls of the upper trench 17 expose the body region 15 ; a barrier layer 16 is formed at the bottom of the upper trench 17 , and the barrier layer 16 covers the bottom of the upper trench 17
  • the exposed surface of the body region 15 , the barrier layer 16 and the body region 15 , and the source trench structure 14 and the current transmission layer 122 form a MOS channel diode.
  • the gate structure 13 includes a gate trench 131, a first dielectric layer 132 and a gate conductive layer 133.
  • the first dielectric layer 132 is located on the inner wall and bottom surface of the gate trench 131 and wraps it. the gate conductive layer 133 .
  • the first dielectric layer 132 includes a gate dielectric layer located on the inner wall and bottom surface of the gate trench 131 and an interlayer dielectric layer covering the upper surface of the gate dielectric layer and the gate conductive layer.
  • the source trench structure 14 includes a source trench 141, a second dielectric layer 142 and a source conductive layer 143.
  • the second dielectric layer 142 is located on the inner wall and bottom surface of the source trench 141. Wrap the sidewalls and bottom surface of the source conductive layer 143 .
  • forming the gate structure 13 includes the following steps: forming a layer of patterned light on the upper surface of the epitaxial layer 12 . Resist layer, and form the gate trench 131 based on the patterned photoresist layer; form a gate dielectric layer on the inner wall and bottom surface of the gate trench 131, and form a gate dielectric layer to fill the gate electrode
  • the gate conductive layer 133 of the trench 131 forms an interlayer dielectric layer covering the gate dielectric layer and the upper surface of the gate conductive layer 133 on the upper surface of the epitaxial layer 12 to obtain the gate structure 13 .
  • the source trench 141 may be formed simultaneously with the gate trench 131 , may be formed after the gate structure 13 is formed, or may be formed before the gate structure 13 is formed.
  • Trench 141 and when the source trench is formed before the gate structure, it is necessary to form the source trench 141, the second dielectric layer 142 and the source conductive layer 143 before forming them.
  • the gate trench 131 is described.
  • the epitaxial layer 12 is etched to simultaneously form the gate trench 131 and the source trench 141 .
  • the gate dielectric layer and the second dielectric layer 142 may be formed simultaneously or in separate steps. In this embodiment, in order to reduce process steps, the gate dielectric layer and the second dielectric layer 142 are formed simultaneously.
  • the gate conductive layer 133 and the source conductive layer 143 may be formed simultaneously or in separate steps.
  • the gate conductive layer 133 and the source conductive layer 14 are formed simultaneously to reduce process steps and save costs.
  • the method of forming the gate trench 131 includes dry etching, wet etching or other suitable etching methods.
  • the method of forming the gate dielectric layer includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods; the method of forming the second dielectric layer 142 includes chemical vapor deposition, physical vapor deposition, thermal oxidation. oxidation method or other suitable method.
  • the method of forming the gate conductive layer 133 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the method; the method of forming the source conductive layer 143 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the interlayer dielectric layer also covers the upper surface of the epitaxial layer (the source region and the contact region).
  • the method of forming the interlayer dielectric layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the method of forming the source trench 141 includes dry etching, wet etching or other suitable etching methods.
  • FIG. 7 it is a schematic cross-sectional structural diagram after forming the electric field shielding layer 18 .
  • the first dielectric layer 132 is formed.
  • the second dielectric layer 142 it also includes forming a second conductive type electric field shielding layer 18 in the current transfer layer 122 directly below the bottom surface of the gate trench 131 and the source trench 141 A step of.
  • the method of forming the electric field shielding layer 18 includes ion implantation or other suitable methods.
  • the method of forming the upper trench 17 includes dry etching, wet etching or other suitable methods.
  • FIG. 9 and FIG. 10 are respectively a schematic cross-sectional structural diagram after forming the barrier layer 16 and another schematic cross-sectional structural diagram after forming the barrier layer 16 .
  • the barrier layer 16 includes a first conductive type doping layer 161 and a metal barrier contact layer 162.
  • the method of forming the barrier layer 16 includes ion implantation, chemical vapor deposition, physical vapor deposition or other suitable methods.
  • an ion implantation method is used to form the barrier layer 16 in the body region 15 at the bottom of the upper trench 17 .
  • the method of forming the barrier layer 16 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular Beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
  • the step S6 is performed: forming a source 2 electrically connected to the barrier layer 16 , the source region 151 , the contact region 152 and the source trench structure 14 , and forming a drain 3 electrically connected to the substrate 11 .
  • the method for forming the source electrode 2 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods. .
  • the source electrode 2 fills the upper trench 17 and is electrically connected to the source conductive layer 143 directly or through a conductive material.
  • Figures 1 and 2 they are respectively a schematic cross-sectional structural diagram after forming the drain electrode 3 and another schematic cross-sectional structural diagram after forming the drain electrode 3.
  • the structure of the drain electrode 3 is formed. Methods include sputtering, physical vapor deposition, Chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
  • the source trench 141 , the second dielectric layer 142 and the source conductive layer 143 can be formed simultaneously with the gate trench 131 , the gate dielectric layer and the gate conductive layer 133 , compared with the process of forming a dual-trench MOSFET, only the steps of forming the upper trench 17 and the barrier layer 16 are added, and the process of forming the upper trench 17 and the barrier layer 16 is simple.
  • the MOS channel diode can then reduce the barrier height between the barrier layer 16 and the body region 15 in the device, reduce the turn-on voltage of the MOS channel diode, and then reduce the conduction loss of the device.
  • the source conductive layer 143 is electrically connected to the source electrode 2, causing the conductive channel in the body region 15 adjacent to the source trench structure 14 to open, utilizing conductive
  • the channel transmits reverse current, suppresses the turning on of the body diode in the device, and improves the device's reverse current conduction capability, and the preparation process is simple.
  • the power MOSFET in this embodiment is fabricated by forming an upper trench 17 with a predetermined depth above the source trench structure 14 and forming a layer in the upper trench 17 covering the body region 15
  • the barrier layer 16 is used to form a MOS channel diode by using the barrier layer 16, the body region 15, the source trench structure 14 and the current transfer layer 122.
  • the depth of the above-mentioned trench 17 is used to reduce the length of the conductive channel in the MOS channel diode, thereby reducing the turn-on voltage of the MOS channel diode and reducing the conduction loss of the device without adding complicated process steps. , the preparation method is simple.
  • the power MOSFET and its preparation method of the present invention set a source trench structure at a preset distance from the gate structure between two adjacent gate structures, and set it above the source trench structure.
  • the sidewalls of the upper trench protrude toward the gate structure and are spaced a predetermined distance from the sidewalls of the source trench structure.
  • the bottom surface of the upper trench exposes the body region, forming a potential barrier at the bottom of the upper trench. layer to obtain a MOS channel diode composed of a barrier layer, a body region, a current transmission layer and a source trench structure.
  • the depth of the upper trench is used to control the conductive channel length of the MOS channel diode.
  • the conductive channel length of the channel diode is used to reduce the barrier height for electrons to pass through the body region and enter the barrier layer, thereby reducing the turn-on voltage of the MOS channel diode, thereby reducing the conduction loss of the device; when the device is reversely conductive, due to the source Electrically connected to the source conductive layer, causing the conductive channel in the body region close to the source trench structure to open, the reverse current in the device is transmitted from the conductive channel of the MOS channel diode, and the reverse current through the body region is reduced , suppressing the turn-on of the body diode in the device, eliminating bipolar degradation, improving the reverse current transmission capability of the device, and the process of forming the source trench, the second dielectric layer and the source conductive layer is the same as the process of forming the gate structure
  • the process is synchronized, and the process of forming the upper trench and the barrier layer is simple, no complicated process is required, and the process steps are simple. Therefore, the present invention effectively overcomes various

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Abstract

本发明提供一种功率MOSFET及其制备方法，该功率MOSFET包括半导体结构、栅极结构、源极沟槽结构、体区、源区、接触区、势垒层、源极及漏极，其中，半导体层包括衬底、漂移区及电流传输层；栅极结构嵌于电流传输层中；源极沟槽结构位于相邻两个栅极结构之间且上方设有上沟槽；体区位于电流传输层上表层，上沟槽底部显露出体区；源区与接触区位于体区上表层且相互邻接；势垒层位于上沟槽底部且覆盖体区；源极与势垒层及源极沟槽结构电接触，漏极与衬底电接触。本发明通过于相邻两个栅极结构之间设置源极沟槽结构及位于源极沟槽结构上方且显露体区的上沟槽，并于上沟槽底部设置势垒层，降低器件正向导通损耗并提升器件反向电流导通能力。

Description

一种功率MOSFET及其制备方法 技术领域
本发明属于半导体集成电路制造领域，涉及一种功率MOSFET及其制备方法。
背景技术
碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)具有导通损耗小、开关速度快、开关损耗低、抗辐照性能强、高温稳定性好等特点，成为备受关注的下一代功率半导体器件。因此，使用SiC功率器件的电源转换系统具有更高的转化效率、更小的封装体积和重量以及更低的系统成本。在电源转换系统中，需要在功率器件外部反向并联快恢复二极管作续流二极管使用，然而外接二极管无疑会增加系统的体积并引入额外的寄生电感。此外，由于SiC材料具有较大的禁带宽度，导致PN结体二极管也具有较大的开启电压(室温下接近3V)，相较于硅基功率器件体二极管0.7V的开启电压，MOSFET体二极管作续流二极管使用会产生较大的导通损耗。且由于SiC晶体存在基底面位错，在双极运行期间，电子与空穴的复合会使堆垛层错从基底面位错处蔓延，从而增加器件的导通电阻、降低器件的可靠性。因此，在SiC MOSFET中，SiC寄生体二极管不宜作续流二极管使用。
目前，通常于SiC MOSFET集成结势垒二极管或肖特基势垒二极管，利用低开启电压的结势垒二极管或肖特基势垒二极管传输反向电流，但在器件关态时，这类二极管具有较大的漏电，尤其是高温情况下，较大的漏电严重影响器件的可靠性。也可以在SiC MOSFET中集成异质结二极管，抑制SiC体二极管的同时保持较小的关态漏电流，但器件内部制作异质结会增加工艺复杂度和成本。而在SiC MOSFET中集成内建金属氧化物半导体(MOS)沟道二极管的方案虽然不会显著增加器件的关态漏电和工艺成本，但为了使集成的MOS沟道二极管具有更低的开启电压，通常在MOS沟道一侧处降低栅氧化层的厚度或采用外延浓度较低的N型层，这也会影响器件的可靠性。
因此，亟需寻找一种可靠性高且具有低开启电压的集成体二极管的功率SiC MOSFET。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种功率MOSFET及其制备方法，用于解决现有技术中功率MOSFET中集成体二极管的开启电压高、器件的可靠性差的问题。
为实现上述目的及其他相关目的，本发明提供了一种功率MOSFET，包括：
半导体结构，包括依次层叠的第一导电类型衬底及第一导电类型外延层，所述外延层包括依次层叠的第一导电类型漂移区及第一导电类型电流传输层；
多个间隔设置的栅极结构，嵌于所述电流传输层中；
源极沟槽结构，位于相邻两个所述栅极结构之间，所述源极沟槽结构的侧壁与所述栅极结构的侧壁间隔预设距离，所述源极沟槽结构的上方设有预设深度的上沟槽，所述上沟槽的侧壁沿朝向所述栅极结构的方向突出于所述源极沟槽结构的侧壁；
第二导电类型体区，位于所述源极沟槽结构与所述栅极结构之间的所述电流传输层的上表层，所述上沟槽的底部显露出所述体区；
多个第一导电类型源区及第二导电类型接触区，所述源区与所述接触区均位于所述体区的上表层，且位于所述栅极结构与所述上沟槽之间的所述源区与所述接触区邻接，所述源区远离所述接触区的侧壁与所述栅极结构的侧壁邻接；
势垒层，位于所述上沟槽的底部，所述势垒层覆盖所述上沟槽底部的所述体区的显露表面，所述势垒层与所述体区、所述源极沟槽结构及所述电流传输层组成MOS沟道二极管；
源极及漏极，所述源极与所述势垒层、所述源区、所述接触区及所述源极沟槽结构电连接，所述漏极与所述衬底电连接。
可选地，所述栅极结构包括栅极沟槽、第一介电层及栅导电层，所述第一介电层位于所述栅极沟槽的内壁及底面且包裹所述栅导电层；所述源极沟槽结构包括源极沟槽、第二介电层及源导电层，所述第二介电层位于所述源极沟槽的内壁及底面并包裹所述源导电层的侧壁及底面。
可选地，所述栅极结构及所述源极沟槽结构正下方的所述电流传输层中设有第二导电类型电场屏蔽层，所述电场屏蔽层的底面与所述电流传输层的底面间隔预设距离，所述电场屏蔽层的上表面与所述栅极结构及所述源极沟槽结构的底面接触，相邻两个所述电场屏蔽层间隔设置。
可选地，通过调整所述上沟槽的底面的深度来调整所述MOS沟道二极管的导电沟道长度。
可选地，所述势垒层包括第一导电类型掺杂层及金属势垒接触层中的一种。
可选地，所述势垒层为所述金属势垒接触层，所述上沟槽的底面低于所述接触区的底面。
可选地，所述势垒层覆盖所述上沟槽底部的所述源极沟槽结构显露表面。
可选地，所述势垒层为所述第一导电类型掺杂层，所述势垒层的下表面低于所述接触区的下表面且与所述体区的底面间隔预设距离，所述势垒层的侧壁与所述源极沟槽结构的侧壁 邻接。
可选地，所述势垒层的掺杂浓度高于所述电流传输层的掺杂浓度。
本发明还提供了一种功率MOSFET的制备方法，包括以下步骤：
提供一半导体层，所述半导体层包括第一导电类型衬底及第一导电类型外延层，所述外延层包括依次层叠的第一导电类型漂移区及第一导电类型电流传输层；
于所述电流传输层的上表层形成预设厚度的第二导电类型体区，于所述体区上表层形成多个交替设置的第一导电类型源区和第二导电类型接触区，且所述源区与所述接触区的侧壁相互邻接；
于所述电流传输层中形成多个交替设置且间隔预设距离的栅极结构和源极沟槽结构，所述栅极结构贯穿所述源区及所述体区，所述源极沟槽结构贯穿所述体区及所述接触区；
刻蚀所述源极沟槽结构以得到位于源极沟槽结构上方的沟槽，所述上沟槽的侧壁沿朝向所述栅极结构的方向突出于所述源极沟槽结构的侧壁，所述上沟槽的底部显露出所述体区；
于所述上沟槽的底部形成势垒层，所述势垒层覆盖所述上沟槽底部的所述体区的显露表面，所述势垒层与所述体区、所述源极沟槽结构及所述电流传输层组成MOS沟道二极管；
形成与所述势垒层、所述源区、所述接触区及所述源极沟槽结构电连接的源极，形成与所述衬底电连接的漏极。
如上所述，本发明的功率MOSFET及其制备方法通过于相邻两个所述栅极结构之前设置所述源极沟槽结构及位于所述源极沟槽结构上方的所述上沟槽，且所述上沟槽的侧壁朝向所述栅极结构方向延伸至距离所述源极沟槽结构侧壁预设距离处，并于所述上沟槽的底部形成所述势垒层，所述势垒层的覆盖所述沟道底面的所述体区的显露表面，通过调整所述上沟槽的深度，减小所述势垒层底面到所述体区底面之间的距离，以减小由所述势垒层、所述体区、所述源极沟槽结构构成的所述MOS二极管结构中的导电沟道长度，由于漏诱生势垒降低效应，使电子穿过器件的所述体区，进入所述势垒层的势垒随着导电沟道长度的减小而降低，继而降低了二极管的开启电压，继而降低器件的导通损耗；在器件反向导通时，由于与所述源极沟槽结构电连接的所述源极连接高电压，导致所述体区中所述MOS沟道二极管的导电沟道打开，使器件中的反向电流通过所述MOS沟道二极管中的导电沟道传输，减小了流经所述体区15的反向电流，抑制了器件中的体二极管的开启，消除了双极退化。此外，形成所述源极沟槽、所述第二介电层及所述导电层的工艺与形成所述栅极结构的工艺兼容，无需复杂的工艺，制备工艺简单，具有高度产业利用价值。
附图说明
图1显示为本发明的功率MOSFET的一种剖面结构示意图。
图2显示为本发明的功率MOSFET的另一种剖面结构示意图。
图3显示为几种不同沟道长度的图1所示的功率MOSFET中MOS沟道二极管的势垒高度变化曲线。
图4显示为本发明的功率MOSFET的制备方法的工艺流程图。
图5显示为本发明的功率MOSFET的制备方法的半导体结构的剖面结构示意图。
图6显示为本发明的功率MOSFET的制备方法的形成源区及接触区后的剖面结构示意图。
图7显示为本发明的功率MOSFET的制备方法的形成电场屏蔽层后的剖面结构示意图。
图8显示为本发明的功率MOSFET的制备方法的形成栅极结构后的剖面结构示意图。
图9显示为本发明的功率MOSFET的制备方法的形成势垒层后的一种剖面结构示意图。
图10显示为本发明的功率MOSFET的制备方法的形成势垒层后的另一种剖面结构示意图。
元件标号说明
1                  半导体结构
11                 衬底
12                 外延层
121                漂移区
122                电流传输层
13                 栅极结构
131                栅极沟槽
132                第一介电层
133                栅导电层
14                 源极沟槽结构
141                源极沟槽
142                第二介电层
143                源导电层
15                 体区
151                源区
152                接触区
16                 势垒层
161                第一导电类型掺杂层
162                金属势垒接触层
17                 上沟槽
18                 电场屏蔽层
2                  源极
3                  漏极
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图10。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本实施例提供一种功率MOSFET，如图1及图2所示，分别为一种所述功率MOSFET的剖面结构示意图及另一种功率MOSFET的剖面结构示意图，包括半导体结构1、栅极结构13、源极沟槽结构14、第二导电类型体区15、第一导电类型源区151、第二导电类型接触区152、势垒层16、源极2及漏极3，其中，所述半导体结构1包括依次层叠的第一导电类型衬底11及第一导电类型外延层12，所述外延层12包括依次层叠的第一导电类型漂移区121及第一导电类型电流传输层122；多个所述栅极结构13间隔设置，且所述栅极结构13嵌于所述电流传输层122中；所述源极沟槽结构14位于相邻两个所述栅极结构13之间，所述源极沟槽结构14的侧壁与所述栅极结构13的侧壁间隔预设距离，所述源极沟槽结构14的上方设有预设深度的上沟槽17，所述上沟槽17的侧壁沿朝向所述栅极结构13的方向突出于所述源极沟槽结构14的侧壁；所述体区15位于所述源极沟槽结构14与所述栅极结构13之间的所 述电流传输层122的上表层，所述上沟槽17的底部显露出所述体区15；多个所述源区151与多个所述接触区152均位于所述体区15的上表层，且位于所述栅极结构13与所述上沟槽17之间的所述源区151与所述接触区152邻接，所述源区151远离所述接触区152的侧壁与所述栅极结构13的侧壁邻接；所述势垒层16位于所述上沟槽17的底部，所述势垒层16覆盖所述上沟槽17底部的所述体区15的显露表面，所述势垒层16与所述体区15、所述源极沟槽结构14及所述电流传输层122组成MOS沟道二极管；所述源极2与所述势垒层16、所述源区151、所述接触区152及所述源极沟槽结构14电连接，所述漏极3与所述衬底11电连接。
具体的，所述第一导电类型包括N型或者P型中的一种，所述第二导电类型包括N型或者P型中的一种，且所述第一导电类型与所述第二导电类型的导电类型相反。本实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
具体的，所述衬底11的材质包括碳化硅、硅锗、硅或者其他适合的半导体材料。本实施例中，所述衬底11的材质为碳化硅。
具体的，所述外延层12的材质包括碳化硅、硅锗、硅或者其他适合的半导体材料。本实施例中，所述外延层12的材质为碳化硅。
作为示例，所述栅极结构13包括栅极沟槽131、第一介电层132及栅导电层133，所述第一介电层132位于所述栅极沟槽131的内壁及底面且包裹所述栅导电层133。
具体的，在保证器件性能的情况下，所述栅极沟槽131的深度及开口尺寸可以根据实际情况进行设置，这里不再限制，这里的深度是指所述栅极沟槽131的底面到所述外延层12上表面的距离。
具体的，所述第一介电层132包括栅介质层(未图示)及位于所述栅极沟槽131上方的层间介质层(未图示)，在保证器件性能的情况下，所述栅介质层的厚度可以根据实际情况进行设置，这里不再限制；所述层间介质层的厚度可以根据实际情况进行设置，这里不再限制。本实施例中，所述栅介质层的厚度为50nm，且由于功率器件中与所述栅导电层133电连接的电压低于所述源极2的电压，所述栅介质层的厚度小于所述层间介质层的厚度，以防止器件击穿，继而保证器件的性能。
具体的，所述栅介质层的材质包括氧化硅、氮化硅或者其他适合的介电材料；所述层间介质层的材质包括氧化硅、氮化硅或者其他适合的介电材料。
具体的，所述栅导电层133的材质包括多晶硅或者其他适合的导电材料。
作为示例，所述源极沟槽结构14包括源极沟槽141、第二介电层142及源导电层143， 所述第二介电层142位于所述源极沟槽141的内壁及底面且包裹所述源导电层143的侧壁及底面。
具体的，在保证器件性能的情况下，所述源极沟槽141的深度及开口尺寸可以根据实际情况进行设置，这里不再限制，这里的深度是指所述源极沟槽141的底面到所述外延层12的上表面之间的距离。
具体的，在保证器件性能的情况下，所述第二介电层142的厚度可以根据实际情况进行设置，这里不再限制。本实施例中，所述第二介电层142的厚度为50nm。
具体的，所述第二介电层142的材质包括氧化硅、氮化硅或者其他适合的介电材料。
具体的，所述源导电层143的材质包括多晶硅或者其他适合的导电材料。
作为示例，所述栅极结构13及所述源极沟槽结构14正下方的所述电流传输层122中设有第二导电类型电场屏蔽层18，所述电场屏蔽层18的底面与所述电流传输层122的底面间隔预设距离，所述电场屏蔽层18的上表面与所述栅极结构13及所述源极沟槽结构14的底面接触，相邻两个所述电场屏蔽层18间隔设置，即位于所述栅极结构13正下方的所述电场屏蔽层18的上表面与所述栅极结构13的下表面接触，位于所述源极沟槽结构14正下方的所述电场屏蔽层18的上表面与所述源极沟槽结构14的下表面接触。
具体的，所述电场屏蔽层18用于降低所述栅极结构13底部的所述第一介电层131及所述源极沟槽结构14底部的所述第二介电层142中的电场强度，以保护所述第一介电层132及所述第二介电层142。
具体的，在保证器件性能的情况下，所述电场屏蔽层18的尺寸及厚度可以根据实际情况进行设置，这里不再限制，这里的厚度是指所述电场屏蔽层18的底面到所述电场屏蔽层18的上表面之间的距离。本实施例中，所述电场屏蔽层18的厚度为0.4μm。
具体的，所述电场屏蔽层18的掺杂浓度大于所述电流传输层122的掺杂浓度，在保证器件性能及所述电场屏蔽层18的掺杂浓度高于所述电流传输层122的掺杂浓度的情况下，所述电场屏蔽层18的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述电场屏蔽层18的掺杂浓度为1.0×1019cm-3。
具体的，在保证器件性能的情况下，所述体区15的厚度及尺寸可以根据实际情况进行设置，这里不再限制，所述体区15的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述体区15的厚度为0.7μm，掺杂浓度为1.4×1017cm-3。
具体的，在保证器件性能的情况下，所述源区151的尺寸及厚度可以根据实际情况进行设置，这里不再限制，这里的厚度是指所述源区151上表面到所述源区151下表面之间的距 离。本实施例中，所述源区151的厚度为0.2μm。
具体的，在保证器件性能及所述源区151与所述源极2形成欧姆接触区的情况下，所述源区151的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述源区151的掺杂浓度为1.0×1019cm-3。
具体的，在保证器件性能的情况下，所述接触区152的尺寸及厚度可以根据实际情况进行设置，这里不再限制，这里的厚度是指所述接触区152上表面到所述接触区152下表面之间的距离。本实施例中，所述接触区152的厚度为0.2μm。
具体的，在保证器件性能及所述接触区152与所述源极2形成欧姆接触的情况下，所述接触区152的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述接触区152的掺杂浓度为1.0×1019cm-3。
具体的，所述上沟槽17的设置用于减小器件中的所述MOS沟道二极管的导电沟道长度。
作为示例，通过调整所述上沟槽17的底面的深度来调整所述MOS沟道二极管的导电沟道长度。
具体的，所述MOS沟道二极管由所述势垒层16与所述体区15、所述源极沟槽结构14及所述电流传输层122组成，所述上沟槽17的底面与所述体区15之间的距离即为所述MOS沟道二极管的导电沟道长度，通过调整所述上沟槽17的底面深度就可以调整所述上沟槽17的底面到所述体区15的底面之间的距离，继而可以调整所述MOS沟道二极管的导电沟道长度。
具体的，在保证器件性能的情况下，所述上沟槽17的深度可以根据实际情况进行设置，这里不再限制。
作为示例，所述势垒层16包括第一导电类型掺杂层161及金属势垒接触层162中的一种，也可以是其他适合的势垒结构。
具体的，利用所述势垒层16与所述体区15接触形成势垒，继而使器件的内部形成由所述势垒层16、所述体区15、所述源极沟槽结构14及所述电流传输层122组成的所述MOS沟道二极管结构。
作为示例，所述势垒层16为所述金属势垒接触层162，所述上沟槽17的底面低于所述接触区152的底面，以便于减小所述MOS沟道二极管的导电沟道长度，利用漏诱生势垒降低效应降低所述MOS沟道二极管的势垒高度，继而降低所述MOS沟道二极管的开启电压，降低器件的导通损耗。
具体的，在保证器件性能的情况下，所述金属势垒接触层162的厚度可以根据实际情况 进行设置，这里不再限制，这里的厚度是指所述金属势垒接触层162的上表面到所述金属势垒接触层162与所述体区15的接触面之间的距离。
具体的，在保证所述MOS沟道二极管具有足够低的开启电压的情况下，所述势垒层16的上表面到所述体区15的底面之间的距离可以根据实际情况进行设置，这里不再限制。
具体的，在保证所述金属势垒接触层162与所述体区15形成肖特基接触的情况下，所述金属势垒接触层162的材质可以根据实际情况进行选择，这里不再限制。
作为示例，所述势垒层16覆盖所述上沟槽17底部的所述源极沟槽结构14显露表面。
具体的，由于所述势垒层16为所述金属势垒接触层162，所述势垒层16覆盖所述源极沟槽结构14的上表面可以使所述源极2与所述源导电层143电连接，继而利用所述源极2控制器件中所述MOS沟道二极管中导电沟道的开启，即控制与所述源极沟槽结构14侧壁接触所述体区15中的导电沟道的开启，同时也可以减少的器件的制备工艺步骤，降低制作成本。
具体的，所述金属势垒接触层162也可以不与所述源极沟槽结构14电连接，所述源极2直接与所述源极沟槽结构14中所述源导电层143电连接，可以降低所述源极2与所述源导电层143之间电连接的电阻值。
作为示例，所述势垒层16为所述第一导电类型掺杂层161，所述势垒层16的下表面低于所述接触区152的下表面且与所述体区15的底面间隔预设距离，所述势垒层16的侧壁与所述源极沟槽结构14的侧壁邻接。
具体的，在保证所述势垒层16的下表面低于所述接触区152的下表面，且所述势垒层16覆盖所述上沟槽17底部的所述体区15显露表面的情况下，所述势垒层16的上表面的位置可以根据实际情况进行设置，这里不再限制。
具体的，在保证器件性能的情况下，所述第一导电类型掺杂层161的厚度及尺寸可以根据实际情况进行设置，这里不再限制。本实施例中，所述第一导电类型掺杂层161的厚度及宽度均为0.2μm，这里的宽度是指所述第一导电类型掺杂层161分别靠近所述栅极结构13与所述源极沟槽结构14的两个侧壁之间的距离。
作为示例，所述势垒层16的掺杂浓度高于所述电流传输层122的掺杂浓度，即所述第一导电类型掺杂层161的掺杂浓度高于所述电流传输层122的掺杂浓度。本实施例中，所述第一导电类型掺杂层161的掺杂浓度为1.0×1019cm-3。
具体的，所述第一导电类型掺杂层161与所述源极2形成欧姆接触，以降低器件的器件中的所述MOS沟道二极管的接触电阻。
具体的，在保证器件性能及所述第一导电类型掺杂层161与所述源极2形成欧姆接触的 情况下，所述第一导电类型掺杂层161的掺杂浓度可以根据实际情况进行设置，这里不再限制。
具体的，所述源极2的材质包括钛、氮化钛、银、金、铜、铝及钨中的一种，也可以是其他适合的导电材料。
具体的，所述漏极3的材质包括钛、氮化钛、银、金、铜、铝及钨中的一种，也可以是其他适合的导电材料。
具体的，由于所述上沟槽17的设置，缩小了器件中所述MOS沟道二极管的导电沟道长度，根据漏诱生势垒降低效应，随着导电沟道长度的减小，电子穿过所述体区进入所述势垒层16的势垒高度降低，继而使器件中所述MOS沟道二极管的开启电压降低，在器件在反向导通时，由于与所述源极沟槽结构14电连接的所述源极2接高压，导致所述体区15中所述MOS沟道二极管的导电沟道打开，使器件中的反向电流通过所述MOS沟道二极管中的导电沟道传输，使流过所述体区15的电流减小；同时由于所述体区15中流过电流的减小，使器件中的体二极管的开启被抑制，消除双极退化现象，提升器件反向导通能力的同时提升器件的可靠性。
具体的，由于所述MOS沟道二极管及所述电场屏蔽层18的设置，提升器件反向导通能力的同时使器件具有更大的击穿电压和更低的栅电荷特性，且不会降低器件的其他电学性能。
具体的，如图3所示，为几种不同沟道长度的图1结构中所述MOS沟道二极管的势垒高度变化曲线，其中，器件中所述衬底11的掺杂浓度为1.0×1019cm-3，厚度为2μm；所述漂移区121的掺杂浓度为8.0×1015cm-3，厚度为10μm；所述电流传输层122的掺杂浓度为6.0×1016cm-3，厚度为2μm；所述电场屏蔽层18的掺杂浓度为1.0×1019cm-3，厚度为0.4μm；所述栅介质层及所述第二介电层142的厚度为50nm；所述体区15的掺杂浓度为1.4×1017cm-3，厚度为0.7μm，宽度为0.8μm(这里的宽度是指所述栅极结构13侧壁到所述源极沟槽结构侧壁14之间的所述体区15的长度)；所述源区151及所述接触区152的掺杂浓度均为1.0×1019cm-3，厚度均为0.2μm，宽度均为0.3μm；所述第一导电类型掺杂区161的掺杂浓度为1.0×1019cm-3，厚度及宽度均为0.2μm，图中的LChd表示所述MOS沟道二极管的导电沟道长度，横轴Y为所述第一导电类型掺杂层161的上表面朝向所述外延层12延伸的距离，0μm处为所述第一导电类型掺杂层161上表面的位置，0.7μm处为所述体区15下表面的位置，从图3中可以看出，当所述MOS沟道二极管的导电沟道的长度从0.5μm降低到0.2μm，电子的势垒高度降低了1eV，意味着所述MOS沟道二极管的开启电压降低了1V，即随着所述MOS二极管的导电沟道长度的减小，电子的势垒高度逐渐降低，所述MOS沟道二极管的开 启电压也逐渐降低。
本实施例的功率MOSFET通过在相邻两个所述栅极结构13之间设置一所述源极沟槽结构14，且所述栅极结构13的侧壁与所述源极沟槽结构14的侧壁间隔预设距离，所述源极沟槽结构14包括所述源极沟槽141、所述第二介电层142及所述源导电层143，并于所述源极沟槽结构14的上方设置所述上沟槽17，所述上沟槽17的侧壁向所述栅极结构13延伸至距离所述源极沟槽结构14的侧壁预设距离处，且所述上沟槽17的底面显露出所述体区15，于所述上沟槽17的底部设置所述势垒层16，以形成由所述势垒层16、所述体区15、所述源极沟槽结构14及所述电流传输层122组成的所述MOS沟道二极管，通过加深所述上沟槽17的深度来减小所述MOS沟道二极管的导电沟道长度，由于漏势垒降低效应，导致电子穿过所述体区15进入所述势垒层16的势垒高度降低，继而降低所述MOS沟道二极管的开启电压。此外，由于所述源极沟槽结构14中的所述源导电层143与所述源极2电连接，在器件反向导通时，所述源导电层143接高压，导致所述源极沟槽结构14与所述体区15邻接处导电沟道开启，继而使器件通过所述MOS沟道二极管传输反向电流，同时使流过所述体区15中的电流减小，抑制所述体区15与所述电流传输层122构成的体二极管的开启，消除器件的双极退化。
实施例二
本实施例提供一种功率MOSFET的制备方法，如图4所示，为所述功率MOSFET的制备方法的工艺流程图，包括以下步骤：
S1：提供一半导体层，所述半导体层包括第一导电类型衬底及第一导电类型外延层，所述外延层包括依次层叠的第一导电类型漂移区及第一导电类型电流传输层；
S2：于所述电流传输层的上表层形成预设厚度的第二导电类型体区，于所述体区上表层形成多个交替设置的第一导电类型源区和第二导电类型接触区，且所述源区与所述接触区的侧壁相互邻接；
S3：于所述电流传输层中形成多个交替设置且间隔预设距离的栅极结构和源极沟槽结构，所述栅极结构贯穿所述源区及所述体区，所述源极沟槽结构贯穿所述体区及所述接触区；
S4：刻蚀所述源极沟槽结构以得到位于源极沟槽结构上方的上沟槽，所述上沟槽的侧壁沿朝向所述栅极结构的方向突出于所述源极沟槽结构的侧壁，所述上沟槽的底部显露出所述体区；
S5：于所述上沟槽的底部形成势垒层，所述势垒层覆盖所述上沟槽底部的所述体区的显露表面，所述势垒层与所述体区、所述源极沟槽结构及所述电流传输层组成MOS沟道二极 管；
S6：形成与所述势垒层、所述源区、所述接触区及所述源极沟槽结构电连接的源极，形成与与所述衬底电连接的漏极。
请参阅图5至图6，执行所述步骤S1及所述步骤S2：提供一半导体结构1，所述半导体结构1包括第一导电类型衬底11及第一导电类型外延层12，所述外延层12包括依次层叠的第一导电类型漂移区121及第一导电类型电流传输层122；于所述电流传输层122的上表层形成预设厚度的第二导电类型体区15，于所述体区15上表层形成多个交替设置的第一导电类型源区151和第二导电类型接触区152，且所述源区151与所述接触区152的侧壁相互邻接。
具体的，如图5所示，为所述半导体结构1剖面结构示意图，在保证器件性能的情况下，所述衬底11的厚度可以根据实际情况进行设置，这里不再限制；所述衬底11的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述衬底11的掺杂浓度为1.0×1019cm-3，厚度为2μm。
具体的，在保证器件性能的情况下，所述漂移区121的厚度可以根据实际情况进行设置，这里不再限制；所述漂移区121的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述漂移区121的掺杂浓度为8.0×1015cm-3，厚度为10μm。
具体的，在保证器件性能的情况下，所述电流传输层122的厚度可以根据实际情况进行设置，这里不再限制；所述电流传输层122的掺杂浓度可以根据实际情况进行设置，这里不再限制。本实施例中，所述电流传输层122的掺杂浓度为6.0×1016cm-3，厚度为2μm。
具体的，如图6所示，为形成所述体区15、所述源区151及所述接触区152后的剖面结构示意图，形成所述体区15的方法包括离子注入或者其他适合的方法。
具体的，形成所述源区151的方法包括离子注入或者其他适合的方法。
具体的，形成所述接触区152的方法包括离子注入或者其他适合的方法。
再请参阅图7至图10，执行所述步骤S3、所述步骤S4及所述步骤S5：于所述电流传输层中形成多个交替设置且间隔预设距离的栅极结构13和源极沟槽结构14，所述栅极结构13贯穿所述源区151及所述体区15，所述源极沟槽结构14贯穿所述体区15及所述接触区152；刻蚀所述源极沟槽结构14以得到位于源极沟槽结构14上方的上沟槽17，所述上沟槽17的侧壁沿朝向所述栅极结构13的方向突出于所述源极沟槽结构14的侧壁，所述上沟槽17的底部显露出所述体区15；于所述上沟槽17的底部形成势垒层16，所述势垒层16覆盖所述上沟槽17底部的所述体区15的显露表面，所述势垒层16与所述体区15、所述源极沟槽结构14 及所述电流传输层122组成MOS沟道二极管。
具体的，所述栅极结构13包括栅极沟槽131、第一介电层132及栅导电层133，所述第一介电层132位于所述栅极沟槽131的内壁及底面且包裹所述栅导电层133。
具体的，所述第一介电层132包括位于所述栅极沟槽131内壁及底面的栅介质层和覆盖所述栅介质层及所述栅导电层上表面的层间介质层。
具体的，所述源极沟槽结构14包括源极沟槽141、第二介电层142及源导电层143，所述第二介质层142位于所述源极沟槽141的内壁及底面并包裹所述源导电层143的侧壁及底面。
具体的，如图8所示，为形成所述栅极结构13后的剖面结构示意图，形成所述栅极结构13包括以下步骤：于所述外延层12的上表面形成一层图案化的光刻胶层，并基于图案化的所述光刻胶层形成所述栅极沟槽131；于所述栅极沟槽131的内壁及底面形成一层栅介质层，并形成填充所述栅极沟槽131的栅导电层133；于所述外延层12的上表面形成覆盖所述栅介质层及所述栅导电层133上表面的层间介质层，以得到所述栅极结构13。
具体的，所述源极沟槽141可以和所述栅极沟槽131同步形成，也可以在形成所述栅极结构13之后形成，或者在形成所述栅极结构13之前形成所述源极沟槽141，且当所述源极沟槽形成于所述栅极结构之前，需要形成所述源极沟槽141、所述第二介电层142及所述源导电层143之后再形成所述栅极沟槽131。本实施例中，为了减少工艺步骤，节省成本，刻蚀所述外延层12同步形成所述栅极沟槽131及所述源极沟槽141。
具体的，在保证器件性能的情况下，所述栅介质层与所述第二介电层142可以同步形成，也可以分步形成。本实施例中，为了减少工艺步骤，同步形成所述栅介质层与所述第二介电层142。
具体的，所述栅导电层133与所述源导电层143可以同步形成，也可以分步形成。本实施例中，所述栅导电层133与所述源导电层14同步形成，以减少工艺步骤，节省成本。
具体的，由于形成图案化的所述光刻胶层的方法为常用方法，这里不再赘述。
具体的，形成所述栅极沟槽131的方法包括干法刻蚀、湿法刻蚀或者其他适合的刻蚀方法。
具体的，形成所述栅介质层的方法包括化学气相沉积、物理气相沉积、热氧化法或者其他适合的方法；形成所述第二介电层142的方法包括化学气相沉积、物理气相沉积、热氧化法或者其他适合的方法。
具体的，形成所述栅导电层133的方法包括化学气相沉积、物理气相沉积或者其他适合 的方法；形成所述源导电层143的方法包括化学气相沉积、物理气相沉积或者其他适合的方法。
具体的，所述层间介质层还覆盖所述外延层(所述源区及所述接触区)的上表面。
具体的，形成所述层间介质层的方法包括化学气相沉积、物理气相沉积或者其他适合的方法。
具体的，形成所述源极沟槽141的方法包括干法刻蚀、湿法刻蚀或者其他适合的刻蚀方法。
具体的，如图7所示，为形成所述电场屏蔽层18后的剖面结构示意图，形成所述栅极沟槽13及所述源极沟槽14之后，形成所述第一介电层132及所述第二介电层142之前，还包括于所述栅极沟槽131及所述源极沟槽141的底面正下方的所述电流传输层122中形成第二导电类型电场屏蔽层18的步骤。
具体的，形成所述电场屏蔽层18的方法包括离子注入或者其他适合的方法。
具体的，形成所述上沟槽17的方法包括干法刻蚀、湿法刻蚀或者其他适合的方法。
具体的，如图9及图10所示，分别为形成所述势垒层16后的一种剖面结构示意图及形成所述势垒层16后的另一种剖面结构示意图，所述势垒层16包括第一导电类型掺杂层161及金属势垒接触层162。
具体的，所述势垒层16为所述第一导电类型掺杂层161时，形成所述势垒层16的方法包括离子注入、化学气相沉积、物理气相沉积或者其他适合的方法。本实施例中，为了简化工艺步骤，采用离子注入的方法于所述上沟槽17底部的所述体区15中形成所述势垒层16。
具体的，所述势垒层16为所述金属势垒接触层162时，形成所述势垒层16的方法包括溅射法、物理气相沉积、化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法、原子层沉积法或者其他适合的方法。
请参阅图1及图2，执行所述步骤S6：形成与所述势垒层16、所述源区151、所述接触区152及所述源极沟槽结构14电连接的源极2，形成与与所述衬底11电连接的漏极3。
具体的，形成所述源极2的方法包括溅射法、物理气相沉积、化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法、原子层沉积法或者其他适合的方法。
具体的，所述源极2填充所述上沟槽17，并直接或者通过导电材料与所述源导电层143电连接。
具体的，如图1及图2所示，分别为形成所述漏极3后的一种剖面结构示意图及形成所述漏极3后的另一种剖面结构示意图，形成所述漏极3的方法包括溅射法、物理气相沉积、 化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法、原子层沉积法或者其他适合的方法。
具体的，由于所述源极沟槽141、所述第二介电层142及所述源导电层143可以与述栅极沟槽131、所述栅介质层及所述栅导电层133同步形成，相对于形成双槽MOSFET的工艺仅增加形成所述上沟槽17及形成所述势垒层16的步骤，且形成所述上沟槽17及所述势垒层16的工艺简单。
具体的，由于所述上沟槽17、所述势垒层16及所述源极沟槽结构14的形成，使器件中形成一个由所述上沟槽17的深度来控制导电沟道长度的所述MOS沟道二极管，继而可以降低器件中所述势垒层16与所述体区15之间的势垒高度，降低所述MOS沟道二极管的开启电压，继而降低器件的导通损耗，同时，在器件反向导通时，所述源导电层143与所述源极2电连接，导致与所述源极沟槽结构14邻接的所述体区15中的导电沟道开启，利用导电沟道传输反向电流，抑制器件中体二极管的开启的同时，提升器件反向电流导通能力，且制备工艺简单。
本实施例的功率MOSFET的制备方法通过于所述源极沟槽结构14的上方形成一个预设深度的所述上沟槽17，并于所述上沟槽17中形成覆盖所述体区15的所述势垒层16，利用所述势垒层16、所述体区15、所述源极沟槽结构14及所述电流传输层122形成一个所述MOS沟道二极管，通过加大所述上沟槽17的深度，以减小所述MOS沟道二极管中的导电沟道长度，继而降低所述MOS沟道二极管的开启电压，降低器件的导通损耗，且无需增加复杂的工艺步骤，制备方法简单。
综上所述，本发明的功率MOSFET及其制备方法通过于相邻两个栅极结构之间设置与栅极结构间隔预设距离的源极沟槽结构，且源极沟槽结构的上方设置有上沟槽，上沟槽的侧壁朝向栅极结构突出且与源极沟槽结构的侧壁间隔预设距离，上沟槽的底面显露出体区，于上沟槽的底部形成势垒层，以得到由势垒层、体区、电流传输层及源极沟槽结构组成的MOS沟道二极管，利用上沟槽的深度控制MOS沟道二极管的导电沟道长度，通过减小MOS沟道二极管的导电沟道长度来降低电子穿过体区进入势垒层的势垒高度，降低MOS沟道二极管的开启电压，继而降低器件的导通损耗；在器件反向导通时，由于源极与源导电层电连接，导致靠近源极沟槽结构的体区中的导电沟道开启，器件中的反向电流从MOS沟道二极管的导电沟道传输，通过体区的反向电流减小，抑制了器件中体二极管的开启，消除了双极退化，提升了器件的反向电流传输能力，且形成源极沟槽、第二介电层及源导电层的工艺与形成栅极结构的工艺同步，形成上沟槽的及势垒层的工艺简单，无需复杂的工艺，工艺步骤简单。 所以，本发明有效克服了现有技术中的种种缺点而具有高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种功率MOSFET，其特征在于，包括：
    半导体结构，包括依次层叠的第一导电类型衬底及第一导电类型外延层，所述外延层包括依次层叠的第一导电类型漂移区及第一导电类型电流传输层；
    多个间隔设置的栅极结构，嵌于所述电流传输层中；
    源极沟槽结构，位于相邻两个所述栅极结构之间，所述源极沟槽结构的侧壁与所述栅极结构的侧壁间隔预设距离，所述源极沟槽结构的上方设有预设深度的上沟槽，所述上沟槽的侧壁沿朝向所述栅极结构的方向突出于所述源极沟槽结构的侧壁；
    第二导电类型体区，位于所述源极沟槽结构与所述栅极结构之间的所述电流传输层的上表层，所述上沟槽的底部显露出所述体区；
    多个第一导电类型源区及第二导电类型接触区，所述源区与所述接触区均位于所述体区的上表层，且位于所述栅极结构与所述上沟槽之间的所述源区与所述接触区邻接，所述源区远离所述接触区的侧壁与所述栅极结构的侧壁邻接；
    势垒层，位于所述上沟槽的底部，所述势垒层覆盖所述上沟槽底部的所述体区的显露表面，所述势垒层与所述体区、所述源极沟槽结构及所述电流传输层组成MOS沟道二极管；
    源极及漏极，所述源极与所述势垒层、所述源区、所述接触区及所述源极沟槽结构电连接，所述漏极与所述衬底电连接。
  2. 根据权利要求1所述的功率MOSFET，其特征在于：所述栅极结构包括栅极沟槽、第一介电层及栅导电层，所述第一介电层位于所述栅极沟槽的内壁及底面且包裹所述栅导电层；所述源极沟槽结构包括源极沟槽、第二介电层及源导电层，所述第二介电层位于所述源极沟槽的内壁及底面并包裹所述源导电层的侧壁及底面。
  3. 根据权利要求1所述的功率MOSFET，其特征在于：所述栅极结构及所述源极沟槽结构正下方的所述电流传输层中设有第二导电类型电场屏蔽层，所述电场屏蔽层的底面与所述电流传输层的底面间隔预设距离，所述电场屏蔽层的上表面与所述栅极结构及所述源极沟槽结构的底面接触，相邻两个所述电场屏蔽层间隔设置。
  4. 根据权利要求3所述的功率MOSFET，其特征在于：所述电场屏蔽层的掺杂浓度大于所述电流传输层的掺杂浓度。
  5. 根据权利要求1所述的功率MOSFET，其特征在于：通过调整所述上沟槽的底面的深度来调整所述MOS沟道二极管的导电沟道长度。
  6. 根据权利要求1所述的功率MOSFET，其特征在于：所述势垒层包括第一导电类型掺杂层及金属势垒接触层中的一种。
  7. 根据权利要求6所述的功率MOSFET，其特征在于：所述势垒层为所述金属势垒接触层，所述上沟槽的底面低于所述接触区的底面。
  8. 根据权利要求7所述的功率MOSFET，其特征在于：所述势垒层覆盖所述上沟槽底部的所述源极沟槽结构显露表面。
  9. 根据权利要求7所述的功率MOSFET，其特征在于：所述金属势垒接触层不与所述源极沟槽结构电连接。
  10. 根据权利要求6所述的功率MOSFET，其特征在于：所述势垒层为所述第一导电类型掺杂层，所述势垒层的下表面低于所述接触区的下表面且与所述体区的底面间隔预设距离，所述势垒层的侧壁与所述源极沟槽结构的侧壁邻接。
  11. 根据权利要求10所述的功率MOSFET，其特征在于：所述势垒层的掺杂浓度高于所述电流传输层的掺杂浓度。
  12. 一种功率MOSFET的制备方法，其特征在于，包括以下步骤：
    提供一半导体层，所述半导体层包括第一导电类型衬底及第一导电类型外延层，所述外延层包括依次层叠的第一导电类型漂移区及第一导电类型电流传输层；
    于所述电流传输层的上表层形成预设厚度的第二导电类型体区，于所述体区上表层形成多个交替设置的第一导电类型源区和第二导电类型接触区，且所述源区与所述接触区的侧壁相互邻接；
    于所述电流传输层中形成多个交替设置且间隔预设距离的栅极结构和源极沟槽结构，所述栅极结构贯穿所述源区及所述体区，所述源极沟槽结构贯穿所述体区及所述接触区；
    刻蚀所述源极沟槽结构以得到位于源极沟槽结构上方的上沟槽，所述上沟槽的侧壁沿朝向所述栅极结构的方向突出于所述源极沟槽结构的侧壁，所述上沟槽的底部显露出所述体区；
    于所述上沟槽的底部形成势垒层，所述势垒层覆盖所述上沟槽底部的所述体区的显露表面，所述势垒层与所述体区、所述源极沟槽结构及所述电流传输层组成MOS沟道二极管；
    形成与所述势垒层、所述源区、所述接触区及所述源极沟槽结构电连接的源极，形成与所述衬底电连接的漏极。
  13. 根据权利要求12所述的功率MOSFET的制备方法，其特征在于，所述栅极结构包括栅极沟槽、第一介电层及栅导电层，所述第一介电层位于所述栅极沟槽的内壁及底面且包裹所述栅导电层；所述源极沟槽结构包括源极沟槽、第二介电层及源导电层，所述第二介电层位于所述源极沟槽的内壁及底面并包裹所述源导电层的侧壁及底面。
  14. 根据权利要求13所述的功率MOSFET的制备方法，其特征在于，在形成所述栅极沟槽及所述源极沟槽之后，以及形成所述第一介电层及所述第二介电层之前，还包括于所述栅极沟槽及所述源极沟槽的底面正下方的所述电流传输层中形成第二导电类型电场屏蔽层的步骤。
  15. 根据权利要求12所述的功率MOSFET的制备方法，其特征在于，所述势垒层包括第一导电类型掺杂层及金属势垒接触层中的一种。
PCT/CN2023/107982 2022-09-20 2023-07-18 一种功率mosfet及其制备方法 WO2024060811A1 (zh)

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