WO2022247413A1 - Mosfet器件及制备方法 - Google Patents

Mosfet器件及制备方法 Download PDF

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WO2022247413A1
WO2022247413A1 PCT/CN2022/082194 CN2022082194W WO2022247413A1 WO 2022247413 A1 WO2022247413 A1 WO 2022247413A1 CN 2022082194 W CN2022082194 W CN 2022082194W WO 2022247413 A1 WO2022247413 A1 WO 2022247413A1
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gate
epitaxial
layer
trench
mosfet device
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PCT/CN2022/082194
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English (en)
French (fr)
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焦伟
刘华瑞
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华润微电子（重庆）有限公司
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Publication of WO2022247413A1 publication Critical patent/WO2022247413A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a MOSFET device and a preparation method.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • trench MOSFET devices In order to increase component density, existing MOSFET devices mostly adopt vertical structure design, such as trench MOSFET devices.
  • the structure of this trench MOSFET device is generally that the source is located on the surface, connected to the silicon body through a through hole, and the gate Formed in the trench and connected out through the gate polysilicon, the drain is located on the backside of the substrate.
  • this trench type MOSFET device In order to obtain MOSFET devices with higher withstand voltage, especially for MOSFET devices in the medium voltage segment, this trench type MOSFET device usually adopts thick epitaxy, which leads to high epitaxial resistance, high on-resistance, and long reverse recovery time. As a result, the rectification efficiency is low.
  • MOSFET devices that require secondary synchronous rectification have high withstand voltage and low on-resistance and Fast reverse recovery speed. Therefore, the existing MOSFET devices can no longer meet the demand.
  • the object of the present invention is to provide a MOSFET device and a manufacturing method for solving the problem that the MOSFET device in the prior art is difficult to meet high-efficiency rectification.
  • the present invention provides a MOSFET device, the MOSFET device comprising:
  • An epitaxial structure having a first conductivity type comprising a first epitaxial layer and a second epitaxial layer stacked, and the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer;
  • a trench gate structure the trench gate structure is disposed in the epitaxial structure, comprising a first trench gate structure and a second trench gate structure, wherein the first trench gate structure comprises A first gate dielectric layer and a first gate conductive layer, the second trench gate structure includes a second gate dielectric layer and a second gate conduction layer, and the second trench gate structure is located in the first trench gate structure on a gate dielectric layer and located on the periphery of part of the first gate conductive layer;
  • a source region having a first conductivity type is disposed on the body region.
  • the epitaxial structure is an epitaxial structure with defect centers, and the substance forming the defect centers includes one or a combination of lithium, iron and copper.
  • the thickness of the epitaxial structure ranges from 8 ⁇ m to 20 ⁇ m; the depth of the trench gate structure is 5 ⁇ m to 10 ⁇ m, and the trench gate structure penetrates the second epitaxial layer; the first The thickness of the gate dielectric layer is 500 ⁇ m ⁇ 1000 ⁇ m.
  • the surface of the second gate conductive layer is on the same plane as the surface of the first gate conductive layer.
  • the first gate dielectric layer and the second gate dielectric layer are both silicon oxide; the first gate conductive layer and the second gate conductive layer are both polysilicon.
  • the present invention also provides a kind of preparation method of MOSFET device, it is characterized in that, comprises the following steps:
  • the epitaxial structure includes a first epitaxial layer and a second epitaxial layer stacked, and the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer ;
  • a trench gate structure is formed in the epitaxial structure, the trench gate structure includes a first trench gate structure and a second trench gate structure, wherein the first trench gate structure includes a first trench gate structure A gate dielectric layer and a first gate conductive layer, the second trenched gate structure includes a second gate dielectric layer and a second gate conductive layer, and the second trenched gate structure is located on the first On the gate dielectric layer, and located on the periphery of part of the first gate conductive layer;
  • a source region with a first conductivity type is formed in the body region.
  • a step of forming defect centers in the epitaxial structure is also included, and the substance forming the defect centers includes one or a combination of lithium, iron and copper.
  • the formed epitaxial structure has a thickness ranging from 8 ⁇ m to 20 ⁇ m; the formed trench gate structure has a depth of 5 ⁇ m to 10 ⁇ m, and the trench gate structure penetrates through the second epitaxial layer; The thickness of the first gate dielectric layer is 500 ⁇ m ⁇ 1000 ⁇ m.
  • the step of forming the trench gate structure includes:
  • a second gate dielectric layer and a second gate conductive layer filling the groove are formed in the groove, and the surface of the second gate conductive layer is on the same plane as the surface of the first gate conductive layer.
  • the step of forming the trench gate structure includes:
  • a second gate conductive layer is formed to fill the groove, and the surface of the second gate conductive layer is on the same plane as the surface of the first gate dielectric layer.
  • the first gate dielectric layer not only serves as the gate dielectric layer of the first gate conductive layer, but also serves as the gate dielectric layer of the second gate conductive layer, thus, the first gate
  • the thickness of the first gate dielectric layer corresponding to the outer side of the conductive layer and the second gate conductive layer is different, and gate dielectric layers with different thicknesses are formed on the outer sides of the first gate conductive layer and the second gate conductive layer. electrical layer.
  • the MOSFET device of the present invention introduces a double-layer epitaxial structure with different doping concentrations and a deeper trench gate structure with different gate dielectric layer thicknesses, so that the MOSFET device can Achieve higher withstand voltage, significantly reduce on-resistance and reverse recovery time; in the trench gate structure, form a composite trench gate structure with gate dielectric layers of different thicknesses and gate conductive layers with the same plane
  • the preparation process is simple, easy to realize, and the manufacturing cost is low; the introduction of defect centers in the epitaxial structure can further reduce the reverse recovery time of MOSFET devices, thereby greatly improving the rectification efficiency of the power system;
  • the double-layer epitaxial structure Provides soft reverse recovery characteristics, significantly reduces system voltage and current spikes, and improves system reliability.
  • FIG. 1 is a schematic diagram of a process flow for preparing a MOSFET device in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of the patterned epitaxial structure after forming trenches in an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram after forming a first gate dielectric layer and a first gate conductive layer in a trench according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the structure after forming the second gate dielectric layer and the second gate conductive layer in the embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the structure after forming the body region and the source region in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the structure after defect centers are formed in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the structure after the metal conductive layer is formed in the embodiment of the present invention.
  • spatial relation terms such as “below”, “below”, “below”, “below”, “above”, “on” etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It should be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation (orientations other than those depicted in the figures).
  • a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more layers between the two layers may also be present. As used herein, "between” means that both endpoints are inclusive.
  • a description of a first feature being "on top of" a second feature may include embodiments where the first feature is in direct contact with the second feature, as well as additional features formed between the first feature and the second feature. Embodiments between the second feature such that the first feature and the second feature may not be in direct contact.
  • FIG. 7 shows a cross-sectional view of the MOSFET device of this embodiment.
  • the MOSFET device includes an epitaxial structure 200 having a first conductivity type, a trench gate structure 400 , a body region 500 having a second conductivity type, and a source region 600 having a first conductivity type.
  • the first conductivity type is N-type
  • the second conductivity type is opposite to the first conductivity type, so that the corresponding second conductivity type is P-type, but it is not limited thereto.
  • the first conductivity type may also be P-type
  • the corresponding second conductivity type may also be N-type.
  • the epitaxial structure 200 includes a first epitaxial layer 210 and a second epitaxial layer 220 stacked, and the doping concentration of the first epitaxial layer 210 is greater than that of the second epitaxial layer 220 .
  • the trench gate structure 400 is disposed in the epitaxial structure 200, including a first trench gate structure 410 and a second trench gate structure 420, and the first trench gate structure 410 comprises a first gate The dielectric layer 411 and the first gate conductive layer 412, the second trench gate structure 420 includes the second gate dielectric layer 421 and the second gate conductive layer 422, and the second trench gate structure 420 is located The first gate dielectric layer 411 is located on the periphery of part of the first gate conductive layer 412 .
  • the body region 500 is disposed in the second epitaxial layer 220 between the trench gate structures 400 , and the source region 600 is disposed on the body region 500 .
  • This embodiment introduces a double-layer epitaxial structure with different doping concentrations and a trench gate structure with different gate dielectric layer thicknesses, so that the MOSFET device can achieve a higher withstand voltage under a certain trench depth, which significantly reduces the On-resistance and reverse recovery time; in the trench gate structure, the preparation process of forming a composite trench gate structure with gate dielectric layers of different thicknesses and a gate conductive layer with the same plane is simple, easy to realize manufacturing, and The manufacturing cost is low; at the same time, the double-layer epitaxial structure provides soft reverse recovery characteristics, significantly reduces the voltage and current spikes of the system, and improves the reliability of the system.
  • the MOSFET device further includes a semiconductor substrate 100 , a dielectric layer 800 and a metal conductive layer 900 .
  • the epitaxial structure 200 further includes a defect center 700, so as to reduce the reverse recovery time of the MOSFET device through the defect center 700, thereby greatly improving the rectification efficiency of the power system.
  • the present embodiment provides a kind of preparation method of MOSFET device, specifically can comprise:
  • the epitaxial structure 200 having the first conductivity type is formed, the epitaxial structure 200 includes a stacked first epitaxial layer 210 and a second epitaxial layer 220 , and the first epitaxial layer 210 The doping concentration is greater than that of the second epitaxial layer 220 .
  • a semiconductor substrate 100 can be provided first, and the semiconductor substrate 100 can be a silicon substrate, and is of the first conductivity type.
  • the material of the semiconductor substrate 100 can also be silicon germanium (SiGe) , gallium nitride (GaN) or silicon carbide (SiC) and other doped semiconductor materials.
  • the semiconductor substrate 100 can be used as the drain region of the MOSFET device due to the doping of the first conductivity type.
  • the epitaxial structure 200 with different doping concentrations can be formed on the semiconductor substrate 100 by ion implantation, the concentration of carriers of the first conductivity type in the epitaxial structure 200 is lower than that of the semiconductor substrate 100 , can be used as the drift region of the MOSFET device.
  • the doping concentration of the first epitaxial layer 210 adjacent to the semiconductor substrate 100 in the epitaxial structure 200 is greater than the doping concentration of the second epitaxial layer 220, so as to ensure that under a certain trench depth, the MOSFET devices can achieve higher withstand voltage, and the double-layer epitaxial structure can provide soft reverse recovery characteristics, which can significantly reduce system voltage and current spikes and improve system reliability.
  • the trench gate structure 400 is formed in the epitaxial structure 200, and the trench gate structure 400 includes a first trench gate structure 410 and a second trench gate structure.
  • pole structure 420 wherein the first trench gate structure 410 comprises a first gate dielectric layer 411 and a first gate conductive layer 412, and the second trench gate structure 420 comprises a second gate dielectric layer 421 and the second gate conductive layer 422 , and the second trench gate structure 420 is located on the first gate dielectric layer 411 and is located on a part of the periphery of the first gate conductive layer 412 .
  • the thickness of the first gate dielectric layer 411 located at the lower part is greater than the thickness of the second gate dielectric layer 421 located at the upper part, and the second gate conductive layer
  • the surface of 422 is on the same plane as the surface of the first gate conductive layer 412 to form a compound trench gate structure.
  • the formed epitaxial structure 200 may have a thickness ranging from 8 ⁇ m to 20 ⁇ m, such as 8 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m and so on.
  • the trench gate structure 400 formed has a depth of 5 ⁇ m to 10 ⁇ m, such as 5 ⁇ m, 8 ⁇ m, 10 ⁇ m, etc., and the trench gate structure 400 penetrates the second epitaxial layer 220; the first gate dielectric
  • the thickness of the layer 411 is 500 ⁇ m ⁇ 1000 ⁇ m, such as 500 ⁇ m, 800 ⁇ m, 1000 ⁇ m and so on.
  • the formed first gate dielectric layer 411 and the second gate dielectric layer 421 may be made of silicon oxide, such as silicon oxide formed by a thermal oxidation process.
  • the material composition of silicon such as oxides, nitrides, and oxynitrides with large dielectric constants.
  • the formed first gate conductive layer 412 and the second gate conductive layer 422 may be made of polysilicon, of course, a metal layer, or a stacked layer comprising a metal layer and a polysilicon layer may also be used.
  • the step of forming the trench gate structure 400 may include:
  • first gate dielectric layer 411 and a first gate conductive layer 412 filling the trench 300 in the trench 300, as shown in FIG. 3;
  • a second gate dielectric layer 421 and a second gate conductive layer 422 filling the groove are formed in the groove, and the surface 422 of the second gate conductive layer and the surface of the first gate conductive layer 412 are located same plane, as shown in Figure 4.
  • the step of forming the trench gate structure 400 may further include:
  • first gate dielectric layer 411 and a first gate conductive layer 412 filling the trench 300 in the trench 300, as shown in FIG. 3;
  • a second gate conductive layer 422 is formed to fill the groove, and the surface of the second gate conductive layer 422 is on the same plane as the surface of the first gate dielectric layer 411 .
  • the part of the first gate dielectric layer 411 corresponding to the periphery of the second gate conductive layer 422 serves as the second gate dielectric layer 421, that is, the formed first gate dielectric layer 411 can be It is directly used as the gate dielectric layer of the second trench gate structure 420 to reduce process complexity.
  • a body region 500 with the second conductivity type is formed in the second epitaxial layer 220 between the trench gate structures 400 , and a body region 500 with the first conductivity type is formed in the body region 500 .
  • source region 600 of conductivity type is formed in the body region 500 .
  • the body region 500 and the source region 600 surrounding the trench gate structure 400 can be formed using a conventional body implantation technique. If the first ion implantation can be performed, the body region 500 of the second conductivity type is formed in the upper region of the second epitaxial layer 220 adjacent to the trench gate structure 400 . Next, a second ion implantation is performed to form the source region 600 with the first conductivity type in the body region 500 .
  • the step of forming a defect center 700 in the epitaxial structure 200 may also be included, so that when the reverse freewheeling diode is turned off, the minority carrier holes can recombine with the defect center on the spot, so that Reduce compounding time.
  • the reverse recovery time of the MOSFET device is reduced by the defect center 700, thereby greatly improving the rectification efficiency of the power system.
  • the substance forming the defect center 700 may include one or a combination of lithium, iron and copper.
  • the defect centers 700 are preferably evenly distributed in the first epitaxial layer 210 and the second epitaxial layer 220.
  • a dielectric layer 800 and a metal conductive layer 900 are formed above the source region 600 .
  • the dielectric layer 800 covering the source region 600 and the top surface of the trench gate structure 400 is formed first, and then a known etching process can be used to form the dielectric layer 800 and the The conductive channel of the source region 600 is formed, and then the metal conductive layer 900 is formed on the dielectric layer 800, so that the metal conductive layer 900 is connected to the body region 500 through the conductive channel.
  • the metal conductive layer 900 may include metal materials such as aluminum or copper.
  • the MOSFET device of the present invention introduces a double-layer epitaxial structure with different doping concentrations and a deep trench gate structure with different gate dielectric layer thicknesses, so that the MOSFET device can High withstand voltage can be achieved, and the on-resistance and reverse recovery time are significantly reduced; in the trench gate structure, a composite trench gate with gate dielectric layers of different thicknesses and a gate conductive layer with the same plane is formed
  • the preparation process of the structure is simple, easy to realize, and the manufacturing cost is low; the defect center is introduced in the epitaxial structure, which can further reduce the reverse recovery time of the MOSFET device, thereby greatly improving the rectification efficiency of the power system; in addition, the double-layer epitaxy
  • the structure provides soft reverse recovery characteristics, which significantly reduces the voltage and current spikes of the system and improves system reliability.

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Abstract

本发明提供一种MOSFET器件及制备方法，该MOSFET器件引入了具有不同掺杂浓度的双层外延结构以及较深的具有不同栅介电层厚度的沟槽栅极结构，使得MOSFET器件在一定沟槽深度情况下可以取得较高的耐压，显著降低了导通电阻和反向恢复时间；在沟槽栅极结构中，形成具有不同厚度的栅介电层以及具有同一平面的栅导电层的复合沟槽栅结构的制备工艺简单，便于实现制造，且制造成本较低；在外延结构中引入缺陷中心，可进一步降低MOSFET器件的反向恢复时间，从而大幅提升电源系统的整流效率；此外，双层外延结构提供了软的反向恢复特性，显著降低了系统的电压和电流尖峰，提高了系统可靠性。

Description

MOSFET器件及制备方法
相关申请的交叉引用
本申请要求于2021年5月24日提交中国专利局、申请号为202110566514.3、发明名称为“MOSFET器件及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，特别是涉及一种MOSFET器件及制备方法。
背景技术
金属-氧化物-半导体-场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)是一种可以广泛使用在模拟电路与数字电路的场效晶体管，由于驱动电路简单，驱动功率小，开关速度快，工作频率高等优点，是中低压同步整流电源的重要元器件。
现有的MOSFET器件为提升组件密度，多采用垂直结构的设计，例如沟槽型MOSFET器件，这种沟槽型MOSFET器件的结构一般为源极位于表面，通过通孔接到硅体内，栅极形成于沟槽中，通过栅多晶硅连接出来，漏极则位于衬底背面。为了获得较高耐压的MOSFET器件，特别是适用于中压段的MOSFET器件，这种沟槽型MOSFET器件通常采用厚外延，这导致外延电阻高，导通电阻高，反向恢复时间长，从而使得整流效率低。
然而现代的大功率电源系统，开关频率越来越高，输出电压越来越高，电流也越来越大，需要次级同步整流的MOSFET器件的耐压高，同时具有低的导通电阻和快的反向恢复速度。因此，现有的MOSFET器件已不能满足需求。
因此，提供一种MOSFET器件及制备方法，实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种MOSFET器件及制备方法，用于解决现有技术中MOSFET器件难以满足高效整流的问题。
为实现上述目的及其他相关目的，本发明提供一种MOSFET器件，所述MOSFET器件包括：
具有第一导电类型的外延结构，所述外延结构包括堆叠设置的第一外延层及第二外延 层，且所述第一外延层的掺杂浓度大于所述第二外延层的掺杂浓度；
沟槽栅极结构，所述沟槽栅极结构设置于所述外延结构中，包括第一沟槽栅极结构及第二沟槽栅极结构，其中，所述第一沟槽栅极结构包括第一栅介电层及第一栅导电层，所述第二沟槽栅极结构包括第二栅介电层及第二栅导电层，且所述第二沟槽栅极结构位于所述第一栅介电层上，并位于部分所述第一栅导电层的外围；
具有第二导电类型的体区，所述体区设置于所述沟槽栅极结构之间的所述第二外延层中，所述第二导电类型与所述第一导电类型相反；
具有第一导电类型的源区，所述源区设置于所述体区上。
可选地，所述外延结构为具有缺陷中心的外延结构，形成所述缺陷中心的物质包括锂、铁及铜中的一种或其组合。
可选地，所述外延结构的厚度范围为8μm～20μm；所述沟槽栅极结构的深度为5μm～10μm，且所述沟槽栅极结构贯穿所述第二外延层；所述第一栅介电层的厚度为500μm～1000μm。
可选地，所述第二栅导电层的表面与所述第一栅导电层的表面位于同一平面。
可选地，所述第一栅介电层及所述第二栅介电层均为氧化硅；所述第一栅导电层及第二栅导电层均为多晶硅。
本发明还提供一种MOSFET器件的制备方法，其特征在于，包括以下步骤：
形成具有第一导电类型的外延结构，所述外延结构包括堆叠设置的第一外延层及第二外延层，且所述第一外延层的掺杂浓度大于所述第二外延层的掺杂浓度；
于所述外延结构中形成沟槽栅极结构，所述沟槽栅极结构包括第一沟槽栅极结构及第二沟槽栅极结构，其中，所述第一沟槽栅极结构包括第一栅介电层及第一栅导电层，所述第二沟槽栅极结构包括第二栅介电层及第二栅导电层，且所述第二沟槽栅极结构位于所述第一栅介电层上，并位于部分所述第一栅导电层的外围；
于所述沟槽栅极结构之间的所述第二外延层中形成第二导电类型的体区，所述第二导电类型与所述第一导电类型相反；
于所述体区中形成具有第一导电类型的源区。
可选地，还包括在所述外延结构中形成缺陷中心的步骤，形成所述缺陷中心的物质包括锂、铁及铜中的一种或组合。
可选地，形成的所述外延结构的厚度范围为8μm～20μm；形成的所述沟槽栅极结构的深度为5μm～10μm，且所述沟槽栅极结构贯穿所述第二外延层；所述第一栅介电层的厚度为500μm～1000μm。
可选地，形成所述沟槽栅极结构的步骤包括：
图形化所述外延结构形成沟槽，所述沟槽显露出所述第一外延层；
于所述沟槽中形成填充所述沟槽的第一栅介电层及第一栅导电层；
去除部分所述第一栅介电层，形成凹槽；
于所述凹槽中形成填充所述凹槽的第二栅介电层及第二栅导电层，且所述第二栅导电层的表面与所述第一栅导电层的表面位于同一平面。
可选地，形成所述沟槽栅极结构的步骤包括：
图形化所述外延结构形成沟槽，所述沟槽显露出所述第一外延层；
于所述沟槽中形成填充所述沟槽的第一栅介电层及第一栅导电层；
图形化所述第一栅介电层，形成凹槽；
形成填充所述凹槽的第二栅导电层，且所述第二栅导电层的表面与所述第一栅介电层的表面位于同一平面。此时，所述第一栅介电层除作为所述第一栅导电层的栅介电层外，还作为所述第二栅导电层的栅介电层，由此，所述第一栅导电层和所述第二栅导电层外侧对应的所述第一栅介电层的厚度不同，在所述第一栅导电层和所述第二栅导电层的外侧形成了不同厚度的栅介电层。
如上所述，本发明的MOSFET器件引入了具有不同掺杂浓度的双层外延结构以及较深的具有不同栅介电层厚度的沟槽栅极结构，使得MOSFET器件在一定沟槽深度情况下可以取得较高的耐压，显著降低了导通电阻和反向恢复时间；在沟槽栅极结构中，形成具有不同厚度的栅介电层以及具有同一平面的栅导电层的复合沟槽栅结构的制备工艺简单，便于实现制造，且制造成本较低；在外延结构中引入了缺陷中心，可进一步降低MOSFET器件的反向恢复时间，从而大幅提升电源系统的整流效率；此外，双层外延结构提供了软的反向恢复特性，显著降低了系统的电压和电流尖峰，提高了系统可靠性。
附图说明
图1显示为本发明实施例中制备MOSFET器件的工艺流程示意图。
图2显示为本发明实施例中图形化外延结构形成沟槽后的结构示意图。
图3显示为本发明实施例中于沟槽中形成第一栅介电层及第一栅导电层后的结构示意图。
图4显示为本发明实施例中形成第二栅介电层及第二栅导电层后的结构示意图。
图5显示为本发明实施例中形成体区及源区后的结构示意图。
图6显示为本发明实施例中形成缺陷中心后的结构示意图。
图7显示为本发明实施例中形成金属导电层后的结构示意图。
元件标号说明
100                    半导体衬底
200                    外延结构
210                    第一外延层
220                    第二外延层
300                    沟槽
400                    沟槽栅极结构
410                    第一沟槽栅极结构
411                    第一栅介电层
412                    第一栅导电层
420                    第二沟槽栅极结构
421                    第二栅介电层
422                    第二栅导电层
500                    体区
600                    源区
700                    缺陷中心
800                    介质层
900                    金属导电层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用。本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，所述示意图只是示例性的，其在此不应被用于限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。应当理 解的是，这些空间关系词语意图包含使用中或操作中的器件的其他方向(除了附图中描绘的方向之外的方向)。此外，当一层被称为在两层“之间”时，它可以是上述两层之间仅有的层，或者也可以存在一个或多个介于上述两层之间的层。本文使用的“介于……之间”表示包括两端点值。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一特征和第二特征直接接触的实施例，也可以包括另外的特征形成在第一特征和第二特征之间的实施例，这样第一特征和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意的方式说明本发明的基本构想，遂图示中仅显示了与本发明中有关的组件，而非按照实际实施时的组件数目、形状及尺寸绘制。实际实施时，各组件的型态、数量及比例可为一种随意的改变，组件布局型态也可能更为复杂。
图7显示为本实施例的MOSFET器件的截面图。所述MOSFET器件包括具有第一导电类型的外延结构200、沟槽栅极结构400、具有第二导电类型的体区500、具有第一导电类型的源区600。
本实施例中，所述第一导电类型为N型，所述第二导电类型与所述第一导电类型相反，从而相应的所述第二导电类型为P型，但并非局限于此，在另一实施例中，所述第一导电类型也可为P型，相应的所述第二导电类型也可为N型。
具体地，所述外延结构200包括堆叠设置的第一外延层210及第二外延层220，且所述第一外延层210的掺杂浓度大于所述第二外延层220的掺杂浓度。所述沟槽栅极结构400设置于所述外延结构200中，包括第一沟槽栅极结构410及第二沟槽栅极结构420，所述第一沟槽栅极结构410包括第一栅介电层411及第一栅导电层412，所述第二沟槽栅极结构420包括第二栅介电层421及第二栅导电层422，且所述第二沟槽栅极结构420位于所述第一栅介电层411上，并位于部分所述第一栅导电层412的外围。所述体区500设置于所述沟槽栅极结构400之间的所述第二外延层220中，所述源区600设置于所述体区500上。
本实施例引入具有不同掺杂浓度的双层外延结构以及具有不同栅介电层厚度的沟槽栅极结构，使得MOSFET器件在一定沟槽深度情况下可以取得较高的耐压，显著降低了导通电阻和反向恢复时间；在沟槽栅极结构中，形成具有不同厚度的栅介电层以及具有同一平面的栅导电层的复合沟槽栅结构的制备工艺简单，便于实现制造，且制造成本较低；同时双层外延结构提供了软的反向恢复特性，显著降低了系统的电压和电流尖峰，提高了系统可靠性。
如图7，所述MOSFET器件还包括半导体衬底100、介质层800及金属导电层900。进一步地，本实施例中，在所述外延结构200中还包括缺陷中心700，以通过所述缺陷中心700降低所述MOSFET器件的反向恢复时间，从而大幅提升电源系统的整流效率。
以下结合附图，对所述MOSFET器件的制备工艺进行介绍。
参阅图1，本实施例提供了一种MOSFET器件的制备方法，具体可包括：
(1)参阅图2，形成具有第一导电类型的所述外延结构200，所述外延结构200包括堆叠设置的第一外延层210及第二外延层220，且所述第一外延层210的掺杂浓度大于所述第二外延层220的掺杂浓度。
具体地，首先，可先提供半导体衬底100，所述半导体衬底100可为硅衬底，并且为第一导电类型，当然，所述半导体衬底100的材质还可为锗硅(SiGe)、氮化镓(GaN)或碳化硅(SiC)等掺杂半导体材料。所述半导体衬底100由于具有第一导电类型掺杂，可作为所述MOSFET器件的漏区。
接着，可通过离子注入在所述半导体衬底100上形成具有不同掺杂浓度的所述外延结构200，所述外延结构200中第一导电类型载流子的浓度低于所述半导体衬底100，可作为所述MOSFET器件的漂移区。所述外延结构200中临近所述半导体衬底100的所述第一外延层210的掺杂浓度大于所述第二外延层220的掺杂浓度，以确保在一定沟槽深度情况下，所述MOSFET器件可取得较高的耐压，且双层外延结构可提供软的反向恢复特性，显著降低系统的电压和电流尖峰，提高系统可靠性。
(2)如图2～图4，于所述外延结构200中形成所述沟槽栅极结构400，所述沟槽栅极结构400包括第一沟槽栅极结构410及第二沟槽栅极结构420，其中，所述第一沟槽栅极结构410包括第一栅介电层411及第一栅导电层412，所述第二沟槽栅极结构420包括第二栅介电层421及第二栅导电层422，且所述第二沟槽栅极结构420位于所述第一栅介电层411上，并位于部分所述第一栅导电层412的外围。在所述沟槽栅极结构400中，使得位于下部的所述第一栅介电层411的厚度大于位于上部的所述第二栅介电层421的厚度，且所述第二栅导电层422的表面与所述第一栅导电层412的表面位于同一平面，以形成复合沟槽栅结构。上述结构的制备工艺简单，便于实现制造，且制造成本较低。
作为示例，形成的所述外延结构200的厚度范围可为8μm～20μm，如8μm、10μm、15μm、20μm等。形成的所述沟槽栅极结构400的深度为5μm～10μm，如5μm、8μm、10μm等，且所述沟槽栅极结构400贯穿所述第二外延层220；所述第一栅介电层411的厚度为500μm～1000μm，如500μm、800μm、1000μm等。
作为示例，形成的所述第一栅介电层411及所述第二栅介电层421可均为氧化硅材质， 如采用热氧化工艺形成的氧化硅，当然也可采用介电常数大于氧化硅的材料构成，如介电常数较大的氧化物、氮化物、氮氧化物等。形成的所述第一栅导电层412及第二栅导电层422可均为多晶硅材质，当然也可采用如金属层，或包括金属层和多晶硅层的叠层。
具体地，作为示例，形成所述沟槽栅极结构400的步骤可包括：
图形化所述外延结构200形成沟槽300，所述沟槽300显露出所述第一外延层210，如图2所示；
于所述沟槽300中形成填充所述沟槽300的第一栅介电层411及第一栅导电层412，如图3所示；
去除部分所述第一栅介电层411，形成凹槽(在图中未示出)；
于所述凹槽中形成填充该凹槽的第二栅介电层421及第二栅导电层422，且所述第二栅导电层的表面422与所述第一栅导电层412的表面位于同一平面，如图4所示。
在另一实施例中，形成所述沟槽栅极结构400的步骤还可包括：
图形化所述外延结构200形成沟槽300，所述沟槽300显露出所述第一外延层210，如图2所示；
于所述沟槽300中形成填充所述沟槽300的第一栅介电层411及第一栅导电层412，如图3所示；
图形化所述第一栅介电层，形成凹槽(在图中未示出)；
形成填充所述凹槽的第二栅导电层422，且所述第二栅导电层422的表面与所述第一栅介电层411的表面位于同一平面。如图4所示，所述第二栅导电层422外围对应的所述第一栅介电层411的部分充当第二栅介电层421，即形成的所述第一栅介电层411可直接作为所述第二沟槽栅极结构420的栅介电层应用，以降低工艺复杂度。
(3)如图5，于所述沟槽栅极结构400之间的所述第二外延层220中形成具有第二导电类型的体区500，以及于所述体区500中形成具有第一导电类型的源区600。
具体地，可采用常规的体注入技术，形成围绕所述沟槽栅极结构400的所述体区500及所述源区600。如可进行第一次离子注入，在所述第二外延层220中邻近所述沟槽栅极结构400的上部区域中形成具有第二导电类型的所述体区500。接着，进行第二次离子注入，在所述体区500中形成具有第一导电类型的所述源区600。
(6)如图6，还可包括在所述外延结构200中形成缺陷中心700的步骤，使得反向续流二极管关断时，少数载流子空穴能够就地与缺陷中心进行复合，以缩短复合时间。通过所述缺陷中心700降低了所述MOSFET器件的反向恢复时间，从而大幅提升了电源系统的整流效率。其中，形成所述缺陷中心700的物质可包括锂、铁及铜中的一种或其组合。所 述缺陷中心700优选均匀分布于所述第一外延层210及第二外延层220中。
(7)如图7，在所述源区600上方形成介质层800以及金属导电层900。
具体地，先形成覆盖所述源区600和所述沟槽栅极结构400的顶部表面的所述介质层800，然后可通过已知的刻蚀工艺，形成穿透所述介质层800以及所述源区600的导电通道，接着在所述介质层800上方形成所述金属导电层900，使得所述金属导电层900经导电通道连接至所述体区500。所述金属导电层900可包括如铝或铜之类的金属材料。
综上所述，本发明的MOSFET器件引入了具有不同掺杂浓度的双层外延结构以及较深的具有不同栅介电层厚度的沟槽栅极结构，使得MOSFET器件在一定沟槽深度情况下可以取得较高的耐压，显著降低了导通电阻和反向恢复时间；在沟槽栅极结构中，形成具有不同厚度的栅介电层以及具有同一平面的栅导电层的复合沟槽栅结构的制备工艺简单，便于实现制造，且制造成本较低；在外延结构中引入了缺陷中心，可进一步降低MOSFET器件的反向恢复时间，从而大幅提升电源系统的整流效率；此外，双层外延结构提供了软的反向恢复特性，显著降低了系统的电压和电流尖峰，提高了系统可靠性。
上述实施例仅示例性地说明本发明的原理及其功效，而非用于限制本发明。任何熟悉本领域的技术人员皆可在不违背本发明的精神及范畴的情况下，对上述实施例进行修饰或改变。因此，凡本技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍属于本发明的权利要求所保护的范围。

Claims (15)

  1. 一种MOSFET器件，其特征在于，所述MOSFET器件包括：
    具有第一导电类型的外延结构，所述外延结构包括堆叠设置的第一外延层及第二外延层，且所述第一外延层的掺杂浓度大于所述第二外延层的掺杂浓度；
    沟槽栅极结构，所述沟槽栅极结构设置于所述外延结构中，包括第一沟槽栅极结构及第二沟槽栅极结构，其中，所述第一沟槽栅极结构包括第一栅介电层及第一栅导电层，所述第二沟槽栅极结构包括第二栅介电层及第二栅导电层，且所述第二沟槽栅极结构位于所述第一栅介电层上，并位于部分所述第一栅导电层的外围；
    具有第二导电类型的体区，所述体区设置于所述沟槽栅极结构之间的所述第二外延层中，所述第二导电类型与所述第一导电类型相反；
    具有第一导电类型的源区，所述源区设置于所述体区上。
  2. 根据权利要求1所述的MOSFET器件，其特征在于：所述外延结构为具有缺陷中心的外延结构，形成所述缺陷中心的物质包括锂、铁及铜中的一种或其组合。
  3. 根据权利要求2所述的MOSFET器件，其特征在于：所述缺陷中心均匀分布于所述第一外延层及第二外延层中。
  4. 根据权利要求1所述的MOSFET器件，其特征在于：所述外延结构的厚度范围为8μm～20μm；所述沟槽栅极结构的深度为5μm～10μm，且所述沟槽栅极结构贯穿所述第二外延层；所述第一栅介电层的厚度为500μm～1000μm。
  5. 根据权利要求1所述的MOSFET器件，其特征在于：所述第二栅导电层的表面与所述第一栅导电层的表面位于同一平面。
  6. 根据权利要求1所述的MOSFET器件，其特征在于：所述第一栅介电层及所述第二栅介电层均为氧化硅；所述第一栅导电层及第二栅导电层均为多晶硅。
  7. 根据权利要求1所述的MOSFET器件，其特征在于：所述MOSFET器件还包括具有第一导电类型的半导体衬底，所述外延结构位于所述半导体衬底上，且所述外延结构中第一导电类型载流子的浓度低于所述半导体衬底。
  8. 根据权利要求1所述的MOSFET器件，其特征在于：所述MOSFET器件还包括在所述源区上方的介质层以及金属导电层。
  9. 一种MOSFET器件的制备方法，其特征在于，包括以下步骤：
    形成具有第一导电类型的外延结构，所述外延结构包括堆叠设置的第一外延层及第二外延层，且所述第一外延层的掺杂浓度大于所述第二外延层的掺杂浓度；
    于所述外延结构中形成沟槽栅极结构，所述沟槽栅极结构包括第一沟槽栅极结构及第二沟槽栅极结构，其中，所述第一沟槽栅极结构包括第一栅介电层及第一栅导电层，所述第二沟槽栅极结构包括第二栅介电层及第二栅导电层，且所述第二沟槽栅极结构位于所述第一栅介电层上，并位于部分所述第一栅导电层的外围；
    于所述沟槽栅极结构之间的所述第二外延层中形成具有第二导电类型的体区，所述第二导电类型与所述第一导电类型相反；
    于所述体区中形成具有第一导电类型的源区。
  10. 根据权利要求9所述的MOSFET器件的制备方法，其特征在于：还包括在所述外延结构中形成缺陷中心的步骤，形成所述缺陷中心的物质包括锂、铁及铜中的一种或其组合。
  11. 根据权利要求9所述的MOSFET器件的制备方法，其特征在于：形成的所述外延结构的厚度范围为8μm～20μm；形成的所述沟槽栅极结构的深度为5μm～10μm，且所述沟槽栅极结构贯穿所述第二外延层；所述第一栅介电层的厚度为500μm～1000μm。
  12. 根据权利要求9所述的MOSFET器件的制备方法，其特征在于，形成所述沟槽栅极结构的步骤包括：
    图形化所述外延结构形成沟槽，所述沟槽显露出所述第一外延层；
    于所述沟槽中形成填充所述沟槽的第一栅介电层及第一栅导电层；
    去除部分所述第一栅介电层，形成凹槽；
    于所述凹槽中形成填充所述凹槽的第二栅介电层及第二栅导电层，且所述第二栅导电层的表面与所述第一栅导电层的表面位于同一平面。
  13. 根据权利要求9所述的MOSFET器件的制备方法，其特征在于，形成所述沟槽栅极结构的步骤包括：
    图形化所述外延结构形成沟槽，所述沟槽显露出所述第一外延层；
    于所述沟槽中形成填充所述沟槽的第一栅介电层及第一栅导电层；
    图形化所述第一栅介电层，形成凹槽；
    形成填充所述凹槽的第二栅导电层，且所述第二栅导电层的表面与所述第一栅介电层的表面位于同一平面。
  14. 根据权利要求9所述的MOSFET器件的制备方法，其特征在于，先提供具有第一导电类型的半导体衬底，在所述半导体衬底上形成具有不同掺杂浓度的所述外延结构，所述外延结构中第一导电类型载流子的浓度低于所述半导体衬底。
  15. 根据权利要求9所述的MOSFET器件的制备方法，其特征在于，在所述源区上方形成介质层以及金属导电层。
PCT/CN2022/082194 2021-05-24 2022-03-22 Mosfet器件及制备方法 WO2022247413A1 (zh)

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CN112713184A (zh) * 2019-10-24 2021-04-27 南通尚阳通集成电路有限公司 具有屏蔽栅的沟槽栅mosfet及其制造方法

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US20190198633A1 (en) * 2017-12-22 2019-06-27 Vanguard International Semiconductor Corporation Semiconductor structure and method for forming the same
CN111223930A (zh) * 2018-11-26 2020-06-02 深圳尚阳通科技有限公司 屏蔽栅沟槽mosfet
CN112713184A (zh) * 2019-10-24 2021-04-27 南通尚阳通集成电路有限公司 具有屏蔽栅的沟槽栅mosfet及其制造方法
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