WO2021088231A1 - 碳化硅mosfet器件的元胞结构及碳化硅mosfet器件 - Google Patents

碳化硅mosfet器件的元胞结构及碳化硅mosfet器件 Download PDF

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WO2021088231A1
WO2021088231A1 PCT/CN2019/128387 CN2019128387W WO2021088231A1 WO 2021088231 A1 WO2021088231 A1 WO 2021088231A1 CN 2019128387 W CN2019128387 W CN 2019128387W WO 2021088231 A1 WO2021088231 A1 WO 2021088231A1
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region
gate
silicon carbide
source
well region
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PCT/CN2019/128387
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English (en)
French (fr)
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戴小平
王亚飞
陈喜明
李诚瞻
罗海辉
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株洲中车时代半导体有限公司
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Priority to US17/774,849 priority Critical patent/US20220406896A1/en
Publication of WO2021088231A1 publication Critical patent/WO2021088231A1/zh

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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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Definitions

  • the present disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a silicon carbide MOSFET device and a silicon carbide MOSFET device.
  • Silicon carbide is a new wide-bandgap semiconductor material with excellent physical, chemical and electrical properties.
  • the breakdown electric field strength of silicon carbide is 10 times that of traditional silicon, and the thermal conductivity is 3 times that of silicon. Silicon carbide is very attractive and promising in power semiconductor devices, especially in high-power and high-temperature application environments.
  • Silicon carbide unipolar devices metal-oxide semiconductor field effect crystal MOSFET, Schottky barrier diode SBD
  • Bipolar devices PiN diode, insulated gate bipolar transistor IGBT, thyristor, etc.
  • SiN diode insulated gate bipolar transistor IGBT, thyristor, etc.
  • SiN diode insulated gate bipolar transistor IGBT, thyristor, etc.
  • SiN diode insulated gate bipolar transistor IGBT, thyristor, etc.
  • bipolar degradation in silicon carbide bipolar devices, that is, recombination after carrier injection (or excitation), and a single Shockley stacking layer
  • the nucleation and expansion of the Schockley Stacking Fault (SSF) occurs at the position of the Basal Plane Dislocation (BPD) or the basal plane of other dislocations.
  • BPD Basal Plane Dislocation
  • BPD Basal Plane Dislocation
  • BPD Basal Plane Dislocation
  • the traditional MOSFET in its cell structure, in addition to the MOS structure, there is still a parasitic PiN diode (Body Diode) in the body.
  • a more effective way is to use SBD and MOSFET in anti-parallel as its freewheeling diode; however, anti-parallel connection of MOSFET and SBD at the chip level will increase the cost of power module packaging and due to additional keys.
  • the stray inductance caused by the wire bonding increases, resulting in a decrease in the electrical performance of the power module.
  • the present disclosure provides a cell structure of a silicon carbide MOSFET device and a silicon carbide MOSFET device.
  • the present disclosure provides a cell structure of a silicon carbide MOSFET device, including:
  • a silicon carbide substrate of the first conductivity type A silicon carbide substrate of the first conductivity type
  • Second conductivity type well regions located on both sides of the cell structure and arranged in the surface of the drift layer;
  • a gate structure located in the center of the cell structure and in contact with the source region, the well region, and the drift layer, wherein the gate structure includes a gate electrode and a gate structure for connecting the gate electrode with the source region and the drift layer.
  • the well region and the gate insulating layer isolated from the drift layer;
  • a source metal layer located above the source region and forming an ohmic contact with the source region
  • the drift layer is downwardly provided with side trenches in the area not covered by the well region; wherein, the side trenches are adjacent to the well region but are not connected to the drift layer.
  • the side trench is provided with a Schottky metal layer that forms a Schottky contact with the drift layer under the side trench.
  • the depth of the side trench is smaller than the depth of the well region.
  • it further includes a second conductivity type enhanced region, the enhanced region being arranged side by side with the source region in the well region in a manner farther away from the center of the cell structure than the source region
  • the ion doping concentration of the enhanced region is greater than the ion doping concentration of the well region
  • the source metal is located on the source region and the enhancement region at the same time.
  • the depth of the enhancement region is greater than or equal to the depth of the well region, so that the bottom of the enhancement region can contact the drift layer under the well region.
  • the gate structure includes a polysilicon planar gate structure
  • the gate insulating layer of the planar gate structure is located above the source region, the well region, and the drift layer, and is in contact with the surface of the source region, the well region, and the drift layer at the same time;
  • the gate of the planar gate structure is arranged above the gate insulating layer.
  • the gate structure includes a polysilicon trench gate structure
  • the drift layer surface is downwardly provided with a gate trench adjacent to the well region, wherein the depth of the gate trench is greater than the depth of the well region and the gate trench
  • the sidewall of the groove is in contact with the source region, the well region and the drift layer;
  • the gate insulating layer of the trench gate structure is disposed on the bottom and the wall of the gate trench, and is used to connect the gate of the trench gate structure disposed in the gate trench to the gate insulating layer.
  • the source region, the well region and the drift layer are isolated.
  • the Schottky metal layer is in contact with the source metal layer to form an electrical connection.
  • the Schottky metal layer is separated from the source metal layer, and an electrical connection is formed through the upper source block metal layer.
  • the gate is isolated from the source metal layer, the source bulk metal layer, and the Schottky metal layer through an interlayer dielectric layer.
  • the present disclosure provides a silicon carbide MOSFET device, which includes several cell structures of the silicon carbide MOSFET device described in the first aspect.
  • the present disclosure provides a cell structure of a silicon carbide MOSFET device and a silicon carbide MOSFET device.
  • the SBD and the MOSFET share a part of the chip area, which improves the use efficiency of the chip area and further improves the overall power of the chip Density, reduce the cost of power module packaging.
  • the integration of SBD in the shallow groove on the chip can also reduce the on-state resistance of the SBD, inhibit the opening of the internal parasitic PiN tube, improve the bipolar degradation effect of the silicon carbide device, improve the reliability of the chip, and optimize the SBD part and the MOSFET part. Area ratio relationship.
  • Figure 1 is a schematic cross-sectional structure diagram of the cell structure of a conventional silicon carbide MOSFET device
  • FIG. 2 is a schematic cross-sectional structure diagram of a cell structure of a silicon carbide MOSFET device with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a cell structure of another silicon carbide MOSFET device with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional structure diagram of a cell structure of another silicon carbide MOSFET device with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional structure diagram of a cell structure of another silicon carbide MOSFET device with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional structure diagram of a cell structure of a silicon carbide MOSFET device with a trench gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional structure diagram of a cell structure of another silicon carbide MOSFET device with a trench gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic cross-sectional structure diagram of a cell structure of another silicon carbide MOSFET device with a trench gate structure according to an exemplary embodiment of the present disclosure
  • Fig. 9 is a schematic cross-sectional structure diagram of a cell structure of another silicon carbide MOSFET device with a trench gate structure according to an exemplary embodiment of the present disclosure.
  • first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections are not Should be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
  • spatial relationship terms such as “above”, “above”, “below”, “below”, etc., may be used here for the convenience of description to describe The relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship term is intended to also include different orientations of the device in use and operation. For example, if the figure is attached The device in is turned over, and then elements or features described as “below other elements” will be oriented “on” the other elements or features. Therefore, the exemplary terms “under” and “under” “Can include both top and bottom orientations. The device can be otherwise oriented (rotated by 90 degrees or other orientations) and the space descriptors used here are interpreted accordingly.
  • the embodiments of the present disclosure are described here with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure. In this way, changes from the shown shape due to, for example, manufacturing techniques and/or tolerances can be expected. Therefore, the embodiments of the present disclosure should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, preparation.
  • the implanted region shown as a rectangle usually has round or curved features and/or implant concentration gradients at its edges, rather than a binary change from an implanted region to a non-implanted region.
  • the buried region formed by the implantation may result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figure are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.
  • an embodiment of the present disclosure provides a cell structure 200 of a silicon carbide MOSFET device with a planar gate structure, which includes: a SiC substrate 201, a drift layer 202, a well region 203, a source region 204, and a source metal
  • the SiC substrate 201 is a SiC substrate of the first conductivity type.
  • the drift layer 202 is a drift layer of the first conductivity type and is located above the SiC substrate 201. According to the different chip withstand voltage capability, the doping concentration and thickness of the drift layer 202 are adjusted.
  • the well region 203 is a well region of the second conductivity type, located on both sides of the cell structure 200 in the drift layer 202, and the upper surface of the well region 203 is flush with the upper surface of the drift layer 202.
  • the source region 204 is a source region of the first conductivity type, located in the well region 203, and the upper surface is flush with the upper surface of the drift layer 202.
  • the width of the source region 204 is smaller than the width of the well region 203, and there is a width difference between the two ends of the well region 203 and the source region 204, and a channel is formed between the width difference near the center of the cell structure 200 and the gate insulating layer 209 (not shown in the figure). Mark), the area between two adjacent channels is the JFET region 205.
  • the area of the drift layer 202 that is not covered by the well region 203 is provided with side trenches (not marked in the figure) downwards.
  • the side trenches are adjacent to the well region 203 but not to the source region 204. contact.
  • the groove depth of the side trench is smaller than the depth of the well region 203.
  • the Schottky metal layer 208 is disposed in the side trench and forms a Schottky contact with the drift layer 202 under the side trench to form a Schottky barrier diode (SBD).
  • the Schottky metal layer 208 may be a metal such as titanium and nickel.
  • the source metal layer 207 is located above the source region 204 and forms an ohmic contact with the source region 204.
  • the source metal 207 cannot be in contact with the drift layer 202.
  • the source metal 207 may be a metal with low contact resistivity such as aluminum.
  • the cell structure 200 may further include an enhanced region 206 of the second conductivity type, and the enhanced region 206 is arranged side by side with the source region 204 in a manner farther away from the center of the cell structure than the source region 204 In the well region 203; wherein the ion doping concentration of the enhanced region 206 is greater than the ion doping concentration of the well region 203.
  • the depth of the enhancement region 206 is greater than or equal to the depth of the well region 203 so that the bottom of the enhancement region 206 can be in contact with the drift layer 202 under the well region 203.
  • the source metal layer 207 is located above the source region 204 and the enhancement region 206 at the same time, and the depth of the side trench is smaller than the depth of the well region 203 and greater than one-fifth of the depth of the enhancement region 206.
  • This cell structure 200 can not only reduce the influence of the parasitic BJT in the MOSFET, but also protect the Schottky junction when the SBD is reverse biased, and reduce the SBD reverse bias leakage current.
  • the enhanced regions 206 located at both ends of the chip can also be used as the field limiting ring of the chip terminal, thus reducing the manufacturing cost of the chip.
  • the sidewalls of the side trenches may be located at the edges of the reinforced area 206; for example, as shown in FIG. 4, the sidewalls of the etching groove may also be located inside the reinforced area 206, that is, the The side trenches may extend into the reinforcement area 206.
  • the Schottky metal layer 208 and the source metal layer 207 may be in contact, or even cover the source metal layer 207 to form an electrical connection; for example, as shown in FIG. 5, it may also be It is selected to be isolated from the source metal layer and connected through the source block metal layer 212.
  • the planar gate structure is located in the center of the cell structure 200 and includes a gate insulating layer 209 and a gate 210.
  • the gate insulating layer 209 is located above the drift layer 202 and is in contact with the surfaces of the source region 204, the well region 203 and the drift layer 202 at the same time, and is used to isolate the gate 210 from the source region 204, the well region 203 and the drift layer 202.
  • a channel (not marked in the figure) is formed between the gate insulating layer 209 and the well region 203, and the thickness of the gate insulating layer 209 is greater than 50 nm.
  • the gate 210 is located above the gate insulating layer 209, and the gate 210 is a polysilicon gate.
  • the interlayer dielectric layer 211 is located above the gate 210 and is used to isolate the gate 210 from the source metal layer 207, the source bulk metal layer 212, and the Schottky metal layer 208.
  • the source compact metal layer 212 is located above the interlayer dielectric layer 211 and simultaneously covers the interlayer dielectric layer 211, the source metal layer 207 and the Schottky metal layer 208, and is electrically connected to the source metal layer 207 and the Schottky metal layer 208 .
  • the drain metal layer 213 is located under the SiC substrate 201 and forms an ohmic contact with the SiC substrate 201.
  • the first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the SBD and the MOSFET share a part of the chip area, which improves the efficiency of chip area usage, further improves the overall power density of the chip, and reduces module packaging costs.
  • the integration of SBD in the shallow groove on the chip can also reduce the on-state resistance of the SBD, inhibit the opening of the internal parasitic PiN tube, improve the bipolar degradation effect of the silicon carbide device, improve the reliability of the chip, and optimize the SBD part and the MOSFET part. Area ratio relationship.
  • an embodiment of the present disclosure provides another cell structure 300 of a silicon carbide MOSFET device, which includes: a SiC substrate 301, a drift layer 302, a gate insulating layer 303, a gate 304, a well region 305, The source region 306, the source metal layer 308, the Schottky metal layer 309, the interlayer dielectric layer 310, the source bulk metal layer 311, and the drain metal layer 312.
  • the SiC substrate 301 is a SiC substrate of the first conductivity type.
  • the drift layer 302 is a drift layer of the first conductivity type and is located above the SiC substrate 301. According to the different chip withstand voltage capability, the doping concentration and thickness of the drift layer 302 are adjusted.
  • a trench gate structure is provided in the center of the cell structure 300, which includes a gate insulating layer 303 and a gate 304.
  • a gate trench (not marked in the figure) adjacent to the well region 305 is provided on the surface of the drift layer 302 downward, wherein the depth of the gate trench is greater than the depth of the well region 305 and the gate
  • the sidewall of the trench is in contact with the source region 306, the well region 305, and the drift layer 302.
  • the gate insulating layer 303 is provided on the bottom and the wall of the gate trench, and is used to isolate the polysilicon gate 304 provided in the gate trench from the source region 306, the well region 305 and the drift layer 302, and the gate insulation
  • the thickness of layer 303 is greater than 50 nm.
  • the well region 305 is a well region of the second conductivity type, which is located on both sides of the cell structure 300 in the drift layer 302, and the upper surface is flush with the upper surface of the drift layer 302.
  • One end of the well region 305 close to the center of the cell structure is in contact with the gate insulating layer 303 to form a channel between the well region 305 and the gate insulating layer 303 (not marked in the figure).
  • the source region 306 is a source region of the first conductivity type, located in the well region 305, and the upper surface is flush with the upper surface of the drift layer 302.
  • the width of the source region 306 is smaller than the width of the well region 305, and an end of the source region 306 close to the center of the cell structure is in contact with the gate insulating layer 303.
  • the area of the drift layer 302 that is not covered by the well region 305 is provided with side trenches (not marked in the figure) downwards.
  • the side trenches are adjacent to the well region 305 but not to the source region 306. contact.
  • the groove depth of the side trench is smaller than the depth of the well region 305.
  • the Schottky metal layer 309 is disposed in the side trench and forms a Schottky contact with the drift layer 302 under the side trench to form a Schottky barrier diode (SBD).
  • the Schottky metal layer 309 may be a metal such as titanium and nickel.
  • the source metal layer 308 is located above the source region 306 and forms an ohmic contact with the source region 306.
  • the source metal 308 cannot be in contact with the drift layer 302.
  • the source metal 308 may be a metal with low contact resistivity such as aluminum.
  • the cell structure 300 may further include an enhanced region 307 of the second conductivity type.
  • the enhanced region 307 is arranged side by side with the source region 306 in a manner farther from the center of the cell structure than the source region 306.
  • the ion doping concentration of the enhanced region 307 is greater than the ion doping concentration of the well region 305.
  • the depth of the enhancement region 307 is greater than or equal to the depth of the well region 305 so that the bottom of the enhancement region 307 can contact the drift layer 302 under the well region 305.
  • the source metal layer 311 is located above the source region 306 and the enhancement region 307 at the same time, and the depth of the side trench is smaller than the depth of the well region 305 and greater than one-fifth of the depth of the enhancement region 307.
  • This cell structure 300 can not only reduce the influence of the parasitic BJT in the MOSFET, but also protect the Schottky junction when the SBD is reverse biased, and reduce the SBD reverse bias leakage current.
  • the enhanced regions 307 located at both ends of the chip can also be used as a field limiting ring of the chip terminal, thereby reducing the manufacturing cost of the chip.
  • the sidewall of the side trench may be located at the edge of the reinforced area 307; for example, as shown in FIG. 8, the sidewall of the side trench may be located inside the reinforced area 307, namely The side groove can extend into the reinforcement area 307.
  • the Schottky metal layer 309 and the source metal layer 308 may be in contact, or even cover the source metal layer 308 to form an electrical connection; for example, as shown in FIG. 9, it may also be It is selected to be isolated from the source metal layer and connected through the source block metal layer 311.
  • the interlayer dielectric layer 310 is located above the drift layer 302 and is used to isolate the gate 304 from the source metal layer 308, the source bulk metal layer 311 and the Schottky metal layer 309.
  • the source compact metal layer 311 is located above the interlayer dielectric layer 310 and simultaneously covers the interlayer dielectric layer 310, the source metal layer 308 and the Schottky metal layer 309, and is electrically connected to the source metal layer 308 and the Schottky metal layer 309 .
  • the drain metal layer 312 is located under the SiC substrate 301 and forms an ohmic contact with the SiC substrate 301.
  • the first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the SBD and the MOSFET share a part of the chip area, which improves the use efficiency of the chip area, further improves the overall power density of the chip, and reduces the module packaging cost.
  • the integration of SBD in the shallow groove on the chip can also reduce the on-state resistance of the SBD, inhibit the turning on of the internal parasitic PiN tube, improve the bipolar degradation effect of the silicon carbide device, improve the reliability of the chip, and optimize the SBD part and the MOSFET part. Area ratio relationship.
  • this embodiment provides a cell structure 200 of an N-type silicon carbide MOSFET device with a planar gate structure, as shown in FIG. 2, which includes: an N-type substrate 201 and an N-type drift layer 202 , P-well region 203, N+ source region 204, source metal layer 207, Schottky metal layer 208, gate insulating layer 209, gate 210, interlayer dielectric layer 211, source bulk metal layer 212 and drain metal ⁇ 213.
  • a P+ enhancement area 206 may also be included.
  • the ion doping concentration of the N-type substrate 201 is 1E18 cm -3 to 1E19 cm -3 .
  • the ion doping concentration of the N-type drift layer 202 ranges from 1E14 cm ⁇ 3 to 5E16 cm ⁇ 3 , which needs to be optimized according to the chip withstand voltage.
  • the ion doping concentration of the P-well region 203 ranges from 1E16 cm -3 to 5E18 cm -3 , and the depth of the P-well region 203 is 1 um.
  • the ion doping concentration of the N+ source region 204 is 1E19 cm ⁇ 3 .
  • the ion doping concentration of the P+ enhanced region 206 is greater than that of the P-well region 203 and is greater than 1E18 cm ⁇ 3 , and the depth of the P+ enhanced region 206 is greater than 1 um.
  • the ion doping concentration of the N-type SiC substrate 201 ranges from 1E18 to 1E19 cm ⁇ 3 .
  • the gate 210 is an N-type polysilicon gate with an ion doping concentration greater than 1E18 cm ⁇ 3 .
  • the SBD and the MOSFET share a part of the chip area, which improves the efficiency of the chip area, further increases the overall power density of the chip, and reduces the cost of module packaging.
  • the integration of SBD in the shallow groove on the chip can also reduce the on-state resistance of the SBD, inhibit the opening of the internal parasitic PiN tube, improve the bipolar degradation effect of the silicon carbide device, improve the reliability of the chip, and optimize the SBD part and the MOSFET part. Area ratio relationship.

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Abstract

一种碳化硅MOSFET器件的元胞结构（200）及碳化硅MOSFET器件。该碳化硅MOSFET器件的元胞结构（200）包括：位于元胞结构（200）两侧且在所述漂移层（202）表面内设置的第二导电类型阱区（203）、位于所述阱区（203）表面内的第一导电类型源区（204）和位于元胞结构（200）中心且与所述源区（204）、所述阱区（203）以及所述漂移层（202）接触的栅结构。还包括位于所述源区（204）上方且与所述源区（204）形成欧姆接触的源极金属层（207），在元胞结构（200）两侧，所述漂移层（202）于其未被所述阱区（203）覆盖的区域向下设置有侧部沟槽，所述侧部沟槽中设置有与所述侧部沟槽下方的所述漂移层（202）形成肖特基接触的肖特基金属层（208）。通过在碳化硅MOSFET器件的元胞结构集成了SBD，改善碳化硅双极退化现象，提高芯片可靠性，并达到了降低模块封装成本和提高模块电气特性的目的。

Description

碳化硅MOSFET器件的元胞结构及碳化硅MOSFET器件
本公开要求享有2019年11月09日提交的名称为“碳化硅MOSFET器件的元胞结构及碳化硅MOSFET器件”的中国专利申请2019110893814的优先权，其全部内容通过引用并入本文中。
技术领域
本公开涉及半导体器件技术领域，具体涉及一种碳化硅MOSFET器件的元胞结构及碳化硅MOSFET器件。
背景技术
碳化硅(SiC)是新型宽禁带半导体材料，具有出色的物理、化学和电性能，例如，碳化硅的击穿电场强度是传统硅的10倍、导热率是硅的3倍等，这使得碳化硅在功率半导体器件，特别是大功率和高温应用环境中非常具有吸引力和应用前景。
碳化硅单极器件(金属-氧化物半导体场效应晶体MOSFET、肖特基势垒二极管SBD)比双极器件(PiN二极管、绝缘栅双极型晶体管IGBT、晶闸管等)更具有优势，这不仅因为与碳化硅PN结内在2V的开启电压有关，更是由于碳化硅双极器件存在着“双极退化”现象，即在载子注入(或激发)之后进行复合，单个肖克莱型堆垛层错(Schockley Stacking Fault,SSF)的成核和扩展发生在基面位错(Basal Plane Dislocation,BPD)的位置或其他位错的基失面段，扩展的SSF导致载流子寿命的显著降低从而使碳化硅双极性器件压降增大、反向偏置漏电流增大，不利于碳化硅双极性器件的可靠性。
传统的MOSFET，如图1所示，在其元胞结构中除MOS结构外仍寄生了一个体内PiN二极管(Body Diode)。为了抑制碳化硅MOSFET中PiN二极管的开启，较为有效的办法是采用SBD与MOSFET反并联使用，作为其续流二极管；然而在芯片级别反并联MOSFET和SBD会增加功率模块封装的成本和由于额外键合线引起的杂散电感增加，导致功率模块电气性能的下降。
发明内容
针对上述问题，本公开提供了一种碳化硅MOSFET器件的元胞结构及碳化硅MOSFET器件。
第一方面，本公开提供一种碳化硅MOSFET器件的元胞结构，包括：
第一导电类型碳化硅衬底；
位于所述衬底上方的第一导电类型漂移层；
位于元胞结构两侧且在所述漂移层表面内设置的第二导电类型阱区；
位于所述阱区表面内的第一导电类型源区；
位于元胞结构中心且与所述源区、所述阱区以及所述漂移层接触的栅结构，其中，所述栅结构包括栅极和用于将所述栅极与所述源区、所述阱区以及所述漂移层隔离的栅极绝缘层；
位于所述源区上方且与所述源区形成欧姆接触的源极金属层；
在元胞结构两侧，所述漂移层于其未被所述阱区覆盖的区域向下设置有侧部沟槽；其中，所述侧部沟槽与所述阱区相邻但不与所述源区接触；
所述侧部沟槽中设置有与所述侧部沟槽下方的所述漂移层形成肖特基接触的肖特基金属层。
根据本公开的实施例，优选地，所述侧部沟槽的深度小于所述阱区的深度。
根据本公开的实施例，优选地，还包括第二导电类型增强区，所述增强区以比所述源区更加远离元胞结构中心的方式与所述源区并排设置在所述阱区内；其中，所述增强区的离子掺杂浓度大于所述阱区的离子掺杂浓度；
所述源极金属同时位于所述源区和所述增强区上。
根据本公开的实施例，优选地，所述增强区的深度大于或等于所述阱区的深度，使得所述增强区的底部能够与所述阱区下方的所述漂移层接触。
根据本公开的实施例，优选地，
所述阱区表面靠近元胞结构中心的一侧未被所述源区完全覆盖；
所述栅结构包括多晶硅平面栅结构；
所述平面栅结构的栅极绝缘层位于所述源区、阱区以及所述漂移层的上方，并与所述源区、所述阱区以及所述漂移层的表面同时接触；
所述栅极绝缘层的上方设置有所述平面栅结构的栅极。
根据本公开的实施例，优选地，
所述阱区表面靠近元胞结构中心的一侧被所述源区完全覆盖；
所述栅结构包括多晶硅沟槽栅结构；
在元胞结构中心，所述漂移层表面向下设置有与所述阱区邻接的栅极沟槽，其中，所述栅极沟槽的深度大于所述阱区的深度且所述栅极沟槽的侧壁与所述源区、所述阱区以及所述漂移层接触；
所述沟槽栅结构的栅极绝缘层设置在所述栅极沟槽的底部和壁部上，用于将设置在所述栅极沟槽中的所述沟槽栅结构的栅极与所述源区、所述阱区以及所述漂移层隔离。
据本公开的实施例，优选地，所述肖特基金属层与所述源极金属层接触，以形成电连 接。
据本公开的实施例，优选地，所述肖特基金属层与所述源极金属层隔离设置，并通过上方的源压块金属层形成电连接。
据本公开的实施例，优选地，所述栅极通过层间介质层与所述源极金属层和所述源压块金属层以及所述肖特基金属层隔离。
第二方面，本公开提供一种碳化硅MOSFET器件，包括若干如第一方面所述的碳化硅MOSFET器件的元胞结构。
采用上述技术方案，至少能够达到如下技术效果：
本公开提供一种碳化硅MOSFET器件的元胞结构及碳化硅MOSFET器件，通过在SiC MOSFET器件元胞内集成SBD，使SBD与MOSFET共用芯片部分区域，提高芯片面积使用效率，进一步提高芯片整体功率密度、降低功率模块封装成本。同时SBD集成于芯片上的浅槽中还可以降低SBD通态电阻，抑制体内寄生PiN管的开启，改善碳化硅器件的双极退化效应，提高芯片的可靠性，并优化SBD部分与MOSFET部分的面积比例关系。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是传统的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图2是本公开一示例性实施例示出的一种平面栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图3是本公开一示例性实施例示出的另一种平面栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图4是本公开一示例性实施例示出的另一种平面栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图5是本公开一示例性实施例示出的另一种平面栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图6是本公开一示例性实施例示出的一种沟槽栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图7是本公开一示例性实施例示出的另一种沟槽栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图8是本公开一示例性实施例示出的另一种沟槽栅结构的碳化硅MOSFET器件的元胞结构的剖面结构示意图；
图9是本公开一示例性实施例示出的另一种沟槽栅结构的碳化硅MOSFET器件的元 胞结构的剖面结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本公开的实施方式，借此对本公开如何应用技术手段来解决技术问题，并达到相应技术效果的实现过程能充分理解并据以实施。本公开实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本公开的保护范围之内。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应理解，尽管可使用术语“第一”、“第二”、“第三”等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
应理解，空间关系术语例如“在...上方”、位于...上方”、“在...下方”、“位于...下方”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下方”的元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下方”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述本公开的实施例。这样，可以预期由于例如制备技术和/或容差导致的从所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制备导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本公开的范围。
为了彻底理解本公开，将在下列的描述中提出详细的结构以及步骤，以便阐释本公开提出的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
实施例一
如图2所示，本公开实施例提供一种平面栅结构的碳化硅MOSFET器件的元胞结构200，其包括：SiC衬底201、漂移层202、阱区203、源区204、源极金属层207、肖特基金属层208、栅极绝缘层209、栅极210、层间介质层211、源压块金属层212和漏极金属层213。
示例性地，SiC衬底201为第一导电类型的SiC衬底。
漂移层202为第一导电类型的漂移层，位于SiC衬底201上方。根据芯片耐压能力不同，调整漂移层202的掺杂浓度和厚度。
阱区203为第二导电类型的阱区，位于元胞结构200两侧、漂移层202内，且阱区203上表面与漂移层202的上表面相平齐。
源区204为第一导电类型的源区，位于阱区203内，且上表面与漂移层202的上表面相平齐。源区204的宽度小于阱区203的宽度，阱区203与源区204两端均有宽度差，靠近元胞结构200中心的宽度差与栅极绝缘层209之间形成沟道(图中未标注)，相邻两个沟道之间的区域为JFET区205。
元胞结构200两侧，漂移层202未被阱区203覆盖的区域向下设置有侧部沟槽(图中未标注)，该侧部沟槽与阱区203相邻但不与源区204接触。该侧部沟槽的槽深小于阱区203的深度。
肖特基金属层208设置于该侧部沟槽内，并与该侧部沟槽下方的漂移层202形成肖特基接触，以形成肖特基势垒二极管(SBD)。肖特基金属层208可以为钛、镍等金属。
源极金属层207位于源区204上方，并与源区204形成欧姆接触。其中源极金属207不能与漂移层202接触。源极金属207可以为铝等具有低接触电阻率的金属。
在本实施例中，例如图3所示，元胞结构200还可以包括第二导电类型的增强区206，增强区206以比源区204更加远离元胞结构中心的方式与源区204并排设置在阱区203内；其中，增强区206的离子掺杂浓度大于阱区203的离子掺杂浓度。增强区206的深度大于或等于阱区203的深度，使得增强区206的底部能够与阱区203下方的漂移层202接触。此时，源极金属层207同时位于源区204和增强区206上方，侧部沟槽深度小于阱区203的深度大于增强区206的深度的五分之一。这种元胞结构200既可以降低MOSFET内寄生BJT的影响，也可以在SBD反向偏置时对肖特基结起保护作用，降低SBD反偏漏电流。同时位于芯片两端的增强区206还可以用做芯片终端的限场环，因此降低了芯片的制造成 本。
这种结构中，例如图3所示，侧部沟槽的侧壁可以位于增强区206的边缘；例如图4所示，该刻蚀槽的侧壁也可以位于增强区206的内部，即该侧部沟槽可延伸至增强区206内。
在本实施例中，例如图3所示，肖特基金属层208与源极金属层207可以接触，甚至覆盖于源极金属层207上方，以形成电连接；例如图5所示，也可以选择与源极金属层隔离设置，并通过源压块金属层212连接。
平面栅结构位于元胞结构200的中心，包括栅极绝缘层209和栅极210。
其中栅极绝缘层209位于漂移层202上方，并与源区204、阱区203和漂移层202的表面同时接触，用于将栅极210与源区204、阱区203和漂移层202隔离开，其中，栅极绝缘层209与阱区203之间形成沟道(图中未标注)，栅极绝缘层209的厚度大于50nm。栅极210位于栅极绝缘层209上方，栅极210为多晶硅栅极。
层间介质层211位于栅极210上方，用于将栅极210与源极金属层207、源压块金属层212和肖特基金属层208隔离开。
源压块金属层212位于层间介质层211上方并同时覆盖层间介质层211、源极金属层207和肖特基金属层208，与源极金属层207和肖特基金属层208电连接。
漏极金属层213位于SiC衬底201下方的，与SiC衬底201形成欧姆接触。
对应地，第一导电类型和所述第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
在本实施例中，通过在平面栅结构的SiC MOSFET器件的元胞内集成SBD，使SBD与MOSFET共用芯片部分区域，提高芯片面积使用效率，进一步提高芯片整体功率密度、降低模块封装成本。同时SBD集成于芯片上的浅槽中还可以降低SBD通态电阻，抑制体内寄生PiN管的开启，改善碳化硅器件的双极退化效应，提高芯片的可靠性，并优化SBD部分与MOSFET部分的面积比例关系。
实施例二
如图6所示，本公开实施例提供另一种碳化硅MOSFET器件的元胞结构300，其包括：SiC衬底301、漂移层302、栅极绝缘层303、栅极304、阱区305、源区306、源极金属层308、肖特基金属层309、层间介质层310、源压块金属层311和漏极金属层312。
示例性地，SiC衬底301为第一导电类型的SiC衬底。
漂移层302为第一导电类型的漂移层，位于SiC衬底301上方。根据芯片耐压能力不同，调整漂移层302的掺杂浓度和厚度。
元胞结构300中心设有沟槽栅结构，包括栅极绝缘层303和栅极304,。在元胞结构 300中心，漂移层302表面向下设置有与阱区305邻接的栅极沟槽(图中未标注)，其中，该栅极沟槽的深度大于阱区305的深度且栅极沟槽的侧壁与源区306、阱区305以及漂移层302接触。
栅极绝缘层303设置在栅极沟槽的底部和壁部上，用于将设置在栅极沟槽中的多晶硅栅极304与源区306、阱区305以及漂移层302隔离，栅极绝缘层303的厚度大于50nm。
阱区305为第二导电类型的阱区，位于元胞结构300两侧、漂移层302内，且上表面与漂移层302的上表面相平齐。阱区305靠近元胞结构中心的一端与栅极绝缘层303接触，以在阱区305与栅极绝缘层303之间形成沟道(图中未标注)。
源区306为第一导电类型的源区，位于阱区305内，且上表面与漂移层302的上表面相平齐。源区306的宽度小于阱区305的宽度，源区306靠近元胞结构中心的一端与栅极绝缘层303接触。
元胞结构300两侧，漂移层302未被阱区305覆盖的区域向下设置有侧部沟槽(图中未标注)，该侧部沟槽与阱区305相邻但不与源区306接触。该侧部沟槽的槽深小于阱区305的深度。
肖特基金属层309设置于该侧部沟槽内，并与该侧部沟槽下方的漂移层302形成肖特基接触，以形成肖特基势垒二极管(SBD)。肖特基金属层309可以为钛、镍等金属。
源极金属层308位于源区306上方，并与源区306形成欧姆接触。其中源极金属308不能与漂移层302接触。源极金属308可以为铝等具有低接触电阻率的金属。
在本实施例中，例如图7所示，元胞结构300还可以包括第二导电类型的增强区307，增强区307以比源区306更加远离元胞结构中心的方式与源区306并排设置在阱区305内；其中，增强区307的离子掺杂浓度大于阱区305的离子掺杂浓度。增强区307的深度大于或等于阱区305的深度，使得增强区307的底部能够与阱区305下方的漂移层302接触。此时，源极金属层311同时位于源区306和增强区307上方，侧部沟槽深度小于阱区305的深度大于增强区307的深度的五分之一。这种元胞结构300既可以降低MOSFET内寄生BJT的影响，也可以在SBD反向偏置时对肖特基结起保护作用，降低SBD反偏漏电流。同时位于芯片两端的增强区307还可以用做芯片终端的限场环，因此降低了芯片的制造成本。
这种结构中，例如图7所示，该侧部沟槽的侧壁可以位于增强区307的边缘；例如图8所示，该侧部沟槽的侧壁可以位于增强区307的内部，即该侧部沟槽可延伸至增强区307内。
在本实施例中，例如图7所示，肖特基金属层309与源极金属层308可以接触，甚至覆盖于源极金属层308上方，以形成电连接；例如图9所示，也可以选择与源极金属层隔离设置，并通过源压块金属层311连接。
层间介质层310位于漂移层302上方，用于将栅极304与源极金属层308、源压块金属层311和肖特基金属层309隔离开。
源压块金属层311位于层间介质层310上方并同时覆盖层间介质层310、源极金属层308和肖特基金属层309，与源极金属层308和肖特基金属层309电连接。
漏极金属层312位于SiC衬底301下方的，与SiC衬底301形成欧姆接触。
对应地，第一导电类型和所述第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。
在本实施例中，通过在沟槽栅结构的SiC MOSFET器件的元胞内集成SBD，使SBD与MOSFET共用芯片部分区域，提高芯片面积使用效率，进一步提高芯片整体功率密度、降低模块封装成本。同时SBD集成于芯片上的浅槽中还可以降低SBD通态电阻，抑制体内寄生PiN管的开启，改善碳化硅器件的双极退化效应，提高芯片的可靠性，并优化SBD部分与MOSFET部分的面积比例关系。
实施例三
在实施例一的基础上，本实施例提供一种平面栅结构的N型碳化硅MOSFET器件的元胞结构200，如图2所示，其包括：N型衬底201、N型漂移层202、P阱区203、N+源区204、源极金属层207、肖特基金属层208、栅极绝缘层209、栅极210、层间介质层211、源压块金属层212和漏极金属层213。
如图3所示，还可以包括P+增强区206。
上述各部分的位置关系与实施例一相同，本实施例中不再赘述。
具体地，N型衬底201的离子掺杂浓度为1E18cm -3至1E19cm -3。
N型漂移层202的离子掺杂浓度范围为1E14cm -3至5E16cm -3，具体需要根据芯片耐压来优化。
P阱区203的离子掺杂浓度范围为1E16cm -3至5E18cm -3，P阱区203的深度为1um。
N+源区204的离子掺杂浓度为1E19cm -3。
P+增强区206的离子掺杂浓度大于P阱区203的离子掺杂浓度，且大于1E18cm -3，P+增强区206的深度大于1um。
具体地，N型SiC衬底201的离子掺杂浓度范围为1E18至1E19cm -3。
栅极210为N型的多晶硅栅极，离子掺杂浓度大于1E18cm -3。
在本实施例中，通过在平面栅结构的N型SiC MOSFET器件的元胞内集成SBD，使SBD与MOSFET共用芯片部分区域，提高芯片面积使用效率，进一步提高芯片整体功率密度、降低模块封装成本。同时SBD集成于芯片上的浅槽中还可以降低SBD通态电阻，抑制体内寄生PiN管的开启，改善碳化硅器件的双极退化效应，提高芯片的可靠性，并优 化SBD部分与MOSFET部分的面积比例关系。
以上仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。虽然本公开所公开的实施方式如上，但的内容只是为了便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属技术领域内的技术人员，在不脱离本公开所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种碳化硅MOSFET器件的元胞结构，其中，包括：
    第一导电类型碳化硅衬底；
    位于所述衬底上方的第一导电类型漂移层；
    位于元胞结构两侧且在所述漂移层表面内设置的第二导电类型阱区；
    位于所述阱区表面内的第一导电类型源区；
    位于元胞结构中心且与所述源区、所述阱区以及所述漂移层接触的栅结构，其中，所述栅结构包括栅极和用于将所述栅极与所述源区、所述阱区以及所述漂移层隔离的栅极绝缘层；
    位于所述源区上方且与所述源区形成欧姆接触的源极金属层；
    在元胞结构两侧，所述漂移层于其未被所述阱区覆盖的区域向下设置有侧部沟槽；其中，所述侧部沟槽与所述阱区相邻但不与所述源区接触；
    所述侧部沟槽中设置有与所述侧部沟槽下方的所述漂移层形成肖特基接触的肖特基金属层。
  2. 据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，所述侧部沟槽的深度小于所述阱区的深度。
  3. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，还包括第二导电类型增强区，所述增强区以比所述源区更加远离元胞结构中心的方式与所述源区并排设置在所述阱区内；其中，所述增强区的离子掺杂浓度大于所述阱区的离子掺杂浓度；
    所述源极金属层同时位于所述源区和所述增强区上方。
  4. 根据权利要求3所述的碳化硅MOSFET器件的元胞结构，其中，
    所述增强区的深度大于或等于所述阱区的深度，使得所述增强区的底部能够与所述阱区下方的所述漂移层接触。
  5. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中：
    所述阱区表面靠近元胞结构中心的一侧未被所述源区完全覆盖；
    所述栅结构包括多晶硅平面栅结构；
    所述平面栅结构的栅极绝缘层位于所述源区、阱区以及所述漂移层的上方，并与所述源区、所述阱区以及所述漂移层的表面同时接触；
    所述栅极绝缘层的上方设置有所述平面栅结构的栅极。
  6. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中：
    所述阱区表面靠近元胞结构中心的一侧被所述源区完全覆盖；
    所述栅结构包括多晶硅沟槽栅结构；
    在元胞结构中心，所述漂移层表面向下设置有与所述阱区邻接的栅极沟槽，其特征在于，所述栅极沟槽的深度大于所述阱区的深度且所述栅极沟槽的侧壁与所述源区、所述阱区以及所述漂移层接触；
    所述沟槽栅结构的栅极绝缘层设置在所述栅极沟槽的底部和壁部上，用于将设置在所述栅极沟槽中的所述沟槽栅结构的栅极与所述源区、所述阱区以及所述漂移层隔离。
  7. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，所述肖特基金属层与所述源极金属层接触，以形成电连接。
  8. 根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其中，所述肖特基金属层与所述源极金属层隔离设置，并通过上方的源压块金属层形成电连接。
  9. 根据权利要求7或8所述的碳化硅MOSFET器件的元胞结构，其中：
    所述栅极通过层间介质层与所述源极金属层和所述源压块金属层以及所述肖特基金属层隔离。
  10. 一种碳化硅MOSFET器件，其中，包括若干如权利要求1至9任一项所述的碳化硅MOSFET器件的元胞结构。
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