CN109119419A - 一种集成肖特基续流二极管碳化硅槽栅mosfet - Google Patents

一种集成肖特基续流二极管碳化硅槽栅mosfet Download PDF

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CN109119419A
CN109119419A CN201810921041.2A CN201810921041A CN109119419A CN 109119419 A CN109119419 A CN 109119419A CN 201810921041 A CN201810921041 A CN 201810921041A CN 109119419 A CN109119419 A CN 109119419A
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易波
张丙可
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

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Abstract

本发明涉及功率半导体领域,具体提供一种集成肖特基续流二极管碳化硅槽栅MOSFET,用以克服现有的集成肖特基续流二极管的碳化硅槽栅MOSFET元胞面积大、集成度低的缺点。本发明提供碳化硅槽栅MOSFET的元胞结构中,通过深槽正下方设置P+型电场屏蔽区,将肖特基二极管集成在深槽两侧,在集成肖特基二极管的同时实现了其所需的电场屏蔽效果,不仅在碳化硅槽栅MOSFET上集成了续流二极管,且具有低导通损耗和低开关损耗,同时具有高集成度和降低面积成本的优点。

Description

一种集成肖特基续流二极管碳化硅槽栅MOSFET
技术领域
本发明涉及功率半导体领域,具体提供一种具有低导通压降、集成肖特基二极管的、高度集成的碳化硅槽栅MOSFET。
背景技术
碳化硅MOSFET被认为在电力元器件节能方面具有很大优势,与相同耐压的硅基IGBT相比,碳化硅MOSFET在减小导通损耗和开关损耗方面具有很大优势;然而,碳化硅MOSFET中集成的续流二极管存在很大的PN结导通压降。针对此问题,文献“T.Nakamura,Y.Nakano,M.Aketa,et al.“High performance SiC trench devices with ultra-lowron,”Electr on Devices Meeting.IEEE,2011:26.5.1-26.5.3.”中提出一种集成的肖特基续流二极管的SiC槽栅MOSFET,其结构如图1所示,由于肖特基二极管导通压降很低,可以显著地减小碳化硅MOSFET反向续流时的导通压降;但是在MOSFET正向耐压时,即阴极K加正高压,肖特基二极管下方的电场过强将使得器件的泄露电流急剧增大,所以需要在肖特基二极管两侧设计电场屏蔽层P+来保护肖特基结,这就使得单个MOSFET元胞的面积极大地增加,降低了集成度和沟道密度。
发明内容
本发明的目的在于针对现有的集成肖特基续流二极管的碳化硅槽栅MOSFET元胞面积大、集成度低的缺点,提供一种新的集成肖特基续流二极管碳化硅槽栅MOSFET,该碳化硅槽栅MOSFET具有高集成度,在集成肖特基二极管的同时,将单个元胞的面积进一步缩小,极大提高了器件集成度和沟道密度。
为实现上述目的,本发明采用的技术方案为:
一种集成肖特基续流二极管碳化硅槽栅MOSFET,其元胞包括:
N+型衬底8,
位于N+型衬底下的漏电极10,
位于N+型衬底上的N-型漂移区1,
分别位于N-型漂移区上左右两侧的P型基区2,P型基区之间设置的栅电极4,所述栅电极与P型基区之间及栅电极与N-型漂移区之间设置的栅氧化层5,
位于P型基区2内的N+源区3,所述N+源区位于P型基区顶部且紧邻栅电极一侧,
深入一侧P型基区2、且与N-型漂移区1直接接触的深槽6,
以及覆盖所述P型基区2、N+源区3与深槽6的源电极9;
其特征在于,所述元胞还包括一个P+型电场屏蔽区7,所述P+型电场屏蔽区位于深槽6正下方,且所述源电极9于深槽6内侧壁位置与N-型漂移区1形成肖特基接触。
本发明的有益效果在于:
本发明提供一种集成肖特基续流二极管碳化硅槽栅MOSFET,其中,集成肖特基二极管设置在深槽两侧,并且P+型电场屏蔽区设置于肖特基结所在的深槽的正下方,实现对肖特基结的保护;由于将肖特基结和P+电场屏蔽区设置在同一深槽处,本发明极大地降低了MOSFET元胞的面积;进而实现提高碳化硅槽栅MOSFET的集成度和沟道密度的目的,进而降低MOSFET和集成肖特基二极管的导通损耗。
附图说明
图1为现有集成肖特基二极管的SiC槽栅MOSFET结构图。
图2为本发明一种集成肖特基续流二极管碳化硅槽栅MOSFET元胞结构示意图。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
本实施例提供一种集成肖特基续流二极管碳化硅槽栅MOSFET,其元胞结构如图2所示,包括:
N+型衬底8(N型重掺杂SiC区),
位于N+型衬底下的漏电极10(MOSFET漏极),
位于N+型衬底上的N-型漂移区1(N型轻掺杂SiC区),
分别位于N-型漂移区上左右两侧的P型基区2(P型掺杂SiC区),P型基区之间设置的栅电极4(多晶硅区),所述栅电极与P型基区之间及栅电极与N-型漂移区之间设置的栅氧化层5,
位于P型基区2内的N+源区3(N型重掺杂SiC区),所述N+源区位于P型基区顶部且紧邻栅电极一侧,
深入右侧P型基区2、且与N-型漂移区1直接接触的深槽6,
覆盖所述P型基区2、N+源区3与深槽6的源电极9(MOSFET源极);
以及一个P+型电场屏蔽区7(P型重掺杂SiC区),所述P+型电场屏蔽区位于深槽6正下方,且所述源电极9于深槽6内侧壁位置与N-型漂移区1形成肖特基接触。
下面结合如图1所示的现有集成了肖特基续流二极管的碳化硅槽栅MOSFET元胞结构的工作原理对本发明工作原理做进一步说明:
如图1所示,其工作原理简单介绍如下:当器件处于正向耐压时,该结构需要两个深槽下方的P+区来吸收漂移区电离杂质产生的电力线,从而防止肖特基二极管结面产生强电场而导致器件击穿电压急剧下降;当图1所示的器件反向续流时,即肖特基二极管正向导通时,其电流可以从肖特基结底部的三个方向流向二极管的阴极(底部的N+区),如图1中虚线箭头所示;由于电场屏蔽区P+的存在,其往往占据了很大的芯片面积,不利于高集成度;并且,对于SiC MOSFET,其沟道电阻往往占据总电阻较大比例;而图1所示结构降低了SiC器件的沟道密度,使得比导通电阻增加。
本发明如图2所示,通过将电场屏蔽层7置于肖特基二极管阳极区所在的深槽6的正下方,极大节省了芯片面积,提高了集成度,同时增加了沟道密度以及肖特基二极管的有效密度,使得正向和反向的导通电阻均得以降低;当图2所示的器件正向耐压时,P区7虽然没有直接和零电位相连,但是随着漂移区的逐渐耗尽,P区2(零电位)和P区7发生穿通,P区7的电位开始被P区2钳位,漂移区进一步耗尽而产生的电力线将被P区7吸收,从而防止肖特基二极管两侧(如图2虚线箭头所示的两侧)产生高电场,所以P区7可以起到很好的电场屏蔽作用,防止器件击穿电压下降;当器件开始反向续流,即肖特基二极管正向导通时,其电流线如图2虚线箭头所示,由肖特基二极管两侧流入漂移区;从而,本发明在集成肖特基二极管的同时实现了其所需的电场屏蔽效果,不仅在SiC MOSFET上集成了续流二极管,且具有低导通损耗和低开关损耗,同时具有高集成度和降低面积成本的优点。
以上所述,仅为本发明的具体实施方式,本说明书中所公开的任一特征,除非特别叙述,均可被其他等效或具有类似目的的替代特征加以替换;所公开的所有特征、或所有方法或过程中的步骤,除了互相排斥的特征和/或步骤以外,均可以任何方式组合。

Claims (1)

1.一种集成肖特基续流二极管碳化硅槽栅MOSFET,其元胞包括:
N+型衬底(8),
位于N+型衬底下的漏电极(10),
位于N+型衬底上的N-型漂移区(1),
分别位于N-型漂移区上左右两侧的P型基区(2),P型基区之间设置的栅电极(4),所述栅电极与P型基区之间及栅电极与N-型漂移区之间设置的栅氧化层(5),
位于P型基区内的N+源区(3),所述N+源区位于P型基区顶部且紧邻栅电极一侧,
深入一侧P型基区(2)、且与N-型漂移区(1)直接接触的深槽(6),
以及覆盖所述P型基区(2)、N+源区(3)与深槽(6)的源电极(9);
其特征在于,所述元胞还包括一个P+型电场屏蔽区(7),所述P+型电场屏蔽区位于深槽(6)正下方,且所述源电极(9)于深槽(6)内侧壁位置与N-型漂移区(1)形成肖特基接触。
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US10777689B1 (en) 2019-10-18 2020-09-15 Hong Kong Applied Science and Technology Research Institute Company, Limited Silicon-carbide shielded-MOSFET embedded with a trench Schottky diode and heterojunction gate
CN111755519A (zh) * 2020-06-02 2020-10-09 西安电子科技大学 一种集成sbd的碳化硅umosfet器件
CN112786679A (zh) * 2019-11-08 2021-05-11 株洲中车时代电气股份有限公司 碳化硅mosfet器件的元胞结构及碳化硅mosfet器件
CN113193043A (zh) * 2021-04-19 2021-07-30 电子科技大学 一种具有二极管钳位载流子存储层的槽栅igbt器件
CN114551570A (zh) * 2022-02-18 2022-05-27 电子科技大学 一种低功耗功率器件

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CN112786679A (zh) * 2019-11-08 2021-05-11 株洲中车时代电气股份有限公司 碳化硅mosfet器件的元胞结构及碳化硅mosfet器件
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CN113193043A (zh) * 2021-04-19 2021-07-30 电子科技大学 一种具有二极管钳位载流子存储层的槽栅igbt器件
CN114551570A (zh) * 2022-02-18 2022-05-27 电子科技大学 一种低功耗功率器件
CN114551570B (zh) * 2022-02-18 2023-05-26 电子科技大学 一种低功耗功率器件

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