CN109103186A - 一种集成异质结续流二极管碳化硅槽栅mosfet - Google Patents
一种集成异质结续流二极管碳化硅槽栅mosfet Download PDFInfo
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Abstract
本发明涉及功率半导体领域，提供一种集成异质结续流二极管碳化硅槽栅MOSFET，用以克服现有的集成了续流二极管的碳化硅槽栅MOSFET元胞面积大、集成度低的缺点；本发明提供碳化硅槽栅MOSFET的元胞结构中，通过在异质结二极管阳极区正下方设置P+型电场屏蔽区，在集成异质结二极管的同时实现了其所需的电场屏蔽效果；其中异质结二极管阳极区可采用不同掺杂类型和浓度的多晶硅来调节异质结二极管导通压降；本发明不仅在碳化硅槽栅MOSFET上集成了续流二极管，且具有低导通损耗和低开关损耗，同时具有高集成度和降低面积成本的优点。
Description
技术领域
本发明涉及功率半导体领域，具体提供一种具有低导通压降、集成单极异质结二极管的、高度集成的碳化硅槽栅MOSFET。
背景技术
碳化硅MOSFET被认为在电力元器件节能方面具有很大优势，与相同耐压的硅基IGBT相比，碳化硅MOSFET在减小导通损耗和开关损耗方面具有很大优势；然而，碳化硅MOSFET中集成的体续流二极管存在很大的PN结导通压降。为了降低SiC体二极管的导通压降，文献“W.Ni,K.Emori,T.Marui,et al.“SiC Trench MOSFET with an Integrated Low VonUnipolar Heterojunction Diode,”Materials Science Forum,2014,778-780:923-926.”中提出一种SiC槽栅MOSFET，其结构如图1所示，该器件采用SiC与多晶硅构成的异质结二极管作为续流二极管集成在SiC槽栅MOSFET中；由于该异质结二极管导通压降很低，可以显著地减小碳化硅MOSFET反向续流时的导通压降；但是由于该结构的场屏蔽层P+制作在器件表面，使单个MOSFET元胞的面积极大地增加，降低了集成度和沟道密度。
发明内容
本发明的目的在于针对现有的集成了续流二极管的碳化硅槽栅MOSFET元胞面积大、集成度低的缺点，提供一种集成异质结续流二极管碳化硅槽栅MOSFET，该碳化硅槽栅MOSF ET具有高集成度，在集成异质结二极管的同时，将单个元胞的面积进一步缩小，极大地提高了集成度和沟道密度。
为实现上述目的，本发明采用的技术方案为：
一种集成异质结续流二极管碳化硅槽栅MOSFET，其元胞包括：
N+型衬底8，
位于N+型衬底下的漏电极10，
位于N+型衬底上的N-型漂移区1，
分别位于N-型漂移区上左右两侧的P型基区2，P型基区之间设置的栅电极4，所述栅电极与P型基区之间及栅电极与N-型漂移区之间设置的栅氧化层5，
位于P型基区2内的N+源区3，所述N+源区位于P型基区顶部且紧邻栅电极一侧，
深入一侧P型基区2、且与N-型漂移区1直接接触的续流异质结二极管阳极多晶硅区6，
以及覆盖所述P型基区2、N+源区3与续流异质结二极管阳极区6的源电极9；
其特征在于，所述元胞还包括一个P+型电场屏蔽区7，所述P+型电场屏蔽区位于续流异质结二极管阳极区6正下方。
本发明的有益效果在于：
本发明提供一种集成异质结续流二极管碳化硅槽栅MOSFET，其中，集成异质结二极管设置在SiC表面深槽刻蚀后淀积的多晶硅与漂移区接触的两侧，并且P+型电场屏蔽区设置于异质结所在的深槽的正下方，实现对异质结的保护；由于将异质结和P+电场屏蔽区设置在同一深槽处，本发明极大地降低了MOSFET元胞的面积；进而实现提高碳化硅槽栅MOSFET的集成度和沟道密度的目的，进而降低MOSFET和集成异质结二极管的导通损耗。
附图说明
图1为现有集成了单极异质结二极管的SiC槽栅MOSFET结构图。
图2为本发明集成异质结续流二极管碳化硅槽栅MOSFET元胞结构示意图。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
本实施例提供一种集成异质结续流二极管碳化硅槽栅MOSFET，其元胞结构如图2所示，包括：
N+型衬底8(N型重掺杂SiC区)，
位于N+型衬底下的漏电极10(MOSFET漏极)，
位于N+型衬底上的N-型漂移区1(N型轻掺杂SiC区)，
分别位于N-型漂移区上左右两侧的P型基区2(P型掺杂SiC区)，P型基区之间设置的栅电极4(多晶硅区)，所述栅电极与P型基区之间及栅电极与N-型漂移区之间设置的栅氧化层5，
位于P型基区2内的N+源区3(N型重掺杂SiC区)，所述N+源区位于P型基区顶部且紧邻栅电极一侧，
深入右侧P型基区2、且与N-型漂移区1直接接触的续流异质结二极管阳极多晶硅区6，
覆盖所述P型基区2、N+源区3与续流异质结二极管阳极区6的源电极9(MOSFET源极)；
以及一个P+型电场屏蔽区7(P型重掺杂SiC区)，所述P+型电场屏蔽区位于续流异质结二极管阳极区6正下方。
下面结合如图1所示的现有集成异质结续流二极管碳化硅槽栅MOSFET的工作原理对本发明的工作原理做进一步说明：
现有的集成续流异质结二极管的碳化硅槽栅MOSFET元胞结构如图1所示，其工作原理简单介绍如下：当器件处于正向耐压时，该结构需要两个深扩散的电场屏蔽区P+来吸收漂移区电离杂质产生的电力线，从而防止异质结二极管结面产生强电场而导致器件击穿电压急剧下降；当图1所示的器件反向续流时，即异质结二极管正向导通时，其电流可以从多晶硅底部的三个方向流向二极管的阴极(底部的N+区)，如图1中箭头所示；由于电场屏蔽区P+采用深扩散形成，其横向扩散往往占据了很大的芯片面积，不利于高集成度；并且，对于SiC MOSFET，其沟道电阻往往占据总电阻较大比例；而图1所示结构降低了SiC器件的沟道密度，使得比导通电阻增加。
本发明如图2所示，通过将电场屏蔽层7置于异质结二极管阳极区6的正下方，省去了两个深P+的面积，极大地节省了芯片面积，提高了集成度，同时增加了沟道密度以及异质结二极管的有效密度，使得正向和反向的导通电阻均得以降低；当图2所示的器件正向耐压时，P区7虽然没有直接和零电位相连，但是随着漂移区的逐渐耗尽，P区2(零电位)和P区7发生穿通，P区7的电位开始被P区2钳位，漂移区进一步产生的电力线将被P区7吸收，从而防止异质结二极管两侧(如图2箭头所示的两侧)产生高电场，所以P区7可以起到很好的电场屏蔽作用，防止器件击穿电压下降；当器件开始反向续流，即异质结二极管正向导通时，其电流线如图2箭头所示，由异质结二极管两侧流入漂移区；从而，本发明在集成异质结二极管的同时实现了其所需的电场屏蔽效果；其中异质结二极管阳极区6可视情况采用不同掺杂类型和浓度的多晶硅来调节异质结二极管导通压降；本发明不仅在SiC MOSFET上集成了续流二极管，且具有低导通损耗和低开关损耗，同时具有高集成度和降低面积成本的优点。
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。
Claims (1)
1.一种集成续流异质结二极管碳化硅槽栅MOSFET，其元胞包括：
N+型衬底(8)，
位于N+型衬底下的漏电极(10)，
位于N+型衬底上的N-型漂移区(1)，
分别位于N-型漂移区上左右两侧的P型基区(2)，P型基区之间设置的栅电极(4)，所述栅电极与P型基区之间及栅电极与N-型漂移区之间设置的栅氧化层(5)，
位于P型基区内的N+源区(3)，所述N+源区位于P型基区顶部且紧邻栅电极一侧，
深入一侧P型基区(2)、且与N-型漂移区(1)直接接触的续流异质结二极管阳极多晶硅区(6)，
以及覆盖所述P型基区(2)、N+源区(3)与续流异质结二极管阳极区(6)的源电极(9)；
其特征在于，所述元胞还包括一个P+型电场屏蔽区(7)，所述P+型电场屏蔽区位于续流异质结二极管阳极区(6)正下方。
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| CN110739219A (zh) * | 2019-10-30 | 2020-01-31 | 北京工业大学 | 一种内嵌沟道二极管的SiC MOSFET制备方法 |
| CN110828555A (zh) * | 2019-11-18 | 2020-02-21 | 重庆大学 | 一种非对称异质结碳化硅槽型场氧功率mos器件 |
| CN113972261A (zh) * | 2021-10-11 | 2022-01-25 | 松山湖材料实验室 | 碳化硅半导体器件及制备方法 |
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| CN114975602B (zh) * | 2022-07-29 | 2022-11-08 | 深圳芯能半导体技术有限公司 | 一种高可靠性的igbt芯片及其制作方法 |
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