CN109087946B - 一种沟槽栅mos控制晶闸管及其制作方法 - Google Patents
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Abstract
本发明属于功率半导体器件技术领域，一种沟槽栅MOS控制晶闸管(Trench‑MCT)，其元胞结构包括自下而上依次层叠的阳极(1)、P+阳极区(2)、N型缓冲层(3)和漂移区(4)；所述漂移区(4)上层两侧有沟槽栅和P基区(5)，所述P基区(5)上层有N‑区(11)、N‑‑区(10)、N+区(6)和P+区(12)，P+区(12)和N+区(6)共同引出阴极(9)。相比于常规栅控晶闸管，本发明可在栅极零偏压时实现耐压，简化了栅极驱动电路。相比于沟槽栅IGBT，本发明的导通电阻更小，且没有饱和电流的限制，使得本发明的器件在脉冲应用下具有更大的峰值电流Ipeak和更大的电流上升率di/dt，全面提升了器件的脉冲特性，降低晶格温度。
Description
技术领域
本发明属于功率半导体器件技术领域，涉及一种沟槽栅MOS控制晶闸管及其制备方法。
背景技术
脉冲功率技术是20世纪60年代初期由于国防科研需要而发展起来的一门新兴科学技术。简单来说，脉冲功率技术是把慢储存起来的能量进行快速压缩，以脉冲的形式释放给负载的电物理技术。随着核物理、电子束加速器物理、激光和等离子体物理研究的发展，脉冲功率技术得到迅速发展，成为当前国际上非常活跃的前沿科技之一，在军事领域和民用领域都有广泛的应用前景，军事领域应用于核聚变技术、国防军事防御的引信系统等；民用领域应用于食品加工、医疗、废水处理，废气处理，臭氧制备、发电机点火、离子注入、材料加工等。(于明伟.LCC谐振式脉冲电流源设计[D].哈尔滨工业大学,2015.)
随着脉冲应用领域的扩展，脉冲功率开关作为脉冲功率电源的关键器件有着举足轻重的地位。目前，常用的半导体脉冲功率开关包括功率MOSFET、晶闸管(SCR)、绝缘栅双极晶体管(IGBT)、MOS控制晶闸管(MCT)以及新发展起来的阴极短路栅控晶闸管(CS-MCT)。上述这些半导体脉冲功率开关各有优缺点。其中双极型功率器件内部存在电导调制效应，使其具有相对于常规单极型器件更小的导通功耗，但不同类型的双极型器件的电导调制程度不同。其中，晶闸管内部由于存在NPN管和PNP管的正反馈作用，使其电导调制程度更高，导通功耗更小。但是由于在开启过程中存在电流集中效应，造成晶闸管的di/dt能力较差。此外，晶闸管属于流控型器件，与压控型器件相比，其驱动电路更为复杂。IGBT主要应用在高频中等脉冲功率电源，IGBT属于压控型器件，驱动相对简单，但是IGBT的电导调制程度受到漂移区和P型基区反偏PN结的限制，导致器件的导通功耗较大；此外，IGBT的导通受栅压控制，最大电流也受饱和电流的限制。栅控晶闸管(MOS-Controlled Thyristor,MCT)具有类似晶闸管的低阻特性，同时具有较高的di/dt能力和压控特性，但器件在开关过程中需要异号的栅极控制信号，导致驱动电路更为复杂(Temple V A K.MOS controlled thyristors(MCT's)[C].Electron Devices Meeting,1984International.IEEE,1984:282-285.)。而本发明的沟槽栅MOS控制晶闸管(Trench-MCT)解决了上述矛盾，属于压控型器件，它的内部存在晶闸管结构，使得其具有较小的导通电阻和较大的di/dt能力，由于低掺杂N--结构的存在，使得在栅极零偏时实现器件的阻断，大大简化了栅极驱动电路；其导通不受饱和电流限制，能更大程度的提升电流等级，大幅度降低晶格温度。
发明内容
本发明提出一种新的沟槽栅MOS控制晶闸管(Trench-MCT)结构。
本发明技术方案如下：
一种沟槽栅MOS控制晶闸管(Trench-MCT)，其元胞结构包括自下而上依次层叠设置的阳极1、P+阳极区2、N型缓冲层3和顶部半导体层；顶部半导体层包括漂移区4、分别位于漂移区4上层两侧的沟槽栅和P基区5；所述沟槽栅包括栅氧化层7和位于栅氧化层7中的栅极8；所述P基区5上层具有并列设置的N-区11和N--区10，且N--区10与栅氧化层7接触，在N--区10的正上方具有P+区12，在N-区11的正上方具有N+区6，P+区12和N+区6共同引出阴极9。
本发明的有益效果为，相比于常规栅控晶闸管，本发明可在栅极零偏压时实现耐压，简化了栅极驱动电路。相比于沟槽栅IGBT，本发明的导通电阻更小，且没有饱和电流的限制，使得本发明的器件在脉冲应用下具有更大的峰值电流Ipeak和更大的电流上升率di/dt，全面提升了器件的脉冲特性，降低晶格温度。
附图说明
图1为已有的Trench-IGBT的二维结构示意图；
图2为本发明所提出的Trench-MCT的二维结构示意图；
图3是本发明的制作工艺流程中在N-漂移区上刻蚀沟槽后的结构示意图；
图4是本发明的制作工艺流程中在沟槽中形成栅氧化层后的结构示意图；
图5是本发明的制作工艺流程中在沟槽中的栅氧化层上淀积多晶硅栅极的结构示意图；
图6是本发明的制作工艺流程中通过离子注入P型杂质推结形成P基区的结构示意图；
图7是本发明的制作工艺流程中通过离子注入N型杂质推结形成N-区的结构示意图；
图8是本发明的制作工艺流程中通过离子注入P型杂质推结，并经过杂质补偿形成N--区的结构示意图；
图9是本发明的制作工艺流程中通过离子注入P型杂质推结形成P+区的结构示意图；
图10是本发明的制作工艺流程中通过离子注入N型杂质推结形成N+区的结构示意图；
图11是本发明的制作工艺流程中正面金属化后的结构示意图；
图12是本发明的制作工艺流程中背面减薄后，进行N型杂质注入形成N+缓冲层的结构示意图；
图13是本发明的制作工艺流程中背面进行P型杂质注入形成P+阳极区的结构示意图；
图14为本发明的制作工艺流程中背面金属化后的结构示意图；
图15为本发明所提出的Trench-MCT中C1切线和C2切线的位置示意图；
图16为本发明所提出的Trench-MCT在C1切线和C2切线处的掺杂浓度分布图；
图17为传统的Trench-IGBT和本发明提出的Trench-MCT在栅压零偏时的击穿电压对比图；
图18为传统的Trench-IGBT和本发明提出的Trench-MCT的导通I-V曲线对比图；
图19为脉冲放电时的电路示意图；
图20为传统的Trench-IGBT和本发明提出的Trench-MCT在脉冲放电时阳极电流的仿真对比图；
图21为传统的Trench-IGBT和本发明提出的Trench-MCT在脉冲放电时最大晶格温度的仿真对比图。
具体实施方式
下面结合附图对本发明进行详细的描述
如图1所示，为已有的Trench-IGBT的二维结构示意图；如图2所示，为本发明所提出的Trench-MCT的二维结构示意图；相比与Trench-IGBT，本发明的Trench-MCT在P基区5上多有N-区11、N--区10、和P+区12。该结构的工作原理为：
在栅极接零偏压时，随着阳极电压的增加，P基区和N--区耗尽，使得空穴能够从上面的P+区抽出，电子从下面的P+阳极区抽出，器件在栅极零偏时得以耐压；
在阳极施加正向偏压，空穴由阳极注入N型缓冲层，再注入漂移区，随着栅极电压增加，当栅极电压达到阈值电压时，栅极右侧的P基区反型，电子由阴极流入漂移区中，作为下方P+阳极区/N+缓冲层和N型漂移区/P基区所形成的PNP晶体管的基极电流，使得PNP晶体管导通，空穴由P+阳极区注入漂移区，载被P基区收集；此处被P基区收集的空穴作为上方N+区和N-区/P基区/N型漂移区所形成的NPN晶体管的基极电流，使得NPN晶体管导通，从而在PNP晶体管和NPN晶体管之间触发正反馈机制，内部晶闸管导通，电导调制效应增强，器件等效电阻减小。
以图2所示的Trench-MCT的元胞结构为例，其典型的制作步骤如下：
第一步：选取合适电阻率的硅片做衬底，即N型漂移区4，在N型漂移区4上表面一侧刻蚀沟槽，如图3所示；
第二步：在沟槽中通过热氧化生长形成栅氧化层7，如图4所示；
第三步：在沟槽中的栅氧化层7上填充多晶硅，形成栅电极8，如图5所示；
第四步：在器件上表面生长预氧氧化层，注入P型杂质，利用多晶硅栅极的自对准工艺，在N型漂移区4上层形成P基区5，如图6所示；
第五步：在N型漂移区4上层注入N型杂质，利用多晶硅栅极的自对准工艺，形成N-区11；N-区11位于P基区5中，如图7所示；
第六步：在N型漂移区4上层注入P型杂质，利用多晶硅栅极的自对准工艺和P区的掩模版，注入的P型杂质浓度低于上一步骤中注入的N型杂质浓度，通过杂质补偿作用之后，形成N--区10，N--区10与N-区11并列设置且N--区10与栅氧化层7接触，如图8所示；
第七步：在上一步的基础上，再注入高浓度的P型杂质，形成浅结高掺杂的P+区12，P+区12位于N--区10，如图9所示；
第八步：在N型漂移区4上层注入N型杂质，利用多晶硅栅极的自对准工艺和N区的掩模版，形成浅结高掺杂的N+区6，如图10所示；
第九步：刻蚀掉器件上表面的预氧氧化层，在器件上表面淀积金属，形成阴极9，阴极9的底部与N+区6和P+区12接触，如图11所示；
第十步：在器件上表面淀积钝化层；对N型半导体漂移区4的下表面进行减薄、抛光处理，预氧氧化层，注入N型杂质并推结，形成N+缓冲层3，如图12所示；
第十一步：在上一步的基础上，再注入P型杂质并激活，在N+缓冲层3下层形成浅结高掺杂的P+阳极区2，如图13所示；
第十二步：背金，去掉预氧氧化层，在下表面淀积金属，形成阳极1，如图14所示。
实施例：
如图15和16所示，以元胞宽度5μm的器件为例，C1和C2的位置和浓度分布如图所示。
图17为传统的Trench-IGBT和本发明提出的Trench-MCT在栅极零偏时的击穿电压对比图，可以看出，本发明所提出的Trench-MCT的耐压水平与传统的Trench-IGBT的耐压水平相当。
图18为传统的Trench-IGBT和本发明提出的Trench-MCT的导通I-V曲线对比图，可以看出，本发明所提出的Trench-MCT导通电阻更小，且没有饱和电流的限制。
本发明所提出的Trench-MCT器件的可以应用在脉冲领域，图19为脉冲放电时的电路示意图。
图20为传统的Trench-IGBT和本发明提出的Trench-MCT在脉冲放电时阳极电流的仿真对比图；可以看出，本发明所提出的Trench-MCT在同等的外部放电电路中，相比于Trench-IGBT，峰值电流Ipeak提高了21.43％，电流上升率di/dt也有明显的大幅度提高。
图21为传统的Trench-IGBT和本发明提出的Trench-MCT在脉冲放电时最大晶格温度的仿真对比图，可以看出，本发明所提出的Trench-MCT电流分布更加均匀，晶格温度下降了90％。
Claims (1)
1.一种沟槽栅MOS控制晶闸管的制作方法，其特征在于，包括以下步骤：
第一步：选取合适电阻率的硅片做衬底，即N型漂移区(4)，在N型漂移区(4)上表面一侧刻蚀沟槽；
第二步：在沟槽中通过热氧化生长形成栅氧化层(7)；
第三步：在沟槽中的栅氧化层(7)上填充多晶硅，形成栅电极(8)；
第四步：在器件上表面生长预氧氧化层，注入P型杂质，利用多晶硅栅极的自对准工艺，在N型漂移区(4)上层形成P基区(5)；
第五步：在N型漂移区(4)上层注入N型杂质，利用多晶硅栅极的自对准工艺，在P基区(5)上层形成N-区(11)；
第六步：在N型漂移区(4)上层注入P型杂质，利用多晶硅栅极的自对准工艺和P区的掩模版，注入的P型杂质浓度低于上一步骤中注入的N型杂质浓度，通过杂质补偿作用之后，形成N--区(10)，N--区(10)与N-区(11)并列设置且N--区(10)与栅氧化层(7)接触；
第七步：采用离子注入工艺，注入高浓度的P型杂质，在N--区(10)正上方形成浅结高掺杂的P+区(12)；
第八步：在N型漂移区(4)上层注入N型杂质，利用多晶硅栅极的自对准工艺和N区的掩模版，在N-区(11)正上方形成浅结高掺杂的N+区(6)；
第九步：刻蚀掉器件上表面的预氧氧化层，在器件上表面淀积金属，形成阴极(9)，阴极(9)的底部与N+区(6)和P+区(12)接触；
第十步：在器件上表面淀积钝化层；对N型半导体漂移区(4)的下表面进行减薄、抛光处理，预氧氧化层，注入N型杂质并推结，在N型半导体漂移区(4)下次形成N+缓冲层(3)；
第十一步：在上一步的基础上，再注入P型杂质并激活，在N+缓冲层(3)下层形成浅结高掺杂的P+阳极区(2)；
第十二步：背金，去掉预氧氧化层，在下表面淀积金属，形成阳极(1)。
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| US5324966A (en) * | 1992-04-07 | 1994-06-28 | Toyo Denki Seizo Kabushiki Kaisha | MOS-controlled thyristor |
| CN1144975A (zh) * | 1996-04-23 | 1997-03-12 | 西安电子科技大学 | 栅控晶闸管 |
| CN101478002A (zh) * | 2008-11-27 | 2009-07-08 | 电子科技大学 | 一种积累层控制的晶闸管 |
| CN103956381A (zh) * | 2014-05-07 | 2014-07-30 | 电子科技大学 | 一种mos栅控晶闸管 |
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| US5324966A (en) * | 1992-04-07 | 1994-06-28 | Toyo Denki Seizo Kabushiki Kaisha | MOS-controlled thyristor |
| CN1144975A (zh) * | 1996-04-23 | 1997-03-12 | 西安电子科技大学 | 栅控晶闸管 |
| CN101478002A (zh) * | 2008-11-27 | 2009-07-08 | 电子科技大学 | 一种积累层控制的晶闸管 |
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