WO2024001422A1 - 集成高速续流二极管的沟槽碳化硅mosfet及制备方法 - Google Patents

集成高速续流二极管的沟槽碳化硅mosfet及制备方法 Download PDF

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WO2024001422A1
WO2024001422A1 PCT/CN2023/087960 CN2023087960W WO2024001422A1 WO 2024001422 A1 WO2024001422 A1 WO 2024001422A1 CN 2023087960 W CN2023087960 W CN 2023087960W WO 2024001422 A1 WO2024001422 A1 WO 2024001422A1
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type doped
silicon carbide
layer
type
oxide layer
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PCT/CN2023/087960
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English (en)
French (fr)
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顾航
高巍
戴茂州
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成都蓉矽半导体有限公司
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Priority to EP23829612.3A priority Critical patent/EP4354513A1/en
Publication of WO2024001422A1 publication Critical patent/WO2024001422A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the invention belongs to the technical field of power semiconductor devices, and specifically relates to a trench silicon carbide MOSFET integrating a high-speed freewheeling diode and a preparation method thereof.
  • the wide bandgap semiconductor material SiC is an ideal material for preparing high-voltage power electronic devices. Compared with Si materials, SiC materials have high breakdown electric field strength (4 ⁇ 10 6 V/cm) and high carrier saturation drift velocity (2 ⁇ 10 7 cm/s), high thermal conductivity, and good thermal stability, so it is particularly suitable for use in high-power, high-voltage, high-temperature and radiation-resistant electronic devices.
  • SiC VDMOS is a commonly used device among SiC power devices. Compared with bipolar devices, SiC VDMOS has no charge storage effect, so it has better frequency characteristics and lower switching losses. At the same time, the wide band gap of SiC material allows the operating temperature of SiC VDMOS to be as high as 300°C.
  • planar SiC VDMOS there are two problems with planar SiC VDMOS.
  • One is that the density of the JFET area is relatively large, which introduces a large Miller capacitance and increases the dynamic loss of the device.
  • the other is that the parasitic SiC body diode conduction voltage drop is too high. , and it is a bipolar device with a large reverse recovery current.
  • the bipolar degradation caused by silicon carbide BPD defects causes the conduction voltage drop of the body diode to continue to increase as the use time increases. Therefore, The body diode of SiC VDMOS cannot be used directly as a freewheeling diode.
  • the present invention proposes the trench silicon carbide MOSFET integrated with a high-speed freewheeling diode.
  • the MOSFET of the present invention has a trench structure.
  • the polysilicon bottom gate oxide layer of the trench MOSFET is thicker.
  • a P-type doped buried layer is added to the bottom of the trench, which can significantly reduce the Miller capacitance compared to planar VDMOS. , reduce its switching losses.
  • the gate-controlled diode is connected in parallel with the original body diode of the device, which greatly reduces the conduction voltage drop of the body diode, thereby reducing the loss in the reverse freewheeling operating mode.
  • the gate-controlled diode is a unipolar device and does not have the minority carrier storage effect, which can completely eliminate the reverse recovery current of the body diode, thereby reducing dynamic losses.
  • the technical problem to be solved by the present invention is to solve the problems existing in the existing technology and to meet the high-frequency switching application requirements of silicon carbide power semiconductors. It provides a trench silicon carbide MOSFET with integrated high-speed freewheeling diode and a preparation method thereof.
  • a trench silicon carbide MOSFET integrating a high-speed freewheeling diode including a backside ohmic contact alloy 1, an N-type doped silicon carbide substrate 2, an N-type doped silicon carbide epitaxial layer 3, and a first P-type doped buried layer 41 , the second P-type doped buried layer 42, the third P-type doped buried layer 43, the first gate oxide layer 51, the second gate oxide layer 52, the first polysilicon 61, the second polysilicon 62, the A P-type doping well region 71, a second P-type doping well region 72, a third P-type doping well region 73, a first N-type doping source region 81, a second N-type doping source region 82, P Type doped source region 9, interlayer dielectric 10, front ohmic contact alloy 11;
  • the N-type doped silicon carbide substrate 2 is located above the backside ohmic contact alloy 1; the N-type doped silicon carbide epitaxial layer 3 is located on the N-type doped silicon carbide epitaxial layer 3.
  • the second P-type doped buried layer 42 is located on the upper right side of the N-type doped silicon carbide epitaxial layer 3; the third P-type doped buried layer 43 is located on the N-type doped silicon carbide epitaxial layer 3;
  • the first gate oxide layer 51 is located above the second P-type doped buried layer 42;
  • the second gate oxide layer 52 is located on the third P-type Above the doped buried layer 43;
  • the first polysilicon 61 is located on the upper right side of the first gate oxide layer 51;
  • the second polysilicon 62 is located on the upper left side of the second gate oxide layer 52;
  • the first N-type doped source region 81 is located on the upper left side of the first gate oxide layer 51;
  • the P-type doped source region 9 is located on the left side of the first N-type doped source region 81;
  • the second N-type doped source region 82 is located on
  • the N-type doped silicon carbide substrate 2 is located above the backside ohmic contact alloy 1; the N-type doped silicon carbide epitaxial layer 3 is located on the N-type doped silicon carbide epitaxial layer 3.
  • the first P-type doped buried layer 41 is located on the upper right side of the N-type doped silicon carbide epitaxial layer 3; the second P-type doped buried layer 42 is located on the N-type doped silicon carbide epitaxial layer 3; Type doped silicon carbide epitaxial layer 3 in the upper left corner; the first gate oxide layer 51 is located in the first P-type doped buried layer 41, N-type doped silicon carbide epitaxial layer 3, and the second P-type doped buried layer 3. above layer 42; the first polysilicon 61 is located above the first gate oxide layer 51; the interlayer dielectric 10 is located above the first polysilicon 61; the first front-side ohmic contact alloy 11 located above the interlayer medium 10 .
  • the doping concentration range of the N-type doped silicon carbide epitaxial layer 3 is 1E15cm -3 ⁇ 1E17cm -3 ;
  • the first P-type doped well region 71 is formed by lateral scattering during Al ion implantation, and its concentration gradually decreases along the negative direction of the x-axis, and the first P-type doped well region 71 is close to the first P-type doped well region 71 .
  • the concentration range of a gate oxide layer 51 is 1E14cm -3 ⁇ 1E16cm -3 .
  • a method for preparing a trench silicon carbide MOSFET with an integrated high-speed freewheeling diode which is characterized by comprising the following steps:
  • Step 1 Deposit an oxide layer on the N-type silicon carbide epitaxial wafer, form a P-well ion implantation mask layer 101 for ion implantation after photolithography, and then perform Al ion implantation at a temperature of 300K ⁇ 1000K to form a second P-type doped layer.
  • the second P-type doped well region 72 will be laterally scattered due to Al ion implantation in silicon carbide. Therefore, a P-type doped scattering region with a laterally varying concentration will be formed on the left and right sides of the second P-type doped well region 72, respectively.
  • the mask layer is removed after the injection is completed, and surface cleaning is completed;
  • Step 2 Deposit the oxide layer, and form an ion implanted N-type source region after photolithography.
  • the ion implantation mask layer 102 is then performed at a temperature of 300K to 1000K.
  • P ion implantation is performed to form the first N-type doped source region 81. and a second N-type doped source region 82 . After the injection is completed, remove the mask layer and complete surface cleaning;
  • Step 3 Deposit the oxide layer, and form an ion implanted P-type source region after photolithography.
  • the ion implantation mask layer 103 is then implanted with Al ions at a temperature of 300K ⁇ 1000K to form a P-type doped source region 9. After completion, remove the mask layer and complete surface cleaning;
  • Step 4 Deposit the oxide layer, form the trench etching barrier layer 104 after photolithography, and then perform reactive ion etching on the N-type doped silicon carbide epitaxial layer 3 to form trenches;
  • Step 5 Perform Al ion implantation at a high temperature of 300K ⁇ 1000K to form the second P-type doped buried layer 42 and the third P-type doped buried layer 43 at the bottom of the trench. After the implantation is completed, remove the trench etching barrier layer 104;
  • Step 6 Cover the carbon cap, anneal at a high temperature above 1600°C, activate the injected impurities, and thermally oxidize to form the first gate oxide layer 51 and the second gate oxide layer 52, then deposit polysilicon, and etch to form the third gate oxide layer.
  • Step 7 Deposit the oxide layer and form the interlayer dielectric 10 by photolithography
  • Step 8 Deposit Ni alloy, anneal to form metal silicide, then deposit Al on the front to form the source metal, sputter the back of the device to form Ni alloy, and anneal to form the back ohmic contact alloy 1.
  • the invention adopts a structure of trench plus P-type buried layer, which fully reduces the Miller capacitance of the device, thereby reducing the switching loss of the device.
  • the addition of the P-type buried layer weakens the electric field concentration at the bottom and corners of the trench, improving the long-term reliability of the device;
  • the present invention monolithically integrates a gate-controlled diode, which has a trench structure, and its trench and the trench of the MOSFET are formed at the same time without requiring additional process steps.
  • This gate-controlled diode is a rectifier based on MOSFET diode connection. Compared with the traditional MOSFET body diode, this rectifier has the advantages of reduced conduction voltage and unipolar conduction (no reverse recovery current, no double-click degradation). This rectifier can be used as a freewheeling diode for MOSFET, greatly reducing dynamic losses.
  • the addition of gate-controlled diodes also weakens the electric field strength at the bottom and corners of the MOSFET trench, thereby improving the long-term reliability of the device;
  • the present invention uses the scattering effect during Al ion implantation to form the channels of the MOSFET and the gate-controlled diode. This method can reduce the doping concentration of the device's channel region while ensuring that the total amount of charge in the P-type well region is sufficient.
  • MOSFET we can control the relative position of the trench and the P-type doped well region to control the doping concentration of the channel region, thereby accurately controlling its threshold voltage.
  • gated diodes we can control the relative position of the trench and the P-type doped well region to control the doping concentration of the channel region, thereby adjusting the conduction voltage drop of the gated diode.
  • SiC MOSFETs In applications such as half-bridge or full-bridge, SiC MOSFETs usually require an anti-parallel SiC Schottky diode for freewheeling.
  • the present invention can avoid additional parallel connection of freewheeling diodes.
  • Figure 1 is a schematic structural diagram of a trench silicon carbide MOSFET integrated with a high-speed freewheeling diode of the present invention.
  • Figure 2 is a schematic diagram of ion implantation in the P-type doped well region in step 1 of Embodiment 2 of the present invention.
  • Figure 3 is a schematic diagram of ion implantation into the N-type doped source region in Step 2 of Embodiment 2 of the present invention.
  • Figure 4 is a schematic diagram of ion implantation into the P-type doped source region in Step 3 of Embodiment 2 of the present invention.
  • Figure 5 is a schematic diagram of trench etching in step 4 of Embodiment 2 of the present invention.
  • Figure 6 is a schematic diagram of ion implantation of P-type doped buried layer in step 5 of Embodiment 2 of the present invention.
  • Figure 7 is a schematic diagram of gate oxide layer formation and polysilicon filling etching in Step 6 of Embodiment 2 of the present invention.
  • Figure 8 is a schematic diagram of the interlayer medium formed by photolithography in Step 7 of Embodiment 2 of the present invention.
  • Figure 10 is a schematic equivalent circuit diagram of the trench silicon carbide MOSFET with integrated high-speed freewheeling diode in forward conduction according to Embodiment 1 of the present invention.
  • Figure 11 is a schematic equivalent circuit diagram of the trench silicon carbide MOSFET with integrated high-speed freewheeling diode in reverse freewheeling according to Embodiment 1 of the present invention.
  • 1 is the backside ohmic contact alloy
  • 2 is the N-type doped silicon carbide substrate
  • 3 is the N-type doped silicon carbide epitaxial layer
  • 41 is the first P-type doped buried layer
  • 42 is the second P-type doped buried layer
  • 43 is the third P-type doped buried layer
  • 51 is the first gate oxide layer
  • 52 is the second gate oxide layer
  • 61 is the first polysilicon
  • 62 is the second polysilicon
  • 71 is the first P-type Doping well region
  • 72 is the second P-type doping well region
  • 73 is the third P-type doping well region
  • 81 is the first N-type doping source region
  • 82 is the second N-type doping source region
  • 9 is the P-type doping source region
  • 10 is the interlayer dielectric
  • 11 is the front ohmic contact alloy
  • 101 is the P-well ion implantation mask layer
  • 102 is the N-type source region ion
  • this embodiment provides a trench silicon carbide MOSFET with an integrated high-speed freewheeling diode, including a backside ohmic contact alloy 1, an N-type doped silicon carbide substrate 2, and an N-type doped silicon carbide epitaxial layer 3 , the first P-type doped buried layer 41, the second P-type doped buried layer 42, the third P-type doped buried layer 43, the first gate oxide layer 51, the second gate oxide layer 52, the first polysilicon 61.
  • the N-type doped silicon carbide substrate 2 is located above the backside ohmic contact alloy 1; the N-type doped silicon carbide epitaxial layer 3 is located on the N-type doped silicon carbide epitaxial layer 3.
  • the second P-type doped buried layer 42 is located on the upper right side of the N-type doped silicon carbide epitaxial layer 3; the third P-type doped buried layer 43 is located on the N-type doped silicon carbide epitaxial layer 3;
  • the first gate oxide layer 51 is located above the second P-type doped buried layer 42;
  • the second gate oxide layer 52 is located on the third P-type Above the doped buried layer 43;
  • the first polysilicon 61 is located on the upper right side of the first gate oxide layer 51;
  • the second polysilicon 62 is located on the upper left side of the second gate oxide layer 52;
  • the first N-type doped source region 81 is located on the upper left side of the first gate oxide layer 51;
  • the P-type doped source region 9 is located on the left side of the first N-type doped source region 81;
  • the second N-type doped source region 82 is located on
  • the N-type doped silicon carbide substrate 2 is located above the backside ohmic contact alloy 1; the N-type doped silicon carbide epitaxial layer 3 is located on the N-type doped silicon carbide epitaxial layer 3.
  • the first P-type doped buried layer 41 is located on the upper right side of the N-type doped silicon carbide epitaxial layer 3; the second P-type doped buried layer 42 is located on the N-type doped silicon carbide epitaxial layer 3; Type doped silicon carbide epitaxial layer 3 in the upper left corner; the first gate oxide layer 51 is located in the first P-type doped buried layer 41, N-type doped silicon carbide epitaxial layer 3, and the second P-type doped buried layer 3. above layer 42; the first polysilicon 61 is located above the first gate oxide layer 51; the interlayer dielectric 10 is located above the first polysilicon 61; the first front-side ohmic contact alloy 11 located above the interlayer medium 10 .
  • the doping concentration range of the N-type doped silicon carbide epitaxial layer 3 is 1E15cm -3 ⁇ 1E17cm -3 ;
  • the first P-type doped well region 71 is formed by lateral scattering during Al ion implantation. Its concentration gradually decreases along the negative direction of the x-axis, and the first P-type doped well region 71 is close to the first gate oxide layer.
  • the concentration range at 51 is 1E14cm -3 ⁇ 1E16cm -3 .
  • the third P-type doped well region 73 is formed by lateral scattering during Al ion implantation. Its concentration gradually decreases along the positive direction of the x-axis, and the third P-type doped well region 73 is close to the second gate oxide layer.
  • the concentration range at 52 is 0 ⁇ 1E15cm -3 .
  • Figure 10 is a schematic diagram of the equivalent circuit of the trench silicon carbide MOSFET with integrated high-speed freewheeling diode in forward conduction according to Embodiment 1 of the present invention.
  • the positive potential difference from the source to the drain causes the diode area to conduct, forming a current I sd from the source to the drain, as shown in Figure 11, which illustrates the implementation of the present invention.
  • Example 1 is a schematic diagram of the equivalent circuit of a trench silicon carbide MOSFET with integrated high-speed freewheeling diode during reverse freewheeling.
  • this embodiment provides a method for preparing a trench silicon carbide MOSFET with an integrated high-speed freewheeling diode, which includes the following steps:
  • Step 1 Deposit an oxide layer on the N-type silicon carbide epitaxial wafer, form a P-well ion implantation mask layer 101 for ion implantation after photolithography, and then perform Al ion implantation at a temperature of 300K ⁇ 1000K to form a second P-type doped layer.
  • the second P-type doped well region 72 will be laterally scattered due to Al ion implantation in silicon carbide. Therefore, a P-type doped scattering region with a laterally varying concentration will be formed on the left and right sides of the second P-type doped well region 72, respectively.
  • Step 2 Deposit the oxide layer, and form an ion implanted N-type source region after photolithography.
  • the ion implantation mask layer 102 is then performed at a temperature of 300K to 1000K.
  • P ion implantation is performed to form the first N-type doped source region 81. and the second N-type doped source region 82 to obtain the structure as shown in Figure 3 .
  • Step 3 Deposit the oxide layer, and form an ion implanted P-type source region after photolithography.
  • the ion implantation mask layer 103 is then implanted with Al ions at a temperature of 300K ⁇ 1000K to form a P-type doped source region 9.
  • Obtain The structure is shown in Figure 4. After the injection is completed, remove the mask layer and complete surface cleaning;
  • Step 4 Deposit the oxide layer, form a trench etching barrier layer 104 after photolithography, and then perform reactive ion etching on the N-type doped silicon carbide epitaxial layer 3 to form a trench; the structure as shown in Figure 5 is obtained;
  • Step 5 Perform Al ion implantation at a high temperature of 300K ⁇ 1000K to form the second P-type doped buried layer 42 and the third P-type doped buried layer 43 at the bottom of the trench, obtaining the structure as shown in Figure 6. After the implantation is completed, the trench etching barrier layer 104 is removed;
  • Step 6 Cover the carbon cap, anneal at a high temperature above 1600°C, activate the injected impurities, and thermally oxidize to form the first gate oxide layer 51 and the second gate oxide layer 52, then deposit polysilicon, and etch to form the third gate oxide layer.
  • Step 7 Deposit the oxide layer, and form the interlayer dielectric 10 by photolithography; obtain the structure as shown in Figure 8;
  • Step 8 Deposit Ni alloy, anneal to form metal silicide, then deposit Al on the front to form the source metal, sputter the back of the device to form Ni alloy, and anneal to form the back ohmic contact alloy 1.
  • the structure shown in Figure 9 is obtained.

Abstract

本发明涉及一种集成高速续流二极管的沟槽碳化硅MOSFET及其制备方法，属于功率半导体器件技术领域，本发明的MOSFET为沟槽结构，为了解决沟槽底部拐角处的电场集中问题，我们在MOSFET旁边加入了沟槽型的栅控二极管，并且沟槽底部均加入了P型埋层，借此削弱彼此的电场强度。此外，栅控二极管与器件原有的体二极管并联，大幅度降低了体二极管的导通压降，从而降低了反向续流工作模式下的损耗。另外，栅控二极管为单极型器件不存在少子存储效应，可以完全消除体二极管的反向恢复电流，从而降低动态损耗。

Description

集成高速续流二极管的沟槽碳化硅MOSFET及制备方法 技术领域
本发明属于功率半导体器件技术领域，具体涉及集成高速续流二极管的沟槽碳化硅MOSFET及其制备方法。
 背景技术
宽禁带半导体材料SiC是制备高压电力电子器件的理想材料，相对于Si材料，SiC材料具有击穿电场强度高（4×10 6V/cm）、载流子饱和漂移速度高(2×10 7cm/s)、热导率高、热稳定性好等优点，因此特别适合用于大功率、高压、高温和抗辐射的电子器件中。
SiC VDMOS是SiC功率器件中较为常用的一种器件，相对于双极型的器件，由于SiC VDMOS没有电荷存储效应，所以其拥有更好的频率特性以及更低的开关损耗。同时SiC材料的宽禁带使得SiC VDMOS的工作温度可以高达300℃。
但是平面型SiC VDMOS存在两个问题，其一是JFET区的密度较大，引入了较大的密勒电容，增加了器件的动态损耗；其二是寄生的SiC体二极管导通压降太高，并且其为双极型器件，存在较大的反向恢复电流，此外碳化硅BPD缺陷造成的双极退化现象使得该体二极管的导通压降随着使用时间的增长持续升高，因此，SiC VDMOS的体二极管无法直接作为续流二极管使用。
为了解决这两个问题，本发明提出了所述的集成高速续流二极管的沟槽碳化硅MOSFET。本发明的MOSFET为沟槽结构，沟槽MOSFET的多晶硅底部栅氧化层较厚，并且在本设计中为沟槽底部加入P型掺杂埋层，相对于平面VDMOS可以大幅度降低起密勒电容，降低其开关损耗。为了解决沟槽底部拐角处的电场集中问题，我们在MOSFET旁边加入了沟槽型的栅控二极管，并且沟槽底部均加入了P型埋层，借此削弱彼此的电场强度。此外，栅控二极管与器件原有的体二极管并联，大幅度降低了体二极管的导通压降，从而降低了反向续流工作模式下的损耗。另外，栅控二极管为单极型器件不存在少子存储效应，可以完全消除体二极管的反向恢复电流，从而降低动态损耗。
 技术解决方案
本发明所要解决的技术问题是针对现有技术存在的问题，针对碳化硅功率半导体的高频开关应用需求，提供了集成高速续流二极管的沟槽碳化硅MOSFET及其制备方法。
为解决上述技术问题，本发明技术方案如下：
一种集成高速续流二极管的沟槽碳化硅MOSFET，包括背面欧姆接触合金1，N型掺杂碳化硅衬底2，N型掺杂碳化硅外延层3，第一P型掺杂埋层41，第二P型掺杂埋层42，第三P型掺杂埋层43，第一栅氧化层51，第二栅氧化层52，第一多晶硅61，第二多晶硅62，第一P型掺杂井区71，第二P型掺杂井区72，第三P型掺杂井区73，第一N型掺杂源区81，第二N型掺杂源区82，P型掺杂源区9，层间介质10，正面欧姆接触合金11；
在x轴和y轴构成的平面上，所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方；所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方；所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3的右上方；所述第三P型掺杂埋层43位于所述N型掺杂碳化硅外延层3的左上方；所述第一栅氧化层51位于所述第二P型掺杂埋层42的上方；所述第二栅氧化层52位于所述第三P型掺杂埋层43的上方；所述第一多晶硅61位于所述第一栅氧化层51的右上方；所述第二多晶硅62位于所述第二栅氧化层52的左上方；所述第一N型掺杂源区81位于所述第一栅氧化层51的左上方；所述P型掺杂源区9位于所述第一N型掺杂源区81的左侧；所述第二N型掺杂源区82位于所述P型掺杂源区9的左侧，并且与第二栅氧化层52的右侧相接；所述第一P型掺杂井区71位于所述第一N型掺杂源区81下方，且位于所述第一栅氧化层51的左侧；所述第二P型掺杂井区72位于所述第一N型掺杂源区81、P型掺杂源区9和第二N型掺杂源区82的下方，并且位于所述第一P型掺杂井区71左侧；所述第三P型掺杂井区73位于所述第二N型掺杂源区82下方，并且位于所述第二P型掺杂井区72左侧；所述层间介质10位于所述第一N型掺杂源区81、第一栅氧化层51、第一多晶硅61的上方；所述正面欧姆接触合金11位于所述层间介质10、第一N型掺杂源区81、P型掺杂源区9、第二N型掺杂源区82、第二栅氧化层52、第二多晶硅62的上方；
在y轴和z轴构成的平面上，所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方；所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方；所述第一P型掺杂埋层41位于所述N型掺杂碳化硅外延层3内部右上方；所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3内部左上方；所述第一栅氧化层51位于所述第一P型掺杂埋层41、N型掺杂碳化硅外延层3、第二P型掺杂埋层42上方；所述第一多晶硅61位于所述第一栅氧化层51的上方；所述层间介质10位于所述第一多晶硅61的上方；所述第正面欧姆接触合金11位于所述层间介质10的上方。
作为优选方式，所述N型掺杂碳化硅外延层3的掺杂浓度范围为1E15cm -3~ 1E17cm -3；
作为优选方式，所述第一P型掺杂井区71为Al离子注入时横向散射形成的，其浓度延x轴的负方向逐渐降低，且第一P型掺杂井区71靠近所述第一栅氧化层51处的浓度范围为1E14cm -3~ 1E16cm -3。
作为优选方式，所述第三P型掺杂井区73为Al离子注入时横向散射形成的，其浓度延x轴的正方向逐渐降低，且第三P型掺杂井区73靠近所述第二栅氧化层52处的浓度范围为0 ~ 1E15cm -3。
一种所述的集成高速续流二极管的沟槽碳化硅MOSFET的制备方法，其特征在于包括以下步骤：
步骤1：N型碳化硅外延片上淀积氧化层，光刻后形成离子注入的P井离子注入掩膜层101，接着在300K~1000K 的温度下进行Al离子注入，注入形成第二P型掺杂井区72，同时由于碳化硅中进行Al离子注入会横向散射，因此在所述第二P型掺杂井区72的左右两侧将同时形成浓度横向渐变的P型掺杂散射区域，分别为第一P型掺杂井区71和第三P型掺杂井区73，注入完成后去除掩膜层，并且完成表面清洗；
步骤2：淀积氧化层，光刻后形成离子注入的N型源区离子注入掩膜层102，接着在300K~1000K 的温度下进行P离子注入，注入形成第一N型掺杂源区81和第二N型掺杂源区82。注入完成后去除掩膜层，并且完成表面清洗；
步骤3：淀积氧化层，光刻后形成离子注入的P型源区离子注入掩膜层103，接着在300K~1000K 的温度下进行Al离子注入，注入形成P型掺杂源区9，注入完成后去除掩膜层，并且完成表面清洗；
步骤4：淀积氧化层，光刻后形成沟槽刻蚀阻挡层104，接着对N型掺杂碳化硅外延层3进行反应离子刻蚀形成沟槽；
步骤5：在300K~1000K 的高温下进行Al离子注入，在沟槽底部形成第二P型掺杂埋层42和第三P型掺杂埋层43，注入完成后去除沟槽刻蚀阻挡层104；
步骤6：覆盖碳帽，并且在1600℃以上的高温下进行退火，激活注入的杂质，热氧化形成第一栅氧化层51和第二栅氧化层52，接着淀积多晶硅，并刻蚀形成第一多晶硅61和第二多晶硅62；
步骤7：淀积氧化层，光刻形成层间介质10；
步骤8：淀积Ni合金，退火形成金属硅化物，接着正面淀积Al形成源极金属，器件的背面溅射形成Ni合金，退火形成背面欧姆接触合金1。
 有益效果
与现有技术相比，本发明的有益效果是：
本发明采用了沟槽加P型埋层的结构，充分减小了器件的密勒电容，从而降低了器件的开关损耗。此外，P型埋层的加入削弱了沟槽底部及拐角处的电场集中，提高了器件的长期可可靠性；
本发明单片集成了栅控二极管，该栅控二极管为沟槽结构，并且其沟槽和MOSFET的沟槽同时形成不需要额外的工艺步骤。该栅控二极管是一种基于MOSFET二极管接法的整流器，相比于传统MOSFET的体二极管，该整流器具有导通压降低、单极导通（无反向恢复电流、无双击退化）的优点，这是的此整流器可以用作MOSFET的续流二极管，大幅度降低了动态损耗。此外，栅控二极管的加入也削弱了MOSFET沟槽底部及拐角处的电场强度，从而提高了器件的长期可靠性；
本发明利用Al离子注入时的散射效应形成MOSFET和栅控二极管的沟道，采用这种做法可以在保障P型井区电荷总量足够的情况下降低器件的沟道区掺杂浓度。对于MOSFET，我们可以控制沟槽与P型掺杂井区的相对位置来控制沟道区掺杂浓度，从而精确控制其阈值电压。对于栅控二极管，我们可以控制沟槽与P型掺杂井区的相对位置来控制沟道区掺杂浓度，从而调整栅控二极管的导通压降。
在例如半桥或者全桥应用中，碳化硅MOSFET通常需要反向并联碳化硅肖特基二极管进行续流。采用本发明可以避免额外的续流二极管并联。
 附图说明
图1 为本发明的集成高速续流二极管的沟槽碳化硅MOSFET结构示意图。
图2 为本发明实施例2步骤1中P型掺杂井区离子注入示意图。
图3 为本发明实施例2步骤2中N型掺杂源区离子注入示意图。
图4 为本发明实施例2步骤3中P型掺杂源区离子注入示意图。
图5 为本发明实施例2步骤4中沟槽刻蚀示意图。
图6 为本发明实施例2步骤5中P型掺杂埋层离子注入示意图。
图7 为本发明实施例2步骤6中栅氧化层形成以及多晶硅填充刻蚀示意图。
图8 为本发明实施例2步骤7中光刻形成层间介质示意图。
图9 为本发明实施例2步骤8中正面欧姆接触合金和背面金属形成示意图。
图10 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET正向导通时的等效电路示意图。
图11 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET反向续流时的等效电路示意图。
1为背面欧姆接触合金，2为N型掺杂碳化硅衬底，3为N型掺杂碳化硅外延层，41为第一P型掺杂埋层，42为第二P型掺杂埋层，43为第三P型掺杂埋层，51为第一栅氧化层，52为第二栅氧化层，61为第一多晶硅，62为第二多晶硅，71为第一P型掺杂井区，72为第二P型掺杂井区，73为第三P型掺杂井区，81为第一N型掺杂源区，82为第二N型掺杂源区，9为P型掺杂源区，10为层间介质，11为正面欧姆接触合金，101为P井离子注入掩膜层，102为N型源区离子注入掩膜层，103为P型源区离子注入掩膜层，104为沟槽刻蚀阻挡层。
 本发明的实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
实施例1
如图1所示，本实施例提供一种集成高速续流二极管的沟槽碳化硅MOSFET，包括背面欧姆接触合金1，N型掺杂碳化硅衬底2，N型掺杂碳化硅外延层3，第一P型掺杂埋层41，第二P型掺杂埋层42，第三P型掺杂埋层43，第一栅氧化层51，第二栅氧化层52，第一多晶硅61，第二多晶硅62，第一P型掺杂井区71，第二P型掺杂井区72，第三P型掺杂井区73，第一N型掺杂源区81，第二N型掺杂源区82，P型掺杂源区9，层间介质10，正面欧姆接触合金11；
在x轴和y轴构成的平面上，所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方；所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方；所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3的右上方；所述第三P型掺杂埋层43位于所述N型掺杂碳化硅外延层3的左上方；所述第一栅氧化层51位于所述第二P型掺杂埋层42的上方；所述第二栅氧化层52位于所述第三P型掺杂埋层43的上方；所述第一多晶硅61位于所述第一栅氧化层51的右上方；所述第二多晶硅62位于所述第二栅氧化层52的左上方；所述第一N型掺杂源区81位于所述第一栅氧化层51的左上方；所述P型掺杂源区9位于所述第一N型掺杂源区81的左侧；所述第二N型掺杂源区82位于所述P型掺杂源区9的左侧，并且与第二栅氧化层52的右侧相接；所述第一P型掺杂井区71位于所述第一N型掺杂源区81下方，且位于所述第一栅氧化层51的左侧；所述第二P型掺杂井区72位于所述第一N型掺杂源区81、P型掺杂源区9和第二N型掺杂源区82的下方，并且位于所述第一P型掺杂井区71左侧；所述第三P型掺杂井区73位于所述第二N型掺杂源区82下方，并且位于所述第二P型掺杂井区72左侧；所述层间介质10位于所述第一N型掺杂源区81、第一栅氧化层51、第一多晶硅61的上方；所述正面欧姆接触合金11位于所述层间介质10、第一N型掺杂源区81、P型掺杂源区9、第二N型掺杂源区82、第二栅氧化层52、第二多晶硅62的上方；
在y轴和z轴构成的平面上，所述N型掺杂碳化硅衬底2位于所述背面欧姆接触合金1的上方；所述N型掺杂碳化硅外延层3位于所述N型掺杂碳化硅衬底2上方；所述第一P型掺杂埋层41位于所述N型掺杂碳化硅外延层3内部右上方；所述第二P型掺杂埋层42位于所述N型掺杂碳化硅外延层3内部左上方；所述第一栅氧化层51位于所述第一P型掺杂埋层41、N型掺杂碳化硅外延层3、第二P型掺杂埋层42上方；所述第一多晶硅61位于所述第一栅氧化层51的上方；所述层间介质10位于所述第一多晶硅61的上方；所述第正面欧姆接触合金11位于所述层间介质10的上方。
所述N型掺杂碳化硅外延层3的掺杂浓度范围为1E15cm -3~ 1E17cm -3；
所述第一P型掺杂井区71为Al离子注入时横向散射形成的，其浓度延x轴的负方向逐渐降低，且第一P型掺杂井区71靠近所述第一栅氧化层51处的浓度范围为1E14cm -3~ 1E16cm -3。
所述第三P型掺杂井区73为Al离子注入时横向散射形成的，其浓度延x轴的正方向逐渐降低，且第三P型掺杂井区73靠近所述第二栅氧化层52处的浓度范围为0 ~ 1E15cm -3。
本发明的集成高速续流二极管的沟槽碳化硅MOSFET，当器件正常工作时右边MOSFET区域的栅极被施加以正向偏置电压，沟道开启，电子在电场的作用下从源极流向漏极，形成自漏极向源极的电流I ds，如图10所示，图10 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET正向导通时的等效电路示意图；当器件关断进入第三象限工作状态时，源极到漏极的正电势差使得二极管区域导通，形成自源极至漏极的电流I sd，如图11所示，图11 为本发明实施例1的集成高速续流二极管的沟槽碳化硅MOSFET反向续流时的等效电路示意图。
实施例2
如图2至图9所示，本实施例提供一种集成高速续流二极管的沟槽碳化硅MOSFET的制备方法，包括以下步骤：
步骤1：N型碳化硅外延片上淀积氧化层，光刻后形成离子注入的P井离子注入掩膜层101，接着在300K~1000K 的温度下进行Al离子注入，注入形成第二P型掺杂井区72，同时由于碳化硅中进行Al离子注入会横向散射，因此在所述第二P型掺杂井区72的左右两侧将同时形成浓度横向渐变的P型掺杂散射区域，分别为第一P型掺杂井区71和第三P型掺杂井区73，得到如图2结构。注入完成后去除掩膜层，并且完成表面清洗；
步骤2：淀积氧化层，光刻后形成离子注入的N型源区离子注入掩膜层102，接着在300K~1000K 的温度下进行P离子注入，注入形成第一N型掺杂源区81和第二N型掺杂源区82，得到如图3结构。注入完成后去除掩膜层，并且完成表面清洗；
步骤3：淀积氧化层，光刻后形成离子注入的P型源区离子注入掩膜层103，接着在300K~1000K 的温度下进行Al离子注入，注入形成P型掺杂源区9，得到如图4结构。注入完成后去除掩膜层，并且完成表面清洗；
步骤4：淀积氧化层，光刻后形成沟槽刻蚀阻挡层104，接着对N型掺杂碳化硅外延层3进行反应离子刻蚀形成沟槽；得到如图5结构；
步骤5：在300K~1000K 的高温下进行Al离子注入，在沟槽底部形成第二P型掺杂埋层42和第三P型掺杂埋层43，得到如图6结构。注入完成后去除沟槽刻蚀阻挡层104；
步骤6：覆盖碳帽，并且在1600℃以上的高温下进行退火，激活注入的杂质，热氧化形成第一栅氧化层51和第二栅氧化层52，接着淀积多晶硅，并刻蚀形成第一多晶硅61和第二多晶硅62；得到如图7结构；
步骤7：淀积氧化层，光刻形成层间介质10；得到如图8结构；
步骤8：淀积Ni合金，退火形成金属硅化物，接着正面淀积Al形成源极金属，器件的背面溅射形成Ni合金，退火形成背面欧姆接触合金1。得到如图9结构。

Claims (5)

  1. 一种集成高速续流二极管的沟槽碳化硅MOSFET，其特征在于：包括背面欧姆接触合金（1），N型掺杂碳化硅衬底（2），N型掺杂碳化硅外延层（3），第一P型掺杂埋层（41），第二P型掺杂埋层（42），第三P型掺杂埋层（43），第一栅氧化层（51），第二栅氧化层（52），第一多晶硅（61），第二多晶硅（62），第一P型掺杂井区（71），第二P型掺杂井区（72），第三P型掺杂井区（73），第一N型掺杂源区（81），第二N型掺杂源区（82），P型掺杂源区（9），层间介质（10），正面欧姆接触合金（11）；
    在x轴和y轴构成的平面上，所述N型掺杂碳化硅衬底（2）位于所述背面欧姆接触合金（1）的上方；所述N型掺杂碳化硅外延层（3）位于所述N型掺杂碳化硅衬底（2）上方；所述第二P型掺杂埋层（42）位于所述N型掺杂碳化硅外延层（3）的右上方；所述第三P型掺杂埋层（43）位于所述N型掺杂碳化硅外延层（3）的左上方；所述第一栅氧化层（51）位于所述第二P型掺杂埋层（42）的上方；所述第二栅氧化层（52）位于所述第三P型掺杂埋层（43）的上方；所述第一多晶硅（61）位于所述第一栅氧化层（51）的右上方；所述第二多晶硅（62）位于所述第二栅氧化层（52）的左上方；所述第一N型掺杂源区（81）位于所述第一栅氧化层（51）的左上方；所述P型掺杂源区（9）位于所述第一N型掺杂源区（81）的左侧；所述第二N型掺杂源区（82）位于所述P型掺杂源区（9）的左侧，并且与第二栅氧化层（52）的右侧相接；所述第一P型掺杂井区（71）位于所述第一N型掺杂源区（81）下方，且位于所述第一栅氧化层（51）的左侧；所述第二P型掺杂井区（72）位于所述第一N型掺杂源区（81）、P型掺杂源区（9）和第二N型掺杂源区（82）的下方，并且位于所述第一P型掺杂井区（71）左侧；所述第三P型掺杂井区（73）位于所述第二N型掺杂源区（82）下方，并且位于所述第二P型掺杂井区（72）左侧；所述层间介质（10）位于所述第一N型掺杂源区（81）、第一栅氧化层（51）、第一多晶硅（61）的上方；所述正面欧姆接触合金（11）位于所述层间介质（10）、第一N型掺杂源区（81）、P型掺杂源区（9）、第二N型掺杂源区（82）、第二栅氧化层（52）、第二多晶硅（62）的上方；
    在y轴和z轴构成的平面上，所述N型掺杂碳化硅衬底（2）位于所述背面欧姆接触合金（1）的上方；所述N型掺杂碳化硅外延层（3）位于所述N型掺杂碳化硅衬底（2）上方；所述第一P型掺杂埋层（41）位于所述N型掺杂碳化硅外延层（3）内部右上方；所述第二P型掺杂埋层（42）位于所述N型掺杂碳化硅外延层（3）内部左上方；所述第一栅氧化层（51）位于所述第一P型掺杂埋层（41）、N型掺杂碳化硅外延层（3）、第二P型掺杂埋层（42）上方；所述第一多晶硅（61）位于所述第一栅氧化层（51）的上方；所述层间介质（10）位于所述第一多晶硅（61）的上方；所述第正面欧姆接触合金（11）位于所述层间介质（10）的上方。
  2. 根据权利要求1所述的集成高速续流二极管的沟槽碳化硅MOSFET，其特征在于：所述N型掺杂碳化硅外延层（3）的掺杂浓度范围为1E15cm -3 ~ 1E17cm -3。
  3. 根据权利要求1所述的集成高速续流二极管的沟槽碳化硅MOSFET，其特征在于：所述第一P型掺杂井区（71）为Al离子注入时横向散射形成的，其浓度延x轴的负方向逐渐降低，且第一P型掺杂井区（71）靠近所述第一栅氧化层（51）处的浓度范围为1E14cm -3 ~ 1E16cm -3。
  4. 根据权利要求1所述的集成高速续流二极管的沟槽碳化硅MOSFET，其特征在于：所述第三P型掺杂井区（73）为Al离子注入时横向散射形成的，其浓度延x轴的正方向逐渐降低，且第三P型掺杂井区（73）靠近所述第二栅氧化层（52）处的浓度范围为0 ~ 1E15cm -3。
  5. 一种权利要求1至4任意一项所述的集成高速续流二极管的沟槽碳化硅MOSFET的制备方法，其特征在于包括以下步骤：
    步骤1：N型碳化硅外延片上淀积氧化层，光刻后形成离子注入的P井离子注入掩膜层（101），接着在300K~1000K 的温度下进行Al离子注入，注入形成第二P型掺杂井区（72），同时由于碳化硅中进行Al离子注入会横向散射，因此在所述第二P型掺杂井区（72）的左右两侧将同时形成浓度横向渐变的P型掺杂散射区域，分别为第一P型掺杂井区（71）和第三P型掺杂井区（73），注入完成后去除掩膜层，并且完成表面清洗；
    步骤2：淀积氧化层，光刻后形成离子注入的N型源区离子注入掩膜层（102），接着在300K~1000K 的温度下进行P离子注入，注入形成第一N型掺杂源区（81）和第二N型掺杂源区（82），注入完成后去除掩膜层，并且完成表面清洗；
    步骤3：淀积氧化层，光刻后形成离子注入的P型源区离子注入掩膜层（103），接着在300K~1000K 的温度下进行Al离子注入，注入形成P型掺杂源区（9），注入完成后去除掩膜层，并且完成表面清洗；
    步骤4：淀积氧化层，光刻后形成沟槽刻蚀阻挡层（104），接着对N型掺杂碳化硅外延层（3）进行反应离子刻蚀形成沟槽；
    步骤5：在300K~1000K 的高温下进行Al离子注入，在沟槽底部形成第二P型掺杂埋层（42）和第三P型掺杂埋层（43），注入完成后去除沟槽刻蚀阻挡层（104）；
    步骤6：覆盖碳帽，并且在1600℃以上的高温下进行退火，激活注入的杂质，热氧化形成第一栅氧化层（51）和第二栅氧化层（52），接着淀积多晶硅，并刻蚀形成第一多晶硅（61）和第二多晶硅（62）；
    步骤7：淀积氧化层，光刻形成层间介质（10）；
    步骤8：淀积Ni合金，退火形成金属硅化物，接着正面淀积Al形成源极金属，器件的背面溅射形成Ni合金，退火形成背面欧姆接触合金（1）。
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