CN114551373A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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Publication number
CN114551373A
CN114551373A CN202210064930.8A CN202210064930A CN114551373A CN 114551373 A CN114551373 A CN 114551373A CN 202210064930 A CN202210064930 A CN 202210064930A CN 114551373 A CN114551373 A CN 114551373A
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China
Prior art keywords
wiring
semiconductor package
terminal
insulating structure
semiconductor chip
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CN202210064930.8A
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English (en)
Inventor
林直毅
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Rely On Technology Japan Co
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Rely On Technology Japan Co
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Publication of CN114551373A publication Critical patent/CN114551373A/zh
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Abstract

本发明提供在半导体器件的芯片两面上形成的电极与布线之间构筑热可靠性高的接合的接合方法。本发明的半导体封装件的制造方法包括以下步骤：以夹持接合膜的方式将半导体芯片接合于第一基板；在上述半导体芯片上形成第一绝缘膜；在上述第一绝缘膜中形成第一通孔；以通过上述第一通孔与上述半导体芯片电连接的方式在上述第一绝缘膜上形成第一布线；在上述接合膜中形成第二通孔；以及以通过上述第二通孔与上述半导体芯片电连接的方式在上述半导体芯片之下形成第二布线。

Description

半导体封装件及其制造方法
技术领域
本发明涉及半导体封装件，例如安装有功率半导体器件的半导体封装件及其制造方法。
背景技术
功率半导体器件是以电力的转换和控制为基本功能的半导体器件。上述功率半导体器件不仅在针对家电或OA(办公自动化)设备所用的逆变器或小型电机中的应用上起到重要的作用，而且还在司掌发电厂的电力系统、在电车或汽车等的电机驱动系统等中的电力转换或控制方面起到重要的作用。作为功率半导体器件的代表性器件，可以举出例如具有pn结二极管结构或肖特基势垒二极管结构的整流二极管、金属氧化物半导体场效应晶体管(MOSFET，Metal Oxide Semiconductor Field Effect Transistor)等的功率晶体管及晶闸管等。如在日本特表2012-164817号公报、日本特开平9-74193号公报及日本特开2001-352009号公报中所公开的，通常的功率半导体器件被作为在上面和下面具有一个或更多的电极(端子)的半导体芯片(以下也称为芯片)而供给，并且在芯片的上表面和下表面两者上构筑布线，通过布线与外部电源或其他器件电连接。
发明内容
在本发明的一个实施方式中，半导体封装件包括：半导体芯片；第一绝缘膜，用于将半导体芯片埋入，且具有第一通孔(via)；第一布线，位于半导体芯片上，且通过第一通孔与半导体芯片电连接；接合膜，位于半导体芯片之下，且具有第二通孔；以及第二布线，位于接合膜下，且通过第二通孔与半导体芯片电连接，其中，第一绝缘膜所包括的材料与接合膜所包括的材料互不相同。
半导体芯片可以在半导体芯片之下和之上分别具有第一端子和第二端子，半导体芯片可以分别通过第一端子和第二端子与第二布线和第一布线电连接。
半导体封装件可以在第一绝缘膜内具有第三通孔，也可以具有位于第一绝缘膜之下、且通过第三通孔与第一布线电连接的第三布线。第一布线与第三布线可以在第三通孔中相连接。第二布线和第三布线可以存在于同一层内。
第一通孔、第二通孔和第三通孔的大小可以互不相同。接合膜还可以具有多个通孔。
接合膜可以包括绝缘材料。
半导体封装件还可以在第一布线上具有基板。
在本发明的一个实施方式中，半导体封装件的制造方法包括以下步骤：以夹持接合膜的方式将半导体芯片接合于第一基板；在半导体芯片上形成第一绝缘膜；在第一绝缘膜中形成第一通孔；以通过第一通孔与半导体芯片电连接的方式在第一绝缘膜之上形成第一布线；在接合膜中形成第二通孔；以及以通过第二通孔与半导体芯片电连接的方式在半导体芯片之下形成第二布线。
在半导体封装件的制造方法中，半导体芯片可以在上述半导体芯片之下和之上分别具有第一端子和第二端子，可以以分别通过第二端子和第一端子与半导体芯片电连接的方式形成第一布线和第二布线。
在半导体封装件的制造方法中，可以与在第一绝缘膜中与第一通孔同时地形成第三通孔，可以以掩埋第三通孔的方式形成第一配线。可以与第一布线电连接的方式，在第三通孔之下与第二布线同时地形成第三布线。
在半导体封装件的制造方法中，第一通孔、第二通孔和第三通孔的大小可以互不相同。可以以贯通上述第一基板的方式形成第二通孔。可以以在接合膜上具有多个通孔的方式形成第二通孔。
在半导体封装件的制造方法中，接合膜可以包括绝缘材料。第一绝缘膜所包括的材料可以与接合膜所包括的材料不同。
在半导体封装件的制造方法中，第一基板可以具有开口部和贯通开口部的布线，并可以以通过第三通孔与布线电连接的方式形成第一布线。
附图说明
图1A至图1C为本发明的一个实施方式的半导体封装件的剖视示意图。
图2为本发明的一个实施方式的半导体封装件的剖视示意图。
图3A至图3E为示出本发明的一个实施方式的半导体封装件的制造方法的图。
图4A至图4D为示出本发明的一个实施方式的半导体封装件的制造方法的图。
图5为示出本发明的一个实施方式的半导体封装件的制造方法的图。
图6A至图6D为示出本发明的一个实施方式的半导体封装件的制造方法的图。
图7A至图7D为示出本发明的一个实施方式的半导体封装件的制造方法的图。
图8A和图8B为示出本发明的一个实施方式的半导体封装件的制造方法的图。
(附图标记的说明)
100：第一基板；105：第二基板；110：接合膜；120：半导体芯片；
122：第一端子；124：第二端子；126：第二端子；130：第一绝缘膜；
135：第二绝缘膜；142：第一通孔；144：第一通孔；146：第三通孔；
148：第三通孔；150：第一布线层；152：第一布线；154：第一布线；
156：第一布线；160：第二通孔；170：第二布线；172：第三布线；
174：第三布线；175：第二布线层；180：抗蚀层；200：第一基板；
202：基板布线；204：基板布线；210：接合膜；220：半导体芯片；
222：第一端子；224：第二端子；226：第二端子；230：第一绝缘膜；
235：第二绝缘膜；242：第一通孔；244：第一通孔；246：第三通孔；
248：第三通孔；250：第一布线层；252：第一布线；254：第一布线；
260：第二通孔；270：第二布线；272：第三布线；274：第三布线；
275：第二布线层；280：抗蚀层
具体实施方式
以下，参照附图对本发明的各实施方式进行说明。但是，本发明可以在不脱离其主旨的范围内以各种方式来实施，因此不局限于以下例示的实施方式的记载内容来解释。
另外，为了更加明确地进行说明，与实际的实施方式相比，附图存在示意性地示出各部位的宽度、厚度及形状等的情况，但附图只是一个示例，并不限定本发明的解释。另外，在本发明的说明书和各附图中，对于与针对已有的附图已说明了的要素具备同样的功能的要素，赋予相同的附图标记，省略重复说明。
在本发明中，在加工某一个膜而形成了多个膜的情况下，这些多个膜可以具有不同的功能及作用。然而，这些多个膜源自于在同一工序中作为同一层而形成的膜。因此，这些多个膜定义为存在于同一层的膜。
即使是与以下记载的各实施方式的形态所带来的效果不同的其他效果，但基于本发明的说明书的记载而显而易见的效果、或者本发明所属领域的普通技术人员容易地预测到的效果，当然应理解为本发明所带来的效果。
(第一实施方式)
在本实施方式中，利用图1A对本发明的一个实施方式的半导体封装件的结构进行说明。
半导体封装件包括半导体芯片120。在半导体芯片120中，在芯片两面的至少一方形成有端子(引出电极)。在图1A中描绘了半导体芯片120具有第一端子122和两个第二端子124、126的示例。
半导体封装件在半导体芯片120上具有第一绝缘膜130，并形成为将半导体芯片120及第二端子124、126埋入。第一绝缘膜130保护半导体芯片120，并且具有通过对半导体封装件赋予物理强度而使得半导体封装件自身的处理操作变得容易的功能。
第一绝缘膜130具有通孔(开口部)。具体而言，第一绝缘膜130在与第二端子124、126重叠的区域中具有第一通孔142、144。此外，第一绝缘膜130在半导体芯片120的附近且不与半导体芯片120重叠的区域中具有第三通孔146、148。第一通孔142、144分别达到第二端子124、126，并且第三通孔146、148贯通了第一绝缘膜130。
半导体封装件在第一绝缘膜130上具有第一布线152、154。第一布线152设置为将第一通孔142和第三通孔146埋入，另一方面，第一布线154设置为将第一通孔144和第三通孔148埋入。第一布线152、154的一部分与第一绝缘膜130的上表面相接。第一布线152、154分别通过第二端子124、126与半导体芯片120电连接。如下所述，可以利用电解镀法或金属导电膏(以下称金属膏)等形成第一布线152或第一布线154。
图1A所示的半导体封装件还可以隔着第二绝缘膜135在第一布线152、154之上具有基板(第二基板)105。第二绝缘膜135具有将第二基板105与第一布线152、154粘合的功能。第二基板105具有在保护半导体芯片120的同时向半导体封装件赋予物理强度的功能。另外，如下所述，当形成第二布线170或第三布线172、174时，第二基板105起到支承基板的作用。因此，根据本实施方式的半导体封装件不是一定要包括第二绝缘膜135或第二基板105，考虑到半导体封装件的物理强度或操作便利性，也可以不设置这些。
半导体封装件还在半导体芯片120之下具有接合膜110，接合膜110至少包括一个第二通孔160。此外，第二布线170以掩埋第二通孔160的方式设置于半导体芯片120、接合膜110之下。第二布线170通过第一端子122与半导体芯片120电连接。如下所述，可以利用电解镀法或金属膏等形成第一布线152、154。
接合膜110与第一绝缘膜130的材料可以不同。即，接合膜110所包括的材料与第一绝缘膜130所包括的材料可以互不相同。因此，包围第一通孔142、144的材料与包围第二通孔160的材料可以不同。
半导体封装件还在第三通孔146、148之下具有第三布线172、174。第一通孔142、144、第二通孔160和第三通孔146、148的大小(截面面积)可以互不相同。例如可以是第三通孔146、148最大，而第二通孔160最小。或者也可以是第一通孔142、144最小。
第三布线172与第一布线152电连接，第三布线174与第一布线154电连接。此外，第二布线170、第三布线172、174不是互相物理连接，而是互相分离，但是可以作为同一层而存在。如下所述，第二布线170、第三布线172、174可以利用电解镀法或金属膏等而形成。
半导体封装件还可以在第二布线170、第三布线172、174之下具有抗蚀层180。抗蚀层180具有保护第二布线170、第三布线172、174的端部的功能，另外例如抗蚀层180可具有与焊料(solder)之间的低的亲和性，从而能够使焊料选择性地与第二布线170、第三布线172、174相接触。
利用本实施方式的半导体封装件，能够针对设置于芯片的两面上的端子构筑布线，对于利用这些布线而设置于芯片的两面的端子，可以从芯片的单侧供给电信号。另外，对于芯片两面的端子可以采用相同的布线形成方法(例如电解镀法)。
一般，在安装在两面上具有端子的芯片的情况下，针对在芯片的上表面的端子，利用电解镀法形成布线。另一方面，芯片下表面的端子利用高熔点焊料或烧结金属(例如烧结银等)、或者诸如导电性的芯片粘接膜(DAF，die attach film)等的导电膜、或者利用基于接触的金属之间的扩散的连接(金属扩散接合)，而与设置于印刷布线基板等上的布线焊盘相接合。即，芯片的上表面与下表面的布线的形成方法不同。因此，在对上表面的端子形成布线时所不使用的例如芯片粘接装置等的装置是必须的，会导致工艺的复杂化、制造成本的增加。另外，关于利用高熔点焊料或烧成金属、导电膜的接合或者基于金属扩散接合的接合，由于热可靠性比较低，因此容易发生接合面剥离的现象，在接合面或其附近容易出现空隙(void)。
对此，如下所述，在本发明的实施方式之一的半导体封装件中，对于芯片两面的端子可以通过相同的方法构筑布线，因此在两面的端子之上可以利用相同的工序、相同的制造装置来形成布线。因此，能够简化制造工艺，并降低制造成本。另外，由于可以利用与芯片两面的端子相同的材料(例如铜)来形成布线，因此能够实现热可靠性高的接合。
(第二实施方式)
在本实施方式中，利用图1B对本发明的一个实施方式的半导体封装件的结构进行说明。本实施方式的半导体封装件在第二通孔160的结构不同的方面与第一实施方式不同。省略对于与第一实施方式相同的结构的描述。
如图1B所示，在本实施方式的半导体封装件中，可在接合膜110上设置单一的通孔(第二通孔160)。此外，可以以掩埋该通孔160的方式形成第二布线170。通过采用该结构，第一端子122与第二布线170之间的连接区域宽阔，能够大幅降低接触电阻。另外，能够促进芯片的散热。
(第三实施方式)
在本实施方式中，利用图1C对本发明的实施方式的半导体封装件的结构进行说明。本实施方式的半导体封装件在第三通孔146、148的结构不同的方面与第一实施方式、第二实施方式不同。对于与第一实施方式、第二实施方式相同的结构，将省略描述。
如图1C所示，在本实施方式的半导体封装件中，第三通孔146、148具有多种直径。即，第三通孔146、148具有开口面积不同的两个或更多区域。因此，第一布线152、154与第三布线172、174在第三通孔146、148内相连接。具有这种形状的第三通孔146、148可以以如下方式形成，例如以不贯通第一绝缘膜130的方式从第一绝缘膜130的上表面形成开口部，之后从第一绝缘膜130的下表面形成更大的开口部。通过采用上述结构，可以利用电解镀法更高效地埋入各通孔，另外在形成通孔时，能够大幅减少在通孔内产生的污迹(smear，俗称胶渣)。
(第四实施方式)
在本实施方式中，利用图2对本发明的实施方式的半导体封装件的结构进行说明。本实施方式的半导体封装件在具有多个半导体芯片120的方面与第一实施方式至第三实施方式不同。另外，在能够在芯片的上下构筑布线的方面与第一实施方式至第三实施方式不同。对于与第一实施方式至第三实施方式相同的结构，将省略描述。
如图2所示，本实施方式的半导体封装件具有两个半导体芯片120。此外，半导体芯片120的数量不限于两个，可以具有三个或更多半导体芯片120。半导体封装件还具有设置于第一绝缘膜130及半导体芯片120的第二端子124、126上的第一布线152、154、156，并且两个半导体芯片120利用第一布线154互相电连接。
在两个半导体芯片120之下，隔着具有第二通孔160的接合膜110，分别设置有第二布线170。另外，抗蚀层180形成为覆盖第一布线152、154、156及第二布线170的端部。另外，半导体封装件并非必须在半导体封装件两面都具有抗蚀层180，例如也可以仅在半导体封装件的下表面具有抗蚀层180。
第一布线152、154、156及第二布线170以相同的方法形成，例如利用电解镀法或金属膏来形成。因此，能够简化工艺，以低成本制造包括多个半导体芯片的半导体封装件。另外，可以赋予具有更高热可靠性的接合。在本实施方式的半导体封装件中，第一布线152、154、156用作在芯片的上表面开口的电极，另一方面，第二布线170用作在芯片的下表面开口的电极。因此，能够制造层叠有半导体封装件的高密度芯片安装基板。
(第五实施方式)
在本实施方式中，作为本发明的实施方式的半导体封装件的制造方法，利用图3A至3E、图4A至4D及图5，对图1A所示的半导体封装件的制造方法进行说明。
利用接合膜110将半导体芯片120接合于第一基板100上。作为第一基板100，可以利用由金属或玻璃、陶瓷、树脂等形成的基板。也可以利用在例如环氧类树脂等的树脂中混合有玻璃纤维等的基板。或者，也可以利用预先形成有布线的印刷基板等。或者，也可以利用在表面上设置有用铜等的金属薄膜夹持着薄的绝缘膜而成的膜的基板。
接合膜110只需具有接合第一基板100和半导体芯片120的功能即可。因此，可以利用以环氧树脂、聚酰亚胺、聚硅氧烷等有机材料为代表的绝缘材料等。作为绝缘材料，可以利用例如绝缘性DAF。但是，如下所述，由于在工序中第一基板100被剥离，因此，优选利用能够以物理或化学的方式剥离第一基板100的接合膜110。例如，可以将受光照射则接合性下降的接合剂用作接合膜110。
半导体芯片120可以为利用硅或镓、碳化硅及氮化镓等的半导体所具有的半导体特性的器件。例如可以举出整流二极管或晶体管等，也可以是以大电压大电流驱动的功率晶体管或晶闸管等的功率半导体器件。在半导体芯片120的芯片两面的至少一方形成有端子(引出电极)。在图3A中描述了具有第一端子122和两个第二端子124、126的示例。
以将半导体芯片120和第二端子124、126埋入的方式形成第一绝缘膜130(图3B)。第一绝缘膜130可以利用环氧类树脂或聚酰亚胺类树脂，并通过喷墨法或印刷法、旋涂法、浸渍法等的湿法制膜法来形成。或者，可以将绝缘性的膜配置于半导体芯片120之上，并利用层压加工等加热、压接来形成第一绝缘膜130。第一绝缘膜130的材料与接合膜110的材料可以不同。换言之，第一绝缘膜130所包括的材料与接合膜110所包括的材料可以不同，因此包围第一通孔142、144的材料与包围第二通孔160的材料可以不同。
之后，如图3C所示，在第一绝缘膜130上的与第二端子124、126重叠的区域中形成第一通孔142、144，使第二端子124、126露出。同时，在第一绝缘膜130上形成达到第一基板100的第三通孔146、148。第三通孔146、148可以大于第一通孔142、144，由此，能够将大的电流供给到半导体芯片120。第一通孔142、144及第三通孔146、148可以利用光刻或激光照射来形成。
接下来，在第一绝缘膜130之上以掩埋第一通孔142、144及第三通孔146、148的方式形成第一布线层150(图3D)。第一布线层150可以利用电解镀法或金属膏来形成。第一布线层150可以包含铜或金。在所形成的第一布线层150上进行蚀刻加工来去除不要的部分，形成第一布线152、154。第一布线152将第一通孔142和第三通孔146埋入，并且通过第二端子124与半导体芯片120电连接。另一方面，第一布线154将第一通孔144和第三通孔148埋入，并且通过第二端子126与半导体芯片120电连接。第一布线152和第一布线154并非直接连接，而是分离的。此外，第一布线152和第一布线154是通过加工第一布线层150而形成的，因此，这些布线存在于同一层内。
在利用电解镀法形成第一布线层150的情况下，第一通孔142、144及第三通孔146、148可能不会被金属充分埋入。在这种情况下，可以将金属膏用作补充材料。例如，可以在形成第一布线层150之前将金属膏涂敷于第一通孔142、144或第三通孔146、148的一部分来形成金属层，之后利用电解镀法形成第一布线层150。或者，也可以在形成第一布线层150之后，利用金属膏追加形成金属层。
接下来，剥离第一基板100(图4A)。可以通过施加物理力的方式，或者进行化学处理的方式来进行剥离。因此，第一基板100起到临时基板的作用。在剥离之后，根据需要可以利用蚀刻用显影液等对与第一基板100相接触的面进行清洁。
之后，隔着第二绝缘膜135将第二基板105形成于第一布线152、154之上。第二基板105可以使用与第一基板100同样的基板。第二基板105也可以直接使用所剥离的第一基板100，也可以新使用其他的基板。第二绝缘膜135可以使用与第一绝缘膜130同样的材料。
接下来，通过对接合膜110进行激光照射或者光刻来形成第二通孔160，使第一端子122露出(图4B)。在此，描述了形成多个第二通孔160且其大小小于第一通孔142、146，但是也可以形成单一的第二通孔160且其大小也可以大于第一通孔142、146。
接下来，利用例如电解镀法或者金属膏形成第二布线层175(图4C)。第二布线层175形成为掩埋第二通孔160，并与第一端子122相接触。对所形成的第二布线层175进行蚀刻加工来去除不要的部分，形成第二布线170和第三布线172、174(图4D)。第二布线170与第三布线172、174相互分离。第二布线170与第一端子122电连接，第三布线172与第一布线152电连接，第三布线174与第一布线154电连接。第二布线170、第三布线172、174均通过加工第二布线层175而形成，因此这些布线存在于同一层内。
与第一布线层150的形成同样地，也可以在形成第二布线层175之前，将金属膏涂敷于第二通孔160的一部分来形成金属层，之后利用电解镀法形成第二布线层175。或者，也可以在利用电解镀法形成第二布线层175之后，利用金属膏追加形成金属层。
之后，也可以在第二布线170与第三布线172、174之间形成抗蚀层180。抗蚀层180具有保护第二布线170、第三布线172、174的端部的功能，例如可以利用树脂，并利用湿法制膜法来形成。另外，在第二布线170、第三布线172、174上选择性地配置焊料的情况下，也可以将阻焊层(solder mask)等对焊料的亲和性低的材料用于抗蚀层180。之后，可以剥离第二基板105，相反也可以留下第二基板105。在作为第二基板105使用金属板的情况下，可通过在半导体封装件中留下第二基板105而将其用作散热板。
如上所述，在根据本发明的实施方式的半导体封装件的制造工序中，可以利用相同的方法(例如电解镀法)对芯片两面的端子构筑布线，因此可以利用相同的工序、相同的制造装置在两面的端子上形成布线。因此，能够简化制造工艺，并降低制造成本。另外，由于可以利用与芯片两面的端子相同的材料(例如铜)来形成布线，因此可实现热可靠性高的接合。
(第六实施方式)
在本实施方式中，对根据本发明的实施方式的半导体封装件的制造方法进行说明。具体而言，利用图6A至6D、图7A至7D、图8A、图8B对将形成有布线的基板用作第五实施方式中示出的第一基板的示例进行说明。对与第五实施方式相同的结构将省略说明。
在本实施方式中，作为第一基板200，使用预先形成有布线(基板布线)202、204的基板(例如印刷布线基板)(图6A)。在第一基板200上形成有贯通通孔208，并且设置有将贯通通孔208贯通的基板布线202、204。此外，在两个贯通通孔208之间设置有穿通孔206。穿通孔206至少有一个即可，但也可以设置有多个。
隔着接合膜210在第一基板200上接合包括第一端子222和第二端子224、226的半导体芯片220。此时，半导体芯片220以与穿通孔206重叠的方式进行接合(图6A)。接下来，以将半导体芯片220和第二端子224、226埋入的方式形成第一绝缘膜230(图6B)。半导体芯片220的固定方法及第一绝缘膜230的形成方法与第五实施方式同样。
与第五实施方式同样地，在第一绝缘膜230中形成第一通孔242、244及第三通孔246、248。之后，利用电解镀法或者金属膏以掩埋第一通孔242、244、第三通孔246、248的方式在第一绝缘膜230上形成第一布线层250(图6D)。进而，对第一布线层250进行蚀刻加工来形成第一布线252、254(图7A)。因此，第一布线252、254虽然相互分离但存在于同一层内。第一布线252通过第二端子224与半导体芯片220电连接，第一布线254通过第二端子226与半导体芯片220电连接。
之后，与第五实施方式同样地，在第一布线252、254上形成第二绝缘膜235(图7B)。虽然未图示，但还可以在第二绝缘膜235上形成基板。
之后，通过穿通孔206进行激光照射，在接合膜210上形成第二通孔260，而使第一端子222露出(图7C)。在此，设置有多个第二通孔260，但是也可以形成单一的第二通孔260。
之后，与第五实施方式同样地，利用电解镀法或金属膏，以与基板布线202、204、第一基板200重叠且掩埋第二通孔260的方式形成第二布线层275(图7D)，进而进行蚀刻加工来形成第二布线270、第三布线272、274(图8A)。也可以根据需要，在第二布线270与第三布线272、274之间形成抗蚀层280(图8B)。
如上所述，在根据本发明的实施方式的半导体封装件的制造工序中，可利用相同的方法(例如电解镀法)对芯片两面的端子构筑布线，因此可以利用相同的工序、相同的制造装置在两面的端子之上形成布线。因此，能够简化制造工艺，并降低制造成本。另外，由于可以利用与芯片两面的端子相同的材料(例如铜)来形成布线，因此可实现热可靠性高的接合。尤其是，不需要剥离第一基板200，并且不需要如在第五实施方式中那样在第一布线252、254上形成第二基板105，因此能够缩短工序。另外，由于可以对设置于贯通通孔208的基板布线202、204预先进行任意的设计，因此能够使用适合于流过大电流的基板。

Claims (20)

1.一种半导体封装件，包括：
半导体芯片；
绝缘结构，具有第一通孔，其中所述半导体芯片借由所述绝缘结构所覆盖且在所述绝缘结构中；
第一布线，位于所述半导体芯片上，且所述第一布线通过所述第一通孔与所述半导体芯片耦接；
接合膜，具有至少一个第二通孔且位于所述半导体芯片之下；以及
第二布线，位于所述接合膜下，且所述第二布线通过所述第二通孔与所述半导体芯片耦接；
第三通孔，位于所述绝缘结构中；以及
第三布线，位于所述绝缘结构之下，且通过所述第三通孔与所述第一布线耦接；
其中所述绝缘结构所包括的材料与所述接合膜所包括的材料互不相同，且所述第三布线与所述第二布线电绝缘。
2.根据权利要求1所述的半导体封装件，其中：
所述半导体芯片在所述半导体芯片之下和之上分别具有第一端子和第二端子，以及
所述半导体芯片分别通过所述第一端子和所述第二端子与所述第二布线和所述第一布线电连接。
3.根据权利要求2所述的半导体封装件，其进一步包括：
第三端子，设置在所述半导体芯片之上，且与所述第二端子电绝缘；
第四布线，位于所述半导体芯片之上，且通过在所述绝缘结构中的第四通孔与所述第三端子耦接；
第五通孔，位于所述绝缘结构中；以及
第五布线，位于所述绝缘结构之下，且通过所述第五通孔与所述第四布线耦接，其中：
所述第四通孔比所述第一通孔宽；
所述第五布线、所述第三布线以及所述第二布线存在于同一层内；以及
所述第一布线以及所述第四布线存在于同一层内。
4.根据权利要求1所述的半导体封装件，其中：
所述第二布线具有第一宽度；
所述半导体芯片具有第二宽度；以及
所述第一宽度大于所述第二宽度。
5.根据权利要求1所述的半导体封装件，其中：
所述第二布线以及所述第三布线存在于同一层内。
6.根据权利要求1所述的半导体封装件，其中：
所述第一布线包括电解镀覆的布线。
7.根据权利要求1所述的半导体封装件，其中：
所述接合膜的所述至少一个第二通孔的数量为多个；以及
所述第二布线重叠所述接合膜且延伸到多个所述第二通孔的每一者中以接触所述第一端子的部分。
8.根据权利要求1所述的半导体封装件，其进一步包括：
基板，包括穿通孔和基板布线，其中：
所述半导体芯片用所述接合膜接合到所述基板以重叠所述穿通孔；
所述接合膜进一步包括多个通孔；
所述穿通孔与所述多个通孔对齐；
所述第二布线是在所述基板之下且通过所述穿通孔和所述多个通孔与所述半导体芯片电连接；以及
所述第三布线通过所述基板布线和所述第三通孔与所述第一布线电连接。
9.根据权利要求1所述的半导体封装件，其中，所述接合膜为绝缘材料。
10.一种半导体封装件，包括：
半导体芯片；
顶表面；
底表面，与所述顶表面相对；
侧表面，在所述顶表面和所述底表面之间延伸；
第一端子，在所述顶表面处；以及
第二端子，在所述底表面处，所述第二端子比所述第一端子宽；
第一绝缘结构，嵌入所述半导体芯片，所述第一绝缘结构包括：
第一表面；
第二表面，与所述第一表面相对；
第一通孔，从所述第一表面延伸至所述第一端子；以及
第二通孔，从所述第一表面延伸到所述第二表面，所述第二通孔与所述第一通孔横向间隔开；
第一布线，在所述第一通孔中且耦合到所述第一端子，所述第一布线延伸以重叠所述第一绝缘结构的所述第一表面；
第二布线，邻近所述第一绝缘结构的所述第二表面且耦接所述第二端子；和
第三布线，邻近所述第一绝缘结构的所述第二表面且通过第二通孔耦接到所述第一布线。
11.根据权利要求10所述的半导体封装件，其进一步包括：
第二绝缘结构，在所述第一布线之上。
12.根据权利要求11所述的半导体封装件，其进一步包括：
基板，在所述第二绝缘结构之上。
13.根据权利要求11所述的半导体封装件，其中：
所述第二绝缘结构覆盖所述第一布线，使得所述第一布线没有部分暴露在所述半导体封装件之外。
14.根据权利要求10所述的半导体封装件，其进一步包括：
第二绝缘结构，在所述第二布线层和所述第三布线层之上。
15.根据权利要求14所述的半导体封装件，其中：
所述第二绝缘结构将所述第二布线与所述第三布线电绝缘；以及
所述第二绝缘结构包括第一开口与第二开口；
所述第二布线层由所述第一开口暴露；以及
所述第三布线层由所述第二开口暴露。
16.根据权利要求10所述的半导体封装件，其进一步包括：
接合层，在介于所述第二端子和所述第二布线层之间。
17.根据权利要求16所述的半导体封装件，其中：
所述接合层包括接合层通孔；以及
所述第二布线层通过所述接合层通孔与所述第二端子耦接。
18.根据权利要求10所述的半导体封装件，其中：
所述半导体芯片还包括位于所述顶表面处且与所述第一端子横向间隔开的第三端子；
所述第一绝缘结构包括从所述第一绝缘结构的所述上表面延伸至所述第三端子的第三通孔；
所述半导体封装件还包括第四布线，所述第四布线设置于所述第三通孔中且耦接至所述第三端子；以及
所述第三端子比所述第一端子宽。
19.根据权利要求18所述的半导体封装件，其中：
所述第一绝缘结构包括从所述第一绝缘结构的所述上表面延伸至所述下表面的第四通孔；
所述第四布线延伸至与所述第一绝缘结构的所述上表面重叠；以及
所述第四布线包括进一步设置在所述第四通孔内的镀覆层。
20.根据权利要求19所述的半导体封装件，其进一步包括：
第五布线，与所述第一绝缘层的所述下表面相邻，所述第五布线通过所述第四通孔与所述第四布线耦接。
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TW201731037A (zh) 2017-09-01
KR102638477B1 (ko) 2024-02-20
JP2017108041A (ja) 2017-06-15

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